Applied Materials, Inc. (AMAT) Earnings Call Transcript & Summary

Hello, and welcome to today's event. I'm Mike Sullivan, Head of Investor Relations at Applied Materials. Over the next few minutes, I'm going to introduce our 2022 Master Class series. The best place to start is with our demand thesis. As we've discussed in recent blogs, data is growing exponentially, fueled by new applications beyond PCs and mobility. We're now in the fourth era of computing, fueled by the Internet of Things, cloud computing and AI. At the same time, classic Moore's Law is slowing. This disconnect between the pace of data growth and the pace of transistor scaling is driving higher semiconductor and equipment spending across all semiconductor markets and nodes. The industry's technology response to the slowing of Moore's Law is a new playbook for driving continued improvements in chip performance, power consumption, area cost and time to market, which we call PPACt. In our 2022 Master Class series, we'll elaborate on key elements of the new playbook that will change the way chips are made in the years ahead. We'll forecast when these changes will happen and how we expect them to affect equipment spending. We'll also relate these changes to Applied's growth opportunities, both in our 2024 financial model time frame and beyond. Today's class is called New Ways to Shrink. We'll focus on the most obvious way to shrink, which is enabling EUV lithography. We'll also focus on a more subtle way to shrink called DTCO. We'll show you how new 3D structures like gate-all-around transistors and backside power distribution enable chipmakers to increase density in ways that go beyond lithographic scaling. And we'll show you how we can accelerate time-to-market of these new solutions using our eBeam metrology and AIx technology. In May, we plan to hold our second Master Class focusing on chip wiring, including the materials engineering breakthroughs our customers need as EUV reduces the space available for wiring. We'll go into the details of engineering backside power distribution, and we'll update you on advanced packaging which chipmakers and systems companies are using to help improve PPACt as Moore's Law slows. Finally, in the fall, we plan to hold our Subscriptions and Services Master Class. At our 2021 Investor Meeting, we set growth targets for our business under a range of WFE market levels. We hope the 2022 Master Classes will give you a better understanding of the inflections and the solutions that drive our growth expectations in semi systems and AGS. And here is today's agenda. In a moment, I'll pass the meeting over to Regina Freed, who will discuss new ways to continue classic 2D scaling by enabling and extending EUV. Next, Ofer Adan will discuss how Applied is using eBeam technology to help customers continue 2D scaling and solve etch placement errors. Then Dr. Uday Mitra will join us to talk about DTCO, including gate-all-around technology and backside power distribution. Finally, Dr. Raman Achutharaman will summarize how EUV enablement and DTCO will help Applied outperform our markets through 2024 and beyond. After today's presentations, we all look forward to taking your questions. And with that introduction, Regina, it's over to you.

Thanks, Mike. In today's Master Class, we're going to cover 2 ways to shrink. The 2 ways are summarized in a paper that one of our customers presented at last year's ISSCC Conference. On the left, intrinsic scaling refers to classic 2D Moore's Law. I'll focus on that part of the discussion. In the middle, DTCO stands for design technology co-optimization. This is a clever rearrangement of logic elements to enable further scaling independent of lithography pits. Uday will focus on this part of today's Master Class. And on the right, our customers state that in the future, about half the density improvements will come from intrinsic scaling and half will come from DTCO. Over the years, lithography advances and material engineering techniques evolve together to help us string features and increase density. Deep UV immersion lithography enabled 80-nanometer features. When the lithography road map stalled, the industry developed silver line double patterning and quadruple patterning to enable 40-nanometer features and then 20-nanometer features. EUV was a big step forward, giving us the ability to create 25-nanometer features with a single little pass. Today, we need even smaller features and EUV double patterning is already being used. For the future, high-end AUV is on the road map to replace EUV double patterning with a single little pass. On the materials engineering side, a number of changes need to be made to enable EUV scaling to continue. We call this EUV enablement and we'll discuss 7 of these innovations today. One, we need to change the materials used to transfer EUV patterns to the wafer. This is a change from spin-on hardmask to CVD hardmask. Two, we need a new kind of etch technology that can deposit and remove materials inside the same chamber to improve the quality of the lines made with EUV. Three, a new directional patterning technology can be used to extend the UV patterns to help increase EUV yields and reduce EUV costs. Four, we can also use this directional patterning technology to remove the bridge defects that occur as the lines made with EUV get closer together. Five, as my colleague Ofer will explain today, we need to use eBeam metrology in the after development and after-etch stages of EUV patterning to increase EUV pattern uniformity across the wafer. Six, we also need 3D eBeam metrology to control etch placement along the layers, which gets incredibly challenging as the critical layer shrink at EUV. And finally, I will explain how we use Applied's AIx technology to speed EUV process development and widen process windows to increase yields. Next, I'll give you a quick summary of the patterns we are making and shrinking with EUV. Modern patterning of the finest layers of a chip begins with uniform lines and spaces that run in a single direction. A second mask called a cut mask determines where the lines are segmented to help define individual features. So it's like the Fins on a FinFET transistor. A third mask defines the location of which are holes that can be filled with metal to connect one layer of the chip to the next. Precisely replicating and placing these lines, spaces and on each layer of the chip is critical to wafer yield and chip performance and power. With each shrink, the challenge has increased. Now let's get specific about how we transfer mask patterns to the wafer. The little scanners and photons to the photomask. Photons are bounced off the mask and on to the photoresist, which absorbs the mask pattern, much like a photograph. The photoresist is developed which creates openings in specific locations so the desired pattern can be transferred to the next layer. The photoresist is measured to make sure the pattern is correct before it's etched into the reefer. This is called after-development inspection, or ADI. We look to make sure the critical dimensions of the pattern are uniform. We also check the overlay, making sure the pattern is correctly centered over the wafer. If the ADI looks good, we commit to etching the wafer. In fact, photoresist are far too delicate to withstand the etching that transfers the pattern to the wafer. So between the photoresist and the wafer, we deposit a transfer layer and a hardmask. The transfer layer is optimized to receive the pattern from the photoresist layer quickly and precisely before their etching fully erodes to photoresist. The hardmask receives the pattern from the transfer layer and is even more resilient. It's engineered to withstand the etching until the pattern is fully replicated in the wafer. Then the wafer is measured in a step called after-etch inspection or AEI. If all the material engineering is successful, then the ADI measurements from the photoresist and the AEI measurements from the wafer will be highly consistent. You'll notice that with EUV lithography, the photoresist layer is much thinner. There are 2 reasons for this: first, EUV has more than 10x fewer photons than DUV, so we need a thinner resist that can fully absorb the mask pattern using far fewer photons. Second, the EUV lines are very narrow. If the photoresist was thicker, then these lines, patterns could collapse. Now let's talk about the first inflection we're covering today, the transition from spin on partnering films to CVD films. Traditionally, the underlayer and hardmask are deposited using spin on deposition technology, which is fast and cost-effective. However, to enable further EUV scaling, we need to replace the spin on films with new films deposited using chemical vapor deposition or CVD. The emerging problem with spin on deposition films is they begin as a liquid and are inherently soft. Soft films are less resilient to etching. Also with spin-on techniques, it becomes difficult to control the film thickness with perfect uniformity across the entire wafer. CVD deposition has more available process variables and can be tuned to control the hardness and uniformity of the films across the 300-millimeter wafer. Today, we are introducing Stensar, a CVD advanced patterning film for EUV that is deposited with our precision system. Our Stensar films can be engineered for specific levels of resilience. Stensar films can also be tuned for the selectivity to specific gas chemistries. This helps further tune etching speed and EUV patent fidelity. Our Stensar films are used for both the underlayer and the hardmask. Today, we are seeing strong customer adoption of Stensar over spin-on films. Now let's talk about today's second EUV enablement inflection, which is about etch innovation. The lower number of photons in EUV creates what we call stochastic errors, which create variability in the photoresist and in the lines, spaces and vias being patterned. The smaller the EUV patterns, the larger the stochastic errors are as a proportion of the features we are trying to make. If these irregularities are transferred down to the wafer, we can have gaps in lines, which causes open circuits, resist between adjacent lines with cost shorts and etch placement errors between the various layers of the chips, which reduce yields. Importantly, we can use material engineering to correct stochastic errors and help enable EUV scaling to continue. I'll give you a great example. We've developed a special technology in our sensory etch systems that allows us to alternate between etching and depositing material within a single chamber. We use this to gently remove and deposit materials in the same chamber as we transfer the EUV pattern to the hardmask. This unique approach average out pattern variation and creates more the features. Using it, we can actually heal stochastic errors before we add to the wafer. This animation shows you how our unique process works. [Presentation]

Personally, I think EUV is amazing and I think this ability to make EUV even better than material engineering is equally amazing. Applied Sym3 ad technology was originally targeted at memory applications. But today, we have very strong adoption in logic, particularly at the most advanced EUV nodes. The reason is reflected in the name. Sym3 provides symmetry in gas flow, plasma and wafer temperatures. And this helps us to tightly control the etch and deposition processes and achieve very even results across the wafer. The Sym3 chambers also have high conductance, meaning we can quickly remove all the etch byproducts on the chamber, which gives our customers higher yields. Raman will show you how quickly we are growing in the patterning etch market. Now let's talk about today's third inflection. We've developed an exciting technology that can help create patterns at a tighter than the resolution limit of EUV. What this means is we can give customers patterns that would otherwise require EUV multi-patterning. Our technology is called directional patterning and I'll give you one example of how it can be used. One of the most critical patterns is VS. We connect a metal wiring of one layer of the chip to the next. Lining these VS on top of one another with good etch placement is key to yield and also helps improve performance and power. Customers prefer elliptical VS because they are easier to land than smaller round of VS. To continue scaling with EUV, we need to get the tips of these VS as close together as possible. First, I'll describe how to create a desired pattern using EUV double patterning. We need to divide the pattern in half so that the via tips in each pattern are within the resolution of EUV. And we used 2 EUV exposures to transfer the entire pattern to the wafer. Using Applied's new approach, we create one mask that has all the layers, observing the tip-to-tip distances needed by EUV. Then we use our directional patterning technology to precisely extend the tips in both directions until the tip-to-tip placement is ideal. We have more ideas on how we can use directional patterning to extend 2D scaling below the limit of EUV. Customers are now evaluating our technology to extend 2D scaling while increasing yields and reducing EUV costs. Next, I'll quickly cover our fourth inflection. As EUV lines and spaces get narrower, we have more potential for bridge defects that cause shorts. Another promising use of our directional patterning technology is to remove unwanted material on the hardmask to heal the patterns before they are etched into the wafer, thereby increasing EUV yields. This capability is now being used to accelerate R&D and has the potential for volume production. Applied's directional patterning technology is unique in the industry, and we'll share more details over time to refine these new applications with our customers. As you have seen from these examples, there's a strong interdependence between lithography and materials engineering. The patterns on the EUV mask are not the patterns on the wafer, unless we tune all of the material deposition, modification and removal steps to ensure pattern fidelity on the wafer. The uniformity needs to be good locally, meaning within the chip, and across the wafer so that most of the chips yields regardless of the location. In the past, industry focused primarily on 2D pattern fidelity with techniques like holistic lithography that work on optical corrections, one layer at a time. So we continue to shrink features using EUV, increase the process steps on each layer and use more 3D design techniques we need to supplement through the optical techniques with 3D methods. Ofer will explain some of the new ways we are enabling further EUV scaling by supplementing 2D optical methods with eBeam. I'll close my section by explaining how we are applying the breadth of Applied's portfolio along with cutting-edge data science to extend 2D scaling into the future. With Applied's AIx technology platform, we are deploying hundreds of sensors in our chambers and systems to measure all of the process variables that can affect fidelity and uniformity. We've put metrology into our deposition system, so we can measure the quality and thickness of films as they are being created in vacuum. And we use PROVision eBeam metrology to measure the on-wafer results of all of these processes. Then we use AI analytics to tease out the optimum combination of process variables that produce the ideal on-wafer results using the widest possible process window. It's not just one layer at a time, it's holistic analysis of the interdependencies across all the critical layers. Solving this multi-dimension optimization challenge is key to faster time to market and higher yields in production. AIx is designed to accelerate process R&D by 2x and widen process windows by 30%. It's a very powerful new way to enable further EUV scaling and controlling materials engineering and etch placements. Thank you for listening. And now I'd like to hand the meeting over to Ofer to discuss the new eBeam inflection.

Thank you, Regina. To continue the 2D scaling road map, we need to ensure 3 things: first, we need to make sure the intended patterns on the EUV photomask are precisely replicated on the photoresist with proper feature centering and uniformity across the entire wafer. We performed after-development inspection or ADI, to find serious errors before etching the wafer. Second, we need to make sure the patterns we etch into the wafer are just as uniform. We used after-etch inspection or AEI, looking for a very high correlation between the ADI and the AEI measurements. Any inconsistencies introduce irregularities that can propagate as we continue to process the wafer. Third, we need to align the edges of the critical features of each layer of the chip with their opposite features on the layers above and below. Etch placement errors can ruin entire wafers or they can crop up in particular areas and negatively impact chip yield, power and performance. I'll show you how we are deploying eBeam technologies in each of these 3 areas. And later, Raman will show you how the eBeam inflection is driving growth of Applied Materials. Let's begin with after-development inspection or ADI. As Regina showed us, the EUV photoresist is much thinner than deep UV photoresists. If we used conventional eBeam systems and energies to look for stochastic defects and measure the critical dimensions and overlay, we could distort the patterns on the delicate resists. To help customers inspect more during ADI, we are preparing to introduce a new version of our VeritySEM that has unique capabilities for emerging EUV nodes. We use lower energies to minimize interaction with the resist. We also provide a unique technology that improves EUV pattern image resolution, giving us sharp, dark and light contrasts at low energy. Customers are already using this technology to ensure seed uniformity at emerging EUV nodes and to center the mean of the pattern variation across the wafer prior to etching. Next, let's discuss pattern fidelity, from development to etch. In easier times, if engineers properly centered the photoresist pattern of the wafer, they could usually count on good etch results as well. But as Regina explained earlier, EUV patterning introduces a number of intermediate steps. The photoresist pattern is etched into a transfer layer, then the transfer layer pattern is etched into a hardmask. And finally, the hardmask pattern is etched into the wafer. Each of these intermediate steps is a potential source for variation that can reduce pattern fidelity on the wafer, and this can cause serious ADI to AEI creation issues. To help with EUV scaling, engineers are now adding metrology steps using our PROVision eBeam metrology system, which is 10 times faster than SEM metrology. PROVision can generate data for each of these intermediate steps, giving process engineers biosignature data that they can use to holistically center the entire patterning flow. Engineers can quickly improve ADI to AEI correlation, identifying and correcting the issues before they result in scrapped wafers. This data can also be used with our AIx platform, creating feedback loops that can help customers tune their process technologies. Finally, let's talk about the most critical challenge, which is etch placement. Prior to EUV, etch placement was much easier. Features were larger, and if we align the optical scribe lines in the resist with the corresponding optical targets on the wafer, we could predict that the edges of the new features would be properly aligned with their opposite features on the previous layers. We could proceed one 2D layer at a time and make optical corrections along the way, producing uniform features from top to bottom. It's actually amazing that optical techniques have worked for so long. The optical proxy targets are at least 10x larger than the features we are creating with EUV. Also, iterative process steps like multi-patterning introduced variations and 3D designs create stress and interlayer distortions. Optical metrology and target-based approximation struggle to detect and diagnose these issues. As we continued to scale with EUV, engineers are encountering more situations when they're using all the optical techniques properly and still having etch placement errors. They are hitting blind spots that bring scaling to a halt. Today, most companies agree that we need to use eBeam metrology to complement optical metrology, but many of their efforts are still focused on diagnosing patterning failures one layer at a time and using the eBeam data to make optical corrections rather than solve the underlying process issues. Applied is driving a different approach we call 3D patterning control. The approach is designed to overcome the blind spots by measuring and addressing all the sources of etch placement error. The new 3D patterning control playbook has 3 elements: one, we supplement optical target approximation of patterns with actual on-device metrology using the eBeam; two, we supplement statistical sampling of a small number of locations with massive across wafer metrology; and three, we go beyond 2D one layer at a time approaches to 3D integrative approach that measures and addresses all of the critical layers as an integrated system. Applied's PROVision eBeam is especially designed for 3D patterning control. We use higher eBeam landing energies to penetrate the many layers of an advanced chip. Using our illuminative technology, we capture the back scanner, the electrons, and produced high-contrast images of the many interdependent features. The clear resulting images allow engineers to see and measure etch placements through all the critical layers all at the same time. PROVision measures all of the sources of etch placement errors, including overlay, seat uniformity and light with roughness. It also gives engineers the data they need to refine process recipes for a wide range of equipment, from litho, to etch, deposition, anneals and CMP. 3D patterning control can be used at different times for different purposes. In early R&D, there are cases where eBeam metrology is the only way to develop a new process with correct etch placement. Later, eBeam data can help in the transition from R&D to tool matching and high-volume ramp, while customers will continue to use optical methods to keep their processes inspect during high-volume production. eBeam can help quickly diagnosing and solving yield issues in HVM. If a manufacturer's optical control scheme has an excursion, it can take weeks to produce new masks with new proxy targets. Using actual on-device measurements with eBeam, customers can continue to process wafers in the meantime. Finally, our customers have collaborated with us to present papers at SPIE, the industry's top lithography conference, showing how the new patterning control playbook can be used to achieve higher yields faster. At last year's SPIE conference, Samsung and Applied demonstrated the use of eBeam SAM overlay and seat uniformity techniques to improve 3D etch placement and yield in logic devices. At the upcoming SPIE conference, Hynix and Applied will demonstrate similar etch placement and yield improvements in DRAM. In addition, IBM and Applied will present a paper on the new very recent technology for EUV photoresist metrology. Thank you for listening. And now I'd like to hand the meeting over to Uday.

Thank you, Ofer. At the beginning of today's Master Class, Regina showed the 2 ways we can continue to shrink. One is intrinsic scaling, where feature size and bit scaling increased density. The other is design technology co-optimization, or DTCO. Today, simply shrinking features creates major issues such as exponential increase in wiring resistance and increase in leakage current, which cannot be fixed by any lithographic process. As a result, DTCO is becoming a much larger contributor to the industry's scaling road map. When most of us think about Moore's Law, we remember the good old days of Dennard scaling, which worked until around the year 2000. Transistors were 2D and we shrunk their sizes by 50% every 2 years. We shrunk the gate that controls the on-off state of the transistor, and its length represented the node name, 130 nanometers, 90 nanometers, 65 nanometers and so on. We scaled the gate oxide proportionately. Dennard scaling gave us simultaneous improvements in performance, power and area cost or PPACt. From around 2000 through 2010, gate and gate oxide scaling hit limits. We entered a period of equivalent scaling. The gate length stayed at around 30 nanometers, and we used materials engineering to improve the performance and power. For example, we strained the silicon channel with epitaxy to increase performance. We switched from tin silicon dioxide to thicker high-k metal gates to reduce leakage and power consumption. In around 2010, we moved to FinFETs, which marked the change from planar 2D transistors to 3D transistors. The FinFET gate surrounded the transistors electrical channel on 3 sites, which enabled further improvements and performance and power. Typically, 3 Fins were used in each transistor to deliver enough current for fast operations within the logic cell. The logic cell is the minimum set of transistors and wiring needed to perform binary bullion operations like add, subtract and compare. We need a positive PMOS transistor and a negative NMOS transistor along with wiring for power and signals. Each cell requires isolation from neighboring cells. Today, we are in a new era where DTCO is driving as much as half of logic density scaling. I'm going to explain 2 new ways to shrink using DTCO. One is the backside power distribution network, and another is gate-all-around transistors. I'll explain why the industry is moving to gate-all-around and how these new transistors are made. Later, Raman will explain what these changes mean for Applied's business. It may seem counterintuitive to describe gate-all-around as a form of DTCO, but the goal of DTCO is to rearrange the layout of the logic cell in clever ways to increase the density independent of the lithographic pitch. And that's what gate-all-around helps us do. Gate-all-around also enables higher performance and performance per watt versus FinFET. Next, I'll provide some DTCO examples, beginning with some that are already in production. Here, we show the transition from double diffusion breaks, which isolate individual logic cells to single diffusion breaks. The large density advantage is obvious. Another example is FEN depopulation. We raised the fin heights and improved the uniformity to increase the drive current. And this allowed us to reduce the number of fins per transition from 3 to 2. A third example is contact over gate. Here, the gate contact to the logic cell is moved from the side of the fence to above the fence, thereby reducing the logic cell area. Now let's move to the emerging DTCO inflections. Customers are already talking about backside power distribution networks. Here's the general idea. Transistors and logic cells sit at the bottom of the wafer and the power is routed from above. There are 2 kinds of wires, tech power lines, which provide the current needed for the transistors to switch, and thin signal lines, which help determine when to switch. All of this wiring proceeds through each metal layer of the chip from top to bottom. At each metal layer of the chip, there's electrical resistance and some of the supply voltage is lost. It's a bit like using a large number of extension cords to get the power from the source to the cell. It wastes power and creates heat. So the emerging idea is to more efficiently route the thick power lines straight to the logic cells from the backside of the wafer. This approach explains the backside power naming convention. We believe the backside power distribution can reduce power consumption as much as 25%. The DTCO benefit is an increase in logic density ranging from around 6% to 30% depending on the approach. We'll go into more detail about how to engineer our backside power distribution in our next Master Class on chip wiring and advanced packaging. Now let's dive in to gate-all-around, which is one of the biggest and most important inflection since the FinFET. The industry will rearrange the elements of the transistor to increase density, independent of the lithographic pace. Its scaling may continue with gate-all-around, but it's unlikely to be very dramatic because we get scaling benefits from DTCO and because further shrinking the transistors and wiring can create electrical challenges that negatively affect performance and power. Conceptually, gate-all-around is like lifting a FinFET transistor and rotating it by 90 degrees. Instead of surrounding the channel on 3 sides as in FinFET, gate-all-around surrounds it on all 4 sides. The resulting channels are called nanowires, nanoribbons or nanosheets. I'll use nanosheets. From a DTCO perspective, the approach allows us to shrink the logic cells in the X and Y dimensions. Designers have new choices. They might aggressively reduce area cost while maintaining the performance of FinFETs, or they may choose to widen the nanosheets to increase drive current, thereby increasing performance as much as 25% and increasing density by around 25% as well. From a manufacturing perspective, gate-all-around borrows many of the proven processes used to make FinFETs, especially the ones that have a significant impact on performance and power. Selective FP is a prime example. There are also some critical new steps which I'll describe. I'll begin by describing how we create the channels, which is one of the key differences in gate-all-around versus FinFET. In FinFETs, the channel width is determined by lithography and etch. There tends to be variability and this variability impacts performance and power. In gate-all-around, we deposit alternating layers of silicon and silicon germanium using simple blanket epitaxy. These layers are etched to create individual rolls of nanosheets. Next, shallow tranches are formed to isolate individual transistors and a dummy gate is deposited. These processes are similar to those used in FinFETs. Then the source and drained regions of the nanosheets are etched, forming a cavity. Next, the exposed silicon germanium and the channel region is selectively recessed, and the recess is filled with a dialectic spacer. The newly created inner spacer reduces parasitic capacitance between the transistor gate and its contact. Then the source and drain regions are etched to create cavities with optimized profiles. These recesses are filled using a highly-precise selective epitaxy, one material for the negative NMOS region and another material for the positive PMOS region. With the source and drained regions now completed, we move to the central region of the channel. The dummy gate is removed, which exposes the channel, a highly selective process is used to revolve the silicon germanium from the nanosheets, leaving behind freestanding silicon channels. The precision of epitaxy and selective materials removal is the key to uniform silicon channels with superior performance and power characteristics. To complete the transistors, we deposit a highly engineered gate oxide stack. And finally, we deposit an equally sophisticated metal gate stack. Together, these elements control the drive current and the on-off state of the transistor. Now that we have the overall gate-all-around process flow, I'll comment on some of the particular steps. You have heard about 2 uses of epitaxy. First was the alternating silicon and germanium blanket epi used to form the nanosheet super latex. This is a simple nonselective epi. Later, I'll describe the 2 selective epi steps used in the source and drain regions of the PMOS and NMOS transistors. These are deposited using an integrated material solution that combines a number of unique steps in one vacuum system. The sequence begins with interface cleaning and lateral silicon shaping that maximizes channel strain and increases electron mobility and performance. These are followed by selective epitaxy steps that precisely grow silicon through the very narrow features that were etched previously. This epitaxial source strand engineering is slow but critical to device performance. There are also 2 new selective removal steps. First, we recessed the silicon germanium at the sorting regions by around 5 to 10 nanometers to isolate the gate from the source train and reduce capacitance. These lateral recesses need to be uniform and square. Selectivity is important because the removal chemistry makes contact with the neighboring silicon, low case spaces and shallow trench isolation oxide. A special challenge is ensuring a consistent silicon germanium recess across all of the structures being created. Applied has developed new metrology techniques that are co-optimized with a selective removal process to deliver precise recesses across the entire wafer. The second new step removes silicon germanium from the superlattice and leaves the freestanding silicon nanosheets in place. This is a very critical step because the width and uniformity of the nanosheets is key to transistor performance. This is also one of the key differences between FinFETs and gate-all-around. In FinFETs, the channel width is defined by litho and etch and it is difficult to control Fin variability. Epitaxy is a slower and more precise process, and we can carefully engineer the channel width and uniformity. Applied's epitaxial deposition of the silicon and silicon germanium nanosheets results in a very clean and clear interface. Our highly selective removal process removes the silicon germanium with extreme selectivity versus silicon. Next, I'll discuss the gate dielectric, which is now undergoing a major change. The gate dielectric surrounds the channel and it controls the transconductance, which is the current voltage characteristics of the device. In the Dennard scaling era, I discussed earlier, the gate dielectric was scaled to smaller physical dimensions as measured by the gate oxide thickness. The scaling allowed us to reduce the supply voltage and still produce a fast on-off switch. In the equivalent scaling era, physical scaling of the gate oxide stalled. However, we continued to engineer improvements in gate dielectric properties and introduced a new metric, equivalent oxide thickness. Over time, equivalent oxide thickness scaling also stalled and it has remained stalled for more than 5 years. Today, Applied is sampling a new integrated material solution that is designed to allow equivalent oxide scaling to resume. Our solution works in high vacuum and combines ALD deposition with special plasma and thermal treatments along with in-situ metrology. Our approach thins the gate oxide by 1.5 angstroms and reduces leakage current by more than 10x. The solution has already been demonstrated to improve FinFET transistor performance and is now being evaluated for gate-all-around. The last key materials engineering topic I'll address is the metal gate. Engineers tune their transistor designs with different threshold voltages to meet the performance per watt goals of specific computing markets, such as low-power mobile devices and high-performance servers. Metal ALD steps and treatments are used to help engineer these voltages and the thickness of the metal layers is key. High demand for performance tuning, coupled with increases in complexity, has driven a 3x increase in the related process steps since the 10-nanometer node. An untold story is that Applied has a strong market position in metal ALD. Our position is overlooked because our metal ALD chambers are integrated with the PVD platforms. And only our dielectric ALD revenue is reflected in third-party market reports. In gate-all-around, the metal gate engineering is more challenging because the space between the nanosheets is typically less than 10-nanometer, which is less than the space available in FinFET designs. Our solutions for gate-all-around include dipole engineering of the dialectic clear, which helps doing voltages without adding any volume. Next, we use ALD deposition in a high vacuum integrated material solution to deposit the ultrathin metal layers. Our integrated gate solution eliminates atmospheric contamination and enables us to precisely tune their transistor threshold voltages. Finally, I'd like to say a word about process control and the gate-all-around regime. The 3D design techniques result in critical features becoming deeply buried within other structures, making them very difficult to measure, control and inspect. We can use transmission electron microscopy to assess our progress, but the technique is destructive and slow. And it doesn't provide the massive data we ideally need to quickly assess alternatives and progress. A key tool in the gate-all-around era will be the technologies like Applied's PROVision eBeam metrology system, which has an illuminator technology. This technology allows us to penetrate deep inside the many layers of the gate-all-around device and collect the back scattered electrons to produce high-fidelity images and measurements. In fact, IMEC and Applied delivered a paper showing how PROVision can be used to control the silicon germanium recess step, which helps speed gate-all-around process development. to accelerate R&D in the gate-all-around era, Applied will go far beyond unit process systems, delivering co-optimized systems, integrated material solutions and AIx. With AIx, we can get the chamber sensor data, in-situ metrology data and massive on-wafer metrology data and then use analytics to converge on optimal solutions to this new engineering challenges. I hope I've left you excited about the promise of DTCO, including the backside power distribution network and gate-all-around, which is coming even sooner. The progress won't end with gate-all-around. Engineers are already thinking about new ways to rearrange transistor and logic cell elements to continue to scale independent of the lithography pitch. One idea is forksheets, where a dielectric wall is inserted between the NMOS and PMOS transistors so they can be brought closer together. And further out, we can imagine complementary effects whereby the NMOS and PMOS transistors are stacked vertically. Now I'd like to hand the meeting over to Raman.

Thanks, Uday. I hope you have enjoyed learning more about new ways to shrink and the new ways Applied will accelerate the road map with new products and technologies. As Mike said during the intro, we also want to relate these changes to our revenue growth targets, and that's what I will do today. In fact, some of these inflections are already generating revenue growth for us. Some will contribute more meaningfully between today and 2024, which is our financial target model horizon. Some will play out after 2024 and add to our longer-term growth opportunities. This is the 2024 financial model we introduced at our investor meeting last year, which is derived from our strategic plan. WFE spending in calendar 2020 was $61 billion. In our high scenario for 2024, WFE grows by around 63% versus 2020, reflecting annualized growth of around 13%. In the same scenario, our goal is to nearly double our semi systems revenue, growing at around 18% or about 1.5x the rate of the market. At the investor meeting, we shared that in 2020, over 55% of the semi systems revenue was in the PPACt enablement areas. Also, we said we expect to grow significantly faster in these areas through 2024. And that brings us to the 2022 Master Classes, where we are detailing the new playbook inflections and the specific products and technologies that will generate the growth for Applied. Today, we talked about 3 areas of the new playbook: Regina discussed new ways to shrink by enabling classic 2D scaling with EUV; Uday discussed new 3D structures like backside power distribution and gate-all-around that enable logic density improvements independent of lithography pitch; and Ofer described how we are accelerating R&D with eBeam and AIx. In a minute, I'll show you how we expect to grow at nearly twice the rate of the market in all of these areas combined. In our next Master Class, we'll go deeply into the new materials, especially new wiring inflections that will overcome the resistance challenges that our company EUV scaling, which show you how we expect to grow at 3x the rate of the market in this area. In fact, wiring inflection should be the biggest growth driver for Applied between now and 2024. We'll also give you an update on heterogenous design and heterogenous integration using advanced packaging, which helps the industry to advance all of the PPACt vectors as Moore's Law slows. Now let's take a deeper dive into the growth we are generating in the areas discussed in today's Master Class, beginning with Regina's topic of patterning. Our patterning opportunity is a sum of logic and DRAM customer spending for patterning steps in the process equipment markets we serve, which includes etch, CVD, CMP and thermal processes. Here, you can see that we have grown at a 35% CAGR in patterning from 2015 through 2020, which is twice the rate of our markets, achieving $1 billion in patterning revenue for the first time in 2020. In 2021, we grew by nearly 50% in patterning, outpacing our markets by more than 20 percentage points. We grew our patterning share from around 10% in 2015 to over 20% in 2020 and over 25% in 2021. Most of our growth has been generated in CVD, which is our patterning films, including stencil for logic and Draco for DRAM, and etch, which is our Sym3 product line. In fact, we have become #1 in DRAM conductor etch and we have been gaining strong etch share in the EUV inflection in growth DRAM and logic. The new directional patterning technology Regina discussed is a longer-term growth driver. Uday discussed backside power distribution, which is also a longer-term inflection, and gate-all-around, which will begin to ramp by 2024 and grow significantly over the longer term. Gate-all-around will increase Applied's market opportunity by more than $1 billion per 100,000 wafer starts of capacity. We expect to gain around 5 points of share in gate-all-around versus FinFET and capture the majority of the spending in our markets. Our gate-all-around opportunity includes 4 materials deposition technologies PVD, CVD, ALD and epi. In materials removal, we offer etch, selective removal and CMP. In materials modification, we participate in implant and thermal processing. The last area we compete is in process control. No other company has the breadth and our strategy is to combine our technologies in unique ways to give customers the best devices and the fastest time-to-market, including with the help of our AIx technology. This chart summarizes the epi market and gate-all-around. There are 2 major applications. Rapid blanket epi film deposition and precise selective epi growth. Applied's very first product was an epitaxy system and we have been the strong #1 supplier ever since. Turning to selective materials removal. This chart shows the growing adoption of this new technology in logic from limited use at 40-nanometer, the growth in success of FinFET nodes and significant adoption in gate-all-around. Like selective AP, selective removal is critical to gate-all-around transistors because it helps control channel width and uniformity, which have a direct bearing on chip power and performance. Applied was first to deliver selective materials removal to the industry with our Selectra product, and we are the market leader by far with over 1,000 chambers in the field. We're capturing the majority of selective etch positions in gate-all-around. Process control has been a significant growth driver for Applied over the past couple of years, and we expect to continue outgrowing the market as we address the limitations of optical metrology and accelerate time to market. We grew our PDC business by over 60% in calendar 2021, approaching $1.5 billion in revenue. Ofer talked about our VeritySEM product for EUV photoresist inspection and process centering. We more than doubled our VeritySEM revenue in 2021. Ofer also discussed how EUV patterning and etch placement challenges are driving the need for massive across wafer metrology and 3D metrology with PROVision. We nearly doubled our total eBeam revenue in 2021, surpassing $1 billion. In summary, Applied's strategy is to be the PPACt enablement company for our customers. We'll continue to pursue unit process leadership. But as the road map becomes increasingly complex, our strength is in our breadth and our ability to combine technologies in unique ways to help customers bring new processes and chips to market faster. Increasingly, our revenue comes from co-optimized systems and from integrated material solutions where we combine multiple technologies such as ALD, PVD and in-situ metrology in a single system under high vacuum. We are already generating more than 70% of our semi systems' revenue from these combinations. In the future, we'll further accelerate the t in PPACt with co-optimized metrology and AIx. I hope today's Master Class has given you the insights into the road map challenges, technology inflections and unique solutions we are bringing to our customers. Some of these solutions are giving us growth today and through the 2024 model horizon, and a number of them will be adopted beyond 2024 and give us further opportunities to outperform the market. Now I'd like to join my colleagues for our Q&A session, which shall begin in a moment.

Welcome to today's Q&A session. [Operator Instructions] Before we begin, I just wanted to let you know that you can find the materials related to today's event on the Events page of the IR section of our website. We've posted all of the slides, the transcript of our prepared remarks and copies of our press release in our blogs. Finally, if we don't get to everybody's questions by the end of the meeting, we'll follow up with you by e-mail. And now we will prepare to take our first question, and that is going to come from the line of C.J. Muse. C.J., if you could unmute, please.

Yes. Can you hear me?

We can. Thank you.

Perfect. I really appreciate all the great presentations. I guess 2 questions for you. The first, was hoping you could kind of dig a little bit deeper into the gate-all-around opportunity for Applied. It sounds like $1 billion for 100,000 wafer starts and that you expect to take 5 points of share. So should we be interpreting that as you gaining roughly 30% of that incremental spend?

C.J., this is Raman. Thanks for the question. Yes, I think gate-all-around, I think, like Uday described in that talk, right? So it involves innovations in all the areas where we have strong products and we have decades of leadership. So I think we're very well positioned. And I think the way where we stand today, I think it's a good opportunity, north of $1 billion. And I think working with customers where we have the DTR positions, today, we think we'll gain greater than 5 points of share. So yes, the way you can interpret, I think your math works but I just want to say there's a good opportunity and it's -- the complexity is high, and I think it plays into all the key areas we're working on, whether it's epi, selective removal, metal gate, gate oxide. And we shared with you a lot of why I think we think we're going to win and how -- why we think we're going to enable the industry.

And then on the share basis, we talked about capturing the majority of that inflection in our areas, right? So the majority.

Yes. Yes.

Mike, I would like to add on the metrology aspects of growth in gate-all-around, so next week, we will have a conference, the SPIE conference, which is the largest conference in the lithography and patterning industry. And we will be introducing, together with IMEC, solutions for looking through the stacks of the gate-all-around to look for the placements of the in the silicon germanium, right? So look for that paper from Applied Materials and IMEC next week.

All right. Thank you. And great. So then the next question that we have will come from the audio line of Stacy Rasgon. Stacy, can you unmute your line for us?

I have, I guess, 2 questions. First, just on the metrology piece. You showed a chart showing some pretty massive growth in eBeam. The optical piece doesn't look like it grew very much at all though from calendar '20 to '21. And I know optical, you've talked about it in other Master Classes, that's a big effort of yours. So I guess what's going on more broadly in optical versus eBeam? And I guess even more broadly than that, what are your thoughts on the overall opportunity going forward for eBeam versus optical as some of these transitions happen? Do you believe that like eBeam starts to take more importance or more precedence versus the other technologies?

Great. Yes. I guess we could -- Ofer can go more into the technology. In terms of share, so one of the things that we've talked about is eBeam versus optical. Our optical, we had a new product introduction last year, and that product had a good buying cycle initially. This past year, we had more growth in the e-beam market, but we're going to have new products in optical. And we think that our optical growth is going to accelerate in 2022 and beyond. And so our mix of e-beam to optical is actually going to start to skew more in the direction of optical. In terms of e-beam growth, we grew, I believe it was about 67% in calendar 2021. And we think that, that the market is going to continue to be an outperformer just because of the way the inflections are going. So things like our PROVision is growing super strong. And I don't know, Ofer, if you want to talk about your expectations at PDC initially and what you think is going to happen.

Yes. So PDC, in 2021, as you said, gained 10 points of share in e-beam, and that's 1.8x our second e-beam competitor and 5x the e-beam market share of our largest competitor. And what's fueling that growth is, we had a Master Class in October talking about a new playbook for patterning control, where we're moving from looking at proximate targets instead of the device. So now we -- the industry needs to look at the device. And we're using PROVision to look on the device and narrow the process histograms. And we're using the VeritySEM to look at the EUV layers where the resists are getting very, very thin. And we're getting traction from customers testing new VeritySEM product that addresses the contrast need for thinner and thinner EUV layers that Regina talked about. So we believe that the growth from both thinner resist with higher and higher resolution from Verity, and we're actually coming with a new product for the thinner resist. We're officially, hopefully, launching it later this year. And PROVision, which is looking across the layers and through the layers, as we talked in the Master Class, to look at the actual edge placement errors. The traditional approach was to look at the 2D layer, one layer at a time, even with e-beam, but not through the layers. Then you take an optical tool and the optical tool would look at the overlay between the layers and then you'll use algorithms to try and align the edges across the layers. What Applied Materials is doing with PROVision, and that is what's fueling the growth that you asked about, is we are directly looking through the layers with higher energy, and then we can directly measure those edge placements. So that's another growth engine where we believe that we will maintain our leading position in e-beam. And we are believing we'll see double-digit growth next year as well.

Okay. Stacy, did that answer your question well or -- okay, I think I don't hear you now so we'll continue.

I'm here. I have one more but I'm happy to get back in the queue.

No, no. No, not at all. Let us take your question now.

I just want to -- so you talked about the move from a spin-on hardmask and transfer layers to CVD, and I thought the reasons for that were clear. You have a competitor that's actually working on a CVD version of photoresist, the dry technology, I think, for some similar reasons. What are your thoughts on that transition? I guess, how do the 2 technologies work together? Can they work together?

So yes, I can try to answer that. So we work always, as you know, very closely with our customers, and we have a really good portfolio of products in our CVD space that can enable all the films that are needed in the stack. But what we do with our customers is that we shift the films when the technical requirements need them to be shifted. So that means that we wait for the inflection before we bring it into the market, and we work really closely with our customers to time those. Our products are capable of depositing these materials. They have the uniformity and the control required. It's really a matter of timing.

I just want to add one thing on, Stacy, is both these inflections -- I mean, these materials coming in, when you go on from something with a wet process to dry, I think the important thing is, in terms of uniformity requirement, in terms of getting to the third dimension where some of the wet processes might run into a challenge with patent collapse and things like this, I think that's what's driving that inflection, where a lot of these mask materials can now go from being a wet process to a dry process thing. So the thing we talked about today is tensile, I think it's essentially driving that because when you look at DTCO and when you look at going to the third dimension, the aspect ratio, I mean, you're trying to make finer sizes with EUV and then you're trying to go in the third dimension, the aspect ratio increases so that's driving the growth for dry. And what's the difference? I mean, there are lots of patterning films. But the difference here is now you're starting to look at really, really, in terms of defect requirements, in terms of uniformity requirements, so there's a lot of innovation that's required to make these films work from the materials side, the chemistry side, the chamber hardware technology side. But fundamentally, the inflection is driven based on the aspect ratio and where the wet-to-dry transition needs to happen to make things work.

All right. Thanks, Stacy. Okay. And then we'll take our next question from the line of Toshiya Hari from Goldman Sachs.

Wonderful. Thanks so much for hosting this. Super helpful. So I guess I had a question on how to think about the competitive -- it's a high-level question, the competitive edge that you guys have, just given the breadth and the depth of your portfolio, I think Applied is perhaps the only maybe 1 of 2 companies globally in semi-cap where you have such a broad portfolio. And I think some of the slides kind of speak to that. I think the patterning revenue growth slide, in particular, was interesting. With the introduction of gate-all-around and the proliferation of EUV, is it fair to say the breadth of your portfolio, the competitive advantage that you have from that is showing up in your share traction, your revenue growth vis-à-vis the overall market? I think historically, customers would typically gravitate toward best-of-breed, and you certainly have a lot of products where you're dominant. But is the breadth of your portfolio finally kind of coming through in the form of share growth and profitability?

Yes, I can answer, Toshi. So if you look at the comment you made, breadth is important, right. If you look at complexity of every device, and you start from logic or DRAM, and it's getting really complex. And when you start making finer and finer structures, the interfaces or the material properties that smaller dimensions are quite different from the larger dimensions. So there is a bigger need to actually innovate on new materials. Also, interfaces matter a lot. So if you just breathe on the wafer, if you just have added exposure, the properties change, so processing in vacuum becomes very, very important. So this, essentially, I think, plays to our strengths in terms of actually having a broad portfolio of products but also having the ability to connect the products, whether it's to create a structure, modify the structure, analyze the structure. We have the breadth in terms of, not only the process capability, but it's also in metrology capability. The other piece, I think, which helps us quite a bit is also we have the ability to -- we have the metal center where we can actually run wafers and actually collect data. So when you work with the customers, we're actually starting at a point where we can actually start conversing in a different way to discuss what to do. So to answer the question, the breadth is really helpful to enable the industry. I think it's playing together. We have shown quite a few examples of how we are either co-optimizing solutions to bring the solutions to the market faster or like actually connecting multiple products in vacuum. I think we talked about last year quite a bit on the wiring solution, where you're talking about putting 7 different processes together in 1 vacuum system to enable the wiring resistance improvement. Today, we talked about gate oxide. I mean, gate oxide scaling for gate-all-around. I mean, that takes, again, how do you form the oxide, how do you treat the oxide? How do you get the defects out to have the right reliable oxide? So all of them needs to be done in vacuum. You cannot actually break it apart. But fundamentally, each of these processes still need to be the best of breed. So it's not just putting things together and making it work. It's making the best products, connecting the best products and then providing the best insight with all the capabilities we have. Maybe Ofer, you can add on to something from the metrology side on it?

Yes. I would like to add, on the metrology side, that the next big thing -- I talked about moving from 2D to 3D imaging across the layers. And the next big thing in e-beam we introduced in the October Master Class is the cold field emission tip. It's a new electron source that is much brighter so you work faster, you cover more area. And it has higher resolution. You can see the smaller defects and measure with tighter tolerances. So we believe that, that would be fueling the growth, is something unique and the next big thing in the market for metrology.

Yes. And if I can just add one more comment is that because of our broad portfolio, it's not only the initial gate-all-around, but gate-all-around will be there for a few nodes, just like FinFET was there for 4 to 5 nodes. And we are actually working closely with our customers using a broad portfolio of epi, SRP, metal deposition, front-end products, metrology, CVD, ALD and, of course, the Integrated Materials Solutions to help improve actually the devices even for future generation of gate-all-around by improving the AC performance, DC performance, multiple threshold voltages and reducing the contacted poly pitch by different techniques, again, using all these unit processes as well as our integrated material solutions.

Yes. How did we do on that, Toshiya? All right. Great. So then we're going to move on to our next question in the queue, and that's going to come from Sidney Ho from Deutsche Bank.

I got a couple of questions on DTCO opportunity. If I look at the chart that shows the contribution to logic density scaling mix going more and more towards DTCO, clearly, Applied will benefit from your higher participation in DTCO than the intrinsic Dennard scaling. But how should we think about the absolute market size of intrinsic scaling? Does it still grow even though it accounts for less than 50% of density scaling at 3 nanometers? Or does it just grow much slower? And I may as well ask the follow-up question here, again related to DTCO. You gave a lot of examples of DTCO applying to transistor formation, FinFET, gate-all-around, whatnot. That's mostly foundry and logic-focused. Does that opportunity also apply to memory as well, which I assume is more focused on DRAM than NAND, but things like High-K Metal Gate? How big is that market opportunity for memory when compared to foundry and logic?

So let me take that. The first question relating to how does intrinsic scaling, growth in intrinsic scaling compare to growth in DTCO. And if you look at the chart which we have put, which is from one of our customers, you can see very strong growth in DTCO going from 7-nanometer to 3-nanometers. The 3-nanometers, the chart showed more than 50% of the scaling, the density improvement was from -- by DTCO. And then moving forward, in my presentation with major inflections like gate-all-around and things like the backside power distribution network, and that's got different names, some people call it RBF, backside power distribution. And also, you also have packaging, heterogeneous integration. With all of these coming in, really, the growth from the density improvements from DTCO is going to be a lot more. So intrinsic scaling is going to be, just like that trend shows much, much less than DTCO.

And then one other thing to think about, Sidney, as well is there is high capital intensity where the intrinsic scaling is happening. So there can still be a lot of industry spending in that space. And I think what our customer was also talking about was just the relative contribution to logic density scaling, it's going to come from these other areas, right? So early on, we had these examples of going from 3 thins to 2, those types of techniques. And gate-all-around is actually a form of that, where you're taking advantage of the geometry change and you're getting scaling. So even if you held the lithography, the intrinsic scaling flat and you go to gate-all-around, you're going to get logic compaction. So that's good for us. But I think there's probably going to be a vibrant market everywhere, right, for everybody that's involved.

And coming to the second question on memory, so if you take a look at DRAM, so DRAM today is still very patterning-intensive, if you look at planar DRAM. But eventually, DRAM will also go to 3D DRAM. You can consider it some sort of like a DTCO, a new device combination. And there, of course, again, it's going to be pretty much structured and materials-driven when it goes to 3D DRAM.

Just to add one comment, Sidney, if you look at 3D NAND, I mean, the other part of memory is, there's a lot of DTCO approach that's already happening. Many customers are already pursuing. In most of these DTCO approaches doesn't happen in the array, it happens with the peri transistor. So does the transistors go under the array or does it go over the array, right? So these approaches are being pursued for 2 reasons, again, right? I mean, it definitely saves area, but it also drives a better performance. It drives better road mapping in terms of capabilities to bring in. So we see this evolving, but I think today we covered foundry, but some of these things are already happening in memory and will continue to proliferate in memory more.

Yes. And maybe one more comment on the DRAM. I think you mentioned about the periphery. And of course, the periphery is adopting more and more elements from logic. So you can also improve things like the capability of the bit line, sense amplifiers, et cetera, to help memory scale.

Okay, super. How did we do, Sidney?

Good. Thank you.

Okay, thank you. All right, great. And then the next question that we have is from Harlan Sur, who's with JPMorgan. Harlan, can you unmute your line so we can hear you?

Thanks for hosting this. This is very informative. And then I got 2 questions. So the first one is that it's pretty clear that the move to gate-all-around provides your customers with lower logic cell size, better transistor performance, and you've articulated the benefits to Applied. But I'm sort of looking at this at a higher level, much like maybe some of your investors. So I'm trying to assess the total increase in process complexity on the move to GAA. So if we take, for example, fixed function logic chip processed using GAA architecture. Compare that to fixed function logic chip to a FinFET-based transistor architecture. So all else being fixed, same number of transistors for chips same number of signal and power interconnect, what is the rough increase in equipment dollars spent per normalized capacity just on the transistor formation process?

Yes. Harlan, I can take this question, and Uday, maybe you can jump in after this. So I think the sizing we provided today is somewhat very similar. I mean, definitely, when you actually change architecture, you do get the power benefits. But if you look at the cost of processing certain things to do, I think the numbers we gave you today in terms of the growth are the same. Some benefits come along because you can get better variability because you're trying to use epi thickness to control the dimensions that you have more flexibility in doing certain things. So I think those automatically drive, whether it's a power benefit or performance benefit. But I mean, the comparison for fixed function, I think if we do it, the growth in the equipment market is, like what we said, it's roughly $1 billion for 100,000 TAM.

Yes. And if I can just add on to Raman's point is, with the gate-all-around, obviously, you get a much more improved transistor, which is giving you better power performance and etch area. But also to use that benefit of power and performance, you have to make some modifications in your contacts. You can have a great transistor, but you have to get the juice out. So that also involves a lot of materials improvement. And all of this drives a big increase in our market size, as Raman mentioned.

So Harlan, did that help with that question?

Yes, very insightful. And then on my second question, again, sort of high level. So on DTCO, it's really great to see the more innovation and tighter coupling between the design methodology and the process architecture. This obviously requires a lot of collaboration and cohesiveness with the entire ecosystem, right? The EDA vendors, your customers, the chip designers and manufacturers and, obviously, the equipment suppliers like yourself. So can you just help us understand how this type of partnership works? I mean, how far in advance are you guys engaging with the ecosystem? Do you interface directly with the EDA software vendors? Also interface directly with the design engineers at your customers? I'm just trying to figure out the level of expertise and sort of breadth the Applied team needs to have in order to implement DTCO successfully.

Okay. Let me take this one and maybe Raman can add later. But we have a very broad, technical team with different backgrounds in materials. We have our own design team also who can do design modeling, et cetera, and of course, the expertise in process and metrology. And we do talk with all of the ecosystem, the broad ecosystem. Of course, we talk very -- we partner very closely with our customers, but we talk with the broader and discuss technology and road map and broad industry directions with the entire ecosystems. And that enables us to provide us the very best solution for our customers and the industry.

Yes. I think, Harlan, if I just want to add this. Like what I said, once the FinFET transition happen and you start looking at 3D, I know pretty soon optimizing and understanding actually the design impact is very critical. So we actually have a strong team who have design background, worked on design, because that drives into what kind of innovation we want to go do with our product development, right? So if you want to get to 3D structures, what type of etch technologies, what type of patterning films we need to do. These are critical because the time for road map development of these do take time. We do engage with customers at various levels. I mean, a lot of the time, we are working on multiple nodes in parallel, all the way from pathfinding down to execution. So the engagement has become very broader with the customer base. It's also our internal capability in terms of what we need to execute is also -- has to get -- has gotten broader. Modeling typically meant reactor modeling or plasma modeling, but now, modeling goes all the way from chip design to understanding what's impact of those design to what etch a chip needs done. So there is a broad -- in terms of expertise we have in-house. And we work with all the partners in the ecosystem to drive the development. And like I said, that is actually critical to make progress today based on the complexity of what we have and also in terms of time-to-market. Having the ability to innovate on this really cuts the lead time overall for the customers, overall for us to develop products and have it on time. And the only thing I would just want to add is there are definitely different types of DTCO solutions. Every customers do optimize based on what they need. And these are things we are definitely working very closely to understand what's the impact, how can we enable it, what new capabilities we need to bring to the table to make that work.

Does that help?

Very helpful.

Okay, great. Yes. And just a quick comment on that, too. I think that things have changed a lot over the last 5 to 10 years. So if you went back a decade, there wasn't as much of that work going on. But if we think about the last decade or so, Gary has brought in a lot of people from, for example, Intel, former chip designers. We have a group that we have now at the company. The leader of that was at Synopsys previously. She's brought in a team. So we have people from different parts of the industry now here because we just have to be able to engage with customers at that level in order -- because of the complexity of the road map, how fast it's changing and how different it is. Before, the customer would just tell us exactly what to do and we can do it. Now we have to really talk to them at a very deep R&D level. And we'll do packaging in the next Master Class, but that's another example where we really have engagements with all kinds of people that are coming in and helping us to understand their needs so that we can respond to them. So things are different. So what I'd like to do is go ahead and take a question, that's a written question before we go back to the audio line. And so Uday, you had talked earlier about the backside power distribution networks, and we have a writing question that talks about the expected adoption of this. Now I know we will have a Master Class on this topic in May, so you don't have to give all the detail if you don't want to. But I think this question's a good one. It's the adoption of these techniques. Sometimes, they're called PowerVias. Sometimes it's backside power distribution. Is there going to be an industry standard? This is the way this gets done. Is it going to be driven by one customer or multiple customers? And are we going to see this happen on exactly the same time line? Or could different customers have different time lines? Maybe, Uday, if you could share a perspective on that, that would be helpful to this investor.

Sure. So some customers have already announced the adoption of the backside power distribution. Some have published conference proceedings like the ITC, Interconnect Conference. And so the backside power distribution network, also some people call it PowerVia, is definitely an industry trend. In terms of timing, it could be different. It may not be all at the same time. I mean, there are 2 major trends, if you look at the back end. Today, we focused -- in my talk, I focused on the front end, a lot of it on gate-all-around. But in the back end, clearly, this backside power distribution is a major inflection. Along with it is also the heterogeneous integration with chiplets. And so these are 2 major trends on the back end. And my colleague, Dr. Mehul Naik, probably will talk in the next Master Class coming up in a month, in May, sometime in May. But both of these inflections really give a lot of opportunity for Applied in things like, areas like CMP, chemical mechanical polish; deposition -- metal deposition, MDP; etch; FinFET products, metrology and packaging. And so we are working closely with our customers in both these major inflection areas. And again, you will hear more from Dr. Naik in the next Master Class.

Super, okay. That's great. That's helpful. So then we'll go back to the audio line. And we have Mehdi Hosseini, who's with SIG on the line.

Two follow-up. I actually want to follow up to the opportunities in the DTCO and backside power. And I think you summarized opportunities as $1 billion per 100,000 wafer per month. And the question is, does this require all your leading-edge customers adopt this technology? And if not, then how should I think about competitive landscape among your customers? And I have a follow-up.

This is Raman. I'll take this question. So the way we size the market is total number of wafer starts, and there's an averaging. Not all customers follow the same methodology to some extent. So the number we give you is a weighted average based on customers. So it's 100,000 wafer starts. It could be 1 customer, it could be 3 customers, it could be 2 customers, right? So it's just -- and what we think the process intensity needs to go from this transition. And again, I said there are variations in how customers will implement this. But that's a rough number which I think will work.

And then the second question has to do with gate-all-around. I want to better understand the middle pitch requirement and whether gate-all-around insertion would require next generation of lithography like high-NA as middle pitch becomes an obstacle. Or you can actually tell me if middle pitch is a requirement for adopting gate-all-around.

Okay. Let me take that one. So metal pitch is not necessarily a requirement for gate-all-around. The layer count for gate-all-around versus FinFET doesn't change very much. There could be changes in the patterning scheme, for example. One advantage of gate-all-around is you can vary the nanosheet width, and customers may go to an EUV litho etch type of process. For gate-all-around and for FinFET, it's more quantized, so there, it could be EUV plus SADP. But in terms of the back end, you don't necessarily -- gate-all-around doesn't necessarily mean that you have to change the pitch. Now you might want to change the pitch for improved a bit of intrinsic scaling, if that continues a little bit, especially something like metal zero, but you don't need high NA. You could do EUV double patterning. So it's -- but overall, I'd say, gate-all-around and the pitch is really is kind of agnostic. The latter part of it is kind of agnostic, too.

Okay. Thanks, Mehdi. And then, one thing maybe to talk a little bit about the next Master Class. There's another thing about the scaling that I think is going to be important. And Raman, feel free to talk a little bit about it today, if you want. So the nice thing, Regina talked about EUV being here and it's really helped with a lot of the patterning things. But at this point in the industry, we're no longer limited by patterning. So making things smaller isn't an issue anymore. What's an issue is making things smaller and still having the wiring work and not having the wiring resistance go up exponentially so that you wind up with a situation where you create something that's smaller, it doesn't work very well, and so you don't get any performance or power benefit as you go forward. So that's a real challenge. And I don't know, Raman, you talked about us growing at 3x the rate of WFE over the next few years in wiring. Do you want to maybe give a little bit of a tease as to what are the challenges and why that's happening? Because that gets back to that earlier question about share and do we expect to grow?

No, great question, Mike. I can take this. So if you look at -- when you start making -- I mean, EUV enables making things small, so intrinsically scale. But the moment you start getting to small dimensions, now we are really looking at the material property at those dimensions. And you cannot just take the existing processes and just plug it in and make it work because it just changes a lot. So there are multiple examples where you really have to go work on it. And this is one of the reasons we started working very closely on these integrated material solutions, right? So for example, Mike, you talked about wiring. If you take a look at that, you need the barrier to make sure -- between the low-k and the copper barrier, you need to have a barrier. But the barrier, when you're making contact with the barrier, that barrier layer now causes enough increase in resistance, almost a 50% increase in resistance, which actually now creates a problem with scaling wiring. To just solve that problem, I mean, you had to actually integrate selective deposition, selective removal. You got to interface modify in-situ. We had to do ALD, a copper reflow step, all in vacuum to make that work. So what's the main point? The main point is actually when you make things small, it's not -- the properties of materials don't stay constant. You have to actually engineer the material. To engineer the material, some things is coming up with fundamental material innovation. There is hardware innovation and processes, but then, you've got to actually connect all of them because exposing things to vacuum becomes a challenge, right? So scaling actually has to be done to continue the industry to move forward. But once you hit certain thresholds of scaling, you are actually starting innovating on all these material opportunity to make things work. So even the example today, Uday talked about gate-all-around, if you want to do metal gate between the 2 nanosheets, now you're looking at actually how do you go to deposit material inside an nanosheet. Today, we talked about gate oxide, right? How do you get gate oxide uniformity and you get the properties around the sheet, which is different from planar or even FinFET. So there are these challenges which open up as we start trying to make things small. And we are really playing with the physics. And I think probably the underappreciated thing is physics really starts dominating. And a lot of the times, scaling gets limited, not just because of size, it actually gets limited because of physics. You look at 3D NAND, scaling has to be done because at some point in time, you couldn't store enough charge, right? So engineering the physics really thinks about looking at material property at a diagnostic level, figuring out how to modify it, how do you treat it. And a single layer makes a difference in what we do. So I think we'll cover the wiring in the next Master Class, but I think we have given examples today of the gate oxide. And there are many, many more examples when you make things small, how do you really start looking at every single layer, every single interface, every single grain boundaries and things like this, how do you make them work? And I think that's where I think it's a great opportunity for us. There was an earlier question on the breadth of our products. I think this is where we can really connect all the abilities we have. We can see what's happening in vacuum. We can have analytics solutions there because variability is going to become a very important problem. So we can actually look at analytics, we can look at sensors, we can look at how to control the variability. And we feel this is a critical part in which we can enable the industry to go forward.

Great. Okay, thanks for that. So why don't we go to the write-in question next? So we'll take one. And this is about -- it's a little bit outside of our area, but maybe Regina can maybe help a little bit. So the question revolves around the lithography. So Regina talked about how we had -- dry lithography went to immersion. EUV came in, and those things were necessary to keep the road map going, right, or certainly very helpful. And the question is, high NA EUV, the next generation of EUV, and the schedule for that, what if that doesn't arrive exactly when it's supposed to? Is that going to be a real issue for the industry? Is it going to stop the scaling from continuing? And does the industry need some sort of a contingency plan just in case it doesn't happen on time or whatever? So I don't know, Regina, if you have a perspective on that.

Yes, I can sort of talk you through that. So like my coworkers, Raman and Uday mentioned, the biggest limitation today to scaling is not the density, but it's truly the physics and the electronics and the interfaces of the materials. So currently, we are limited in scaling by device properties more than actually being able to make something small. So why are our customers still really driving for high NA EUV? The reason is high-NA will help them reduce some of the multilayer patterning back to maybe a single-patterning step and that is a cost saving. So cost is always important in our industry, so that is the main driver for high-NA EUV. We will continue slowly scaling our layers, and that's why we talked about intrinsic scaling at the start of the conference because the big bottleneck for scaling right now is not the lithography tool. EUV actually can print relatively small features and high-NA can go even smaller. But what limits us is the variability, like the material variability, the transfer variability and as well as the defect. We call those the stochastic defects. So with the introduction of high-NA EUV, those will actually become even more important to solve. So we are working really hard on getting ready for high-NA EUV and helping our customers enable those cost savings when the tool is ready. But in parallel, the scaling can continue. And really, a lot of the work is going to be done at the DTCO level and the physics of making the via resistance and the performance work.

Yes. And if I can just add into that is really, as we covered in the road map, the main inflections really as in the front end is gate-all-around. And you'll have different versions, scale, gate-all-around or subsequent generations. And that can improve, not only on the power and performance but also on the density. And then on the back end, we've talked about the backside power distribution, again, because those addresses some of the fundamental limitations by changing the design that can help and also going to a heterogeneous packaging. So all of these can actually help the industry to continue to scale without necessarily reducing intrinsic pitch very much, okay? And as Regina mentioned, so high-NA is actually quite useful to reduce lithographic costs, perhaps instead of 2 UV layers going to 1. It also takes out some of the overlays and that can help shrink things a little bit. If you take out your overlay margin, you could shrink that just by taking this out. And of course, cycle time.

Yes. I would like to add on what Regina said about the increasing variability. So I mentioned earlier the SPIE conference, so there is another paper coming in the lithography and patterning conference by Applied Materials and IBM, where they're taking the and the CD-SEM and the VeritySEM and they're taking down the energy, improving the contrast to get better control of that variability, improving the resolution and the measurement. So there is an optimization going on there. And it's quite interesting to show how we can then reduce the variability, whether we go with EUV, and get increasing variability because the multiple patterning steps or with high-NA EUV, where there's less contrast because it's thinner. So either way, I think that the CD-SEM work is relevant.

Okay, great. So that was from Charles of Needham. And Charles, I hope we did a good job answering your question. We're going to jump back to the audio line. And we have a question from Joe Quatrochi.

Thanks for doing this call, it's very helpful. I was just kind of curious, on gate-all-around, obviously, you talked about over $1 billion of kind of incremental spend there. As we think about the next kind of iterations of gates-all-around and these different architectures, I think you had forksheet and CFET, how do you think about the incremental maybe revenue opportunity from, if it's different steps or materials that might be needed there?

Joe, this is Raman. So I think if you look at what the next near term, 3 to 5 years, right, covering what's happening with gate-all-around, gate-all-around, I think we see the next generation coming. But again, like I said, different customers have different ways to do it. Forksheet is still a little bit out in terms of how it's going to get implemented. So actually quantifying what's the opportunity today might be a little bit early. This is something we'll definitely share with you in the future events or discussions we have. But what we want to provide you today is what we see in the next 3 to 5 years and how gate-all-around plays out and what the innovations are going to come in. But again, like I said, it's early for Gen 2 of gate-all-around. It's a little bit too early for CFET. But when you get a chance, I think we'll cover more how that evolves and what the real challenges are and how we can enable them. That kind of helps us quantify where the value is coming from and what the size of the market will be. And Ofer, if you want to add something, please go ahead.

Yes. I would like to add, because you mentioned is forksheet far away in their road map. So one of the big challenges the chipmakers have when they want to come up with something new is to have process splits. And having process splits, you need massive metrology to make decisions and to make 3D devices like a forksheet, you need either to be very slow at cutting TEMs. These are the tools that look at lamellas or you use cross-sections, and you look at the atomic layers or you can use PROVision, as I mentioned, it's a 3D metrology looking through layers. And we have a paper coming again at our conference next week on how we work with IMEC to tune forksheets, and we compare the PROVision results to the TEMs and show how, while you can get very few TEMs, not enough maybe to make a decision on a process split, you enable faster time to ramp this process by using mass metrology in 3D at these forksheets to look at those layers.

It sounds like quite a few papers at SPIE. So I wonder, can we get our hands on those?

Yes.

Okay. So if anybody wants the SPIE papers, then we'll make those available. Okay, great. So then Joe, did you have any follow-up? I'm sorry, I just want to make sure we got your question answered.

Yes. Maybe just a quick follow-up. Just kind of as we think about the path to high-NA and you talked about there was already some EUV multi-patterning. I guess, what type of multi-patterning level do you think we could get to between now and high-NA? Do we get to quad-level EUV patterning or maybe we're already there? Any help there?

So right now, we see 2 types of EUV multi-patterning. The first one is what we call it litho-etch-litho-etch, where you repeat the litho step multiple times. And that can, in principle, go to more than 2x because when do we use that? We use that when we want to multiply the lines. So that might be 2x to multiply the lines. And then we might use an extra time to cut them into pieces. We've talked about it in one of our past Master Classes for regular EUV. So those same techniques of cutting the lines are being used for EUV. Now how often you need to cut a line really depends on the density of the pattern you want to make. That is the reason that we've developed the directional patterning technology to help avoid that step because that step can explode quite rapidly if you really need a lot of pattern density and design flexibility at the same time. So skipping the step of cutting the line and replacing that with a lateral patterning technique that pushes the lines back together is a big cost savings for our customer. So in that case, you can still see single or double litho etch to make the lines, you remove some of the extra steps to cut them. Now the second type of multi-patterning is spacer multi-patterning, so SADP. That may use one spacer to double the EUV pattern, and then you start cutting again. That technique is also being used. And when we've talked about the regular patterning, we've always talked about SAQP, and some of our customers have put SAQP in production. And that works really well with regular lithography. With EUV, we don't see that happening at this point. Because if you have to go to features that then is enabled by SAQP and EUV, we are running into a lot of physical limits, electrical limits, alignment issues. So there will be a lot of things that will break before we need to go to shrink dense patterns. So that, I don't see coming in the near future. We're really going to have to spend a lot of effort in making the power and performance work before shrinking that far.

Yes. Just to add to what Regina said and something I think we mentioned before. Things are getting really limited by the physics like in the front end, things like leakage. Because as you make the dimension smaller, that becomes more of a factor than how you pattern it. And similarly, in the back end, as we mentioned a couple of times before, the resistance -- wiring resistance shoots up exponentially. So you need really other DTCO-type solutions for both of them to get the density improvements.

Great. All right. Thanks, Joe, for that. And then, there is a follow-up question that we had in writing, well, it reminds me of what you were just talking about, Regina. So there's a question on the line from JPMorgan. And it's about this EUV pattern extension technology that you talked about. So the question is, maybe a little bit about how it specifically works. How do you control the amount of the EUV pattern that's being extended? Like how do you control that? What's the technology? And then if you have a sense of, is this just a futuristic thing without customer adoption? Or is this something that you could see customers really using, and when, if that makes sense.

Yes. Let's start with the technical piece. When we look at pattern elongation, what we use is a plasma that will be directed under an angle. And so controlling that direction of the angle is essential for making that work. We use what we call a ribbon beam tool, so it is a different technology because it needs to be extremely well controlled in a small sheet in order to elongate the pattern really well. So then how do we control the amount is based on what chemistry you use or plasma conditions do we use as well as the time of the process. So we have several knobs that we can use to control the pattern elongation. I think you can think about typically the customers that we work with, they're looking around somewhere between 20 to 35, 40 nanometers of push of pattern elongation for the typical layers that we're working on right now. So that is a good number to keep in mind when you think about what we're doing. But we can control that. We could do less, we could do more. It really depends on the situation. So it's really more the device integration determined than the capability of the tool. So then you had a question about the adoption of this tool. We've talked about this, too, for a few years. When we started talking, we were talking about our Alpha tool. At this point, we have a tool on-site at several of our customers. We are working closely together with our logic foundry customers on this technology, and we received orders for multiple tools already. So yes, this is real. It's still early. I think you're going to see a lot of more news on this in the future, and we'll keep you updated on how we're doing. But it is out of the Alpha state into actual tool collaboration with our customers.

Great. Okay, good. And then Joe had this question about EUV double patterning. So if you use this, you might be able to avoid one of those steps?

Yes.

Okay, great. And then I had a question, before we go back to the audio queue, that was on a writing question. And this gets back to the product that we launched today. This is the new CVD film for the patterning of EUV patterns into the wafer, depositing all of those films that get etched. Is that a significant product? Like is it a big product? Is it a niche product? If there's any way to kind of quantify if that's a big deal for us. And then maybe also just as a related question, the selective materials removal, so this new type of etch that's coming into the industry, is that also something that's very small? Or is it something that for Applied Materials is becoming a bigger product? Maybe just if there's any way to give some color on that.

Yes, Mike, I'll take this question. I'll start with the first question first. The tensile film we launched today, I think I was answering earlier, think about why it's important. We're going to DTCO, going to 3D, going to narrow line with the dry things becomes important. This is already -- we are still in the early innings. I think we're working with all customers qualified. We're generating actually hundreds of millions today revenue in this particular product. And if I look at the next 3 to 4 years, we're looking at close to $0.5 billion. We see more layers getting adopted as the industry progresses, but we're looking at the next set of inflections, what is happening. But we see the more adoption of DTCO or getting into the third dimension push us more into dry processing of films and trying to go away from spin-on. I think so we see an upside opportunity driving this market in the logic space. If you look at selective removal, I mean, this is an area we've been working for a long time. We released the product Selectra in 2016. And I think this is something, if you start from the previous nodes to now like what we showed, we're looking at a couple of steps, right? I mean, low single-digit steps. So now we're looking at low double-digit steps. There is a huge growth coming. A couple of reasons: one, when you start making these 3-dimensional structures, really having selectivity to different materials become very, very critical. You want to be able to remove certain materials but not touch materials on the other dimension, that's really critical. Like I did mention before, a lot of these processes were done with wet. And then when we get to these fine structures and geometries and if you look at how we're doing gate-all-around, there is -- the complexity gets to the point where the wet processing doesn't come in. So 2 things are happening. One, there are more steps because of the architecture coming in. Second thing, there are more steps coming in because this architecture pushes the technology to go from being wet to dry. So again, this market, there have been -- like I said, we released the product in 2016. We have almost greater than 1,000 chambers in the field today. We are generating hundreds of millions of dollars of revenue. And this transition is almost going to probably double our revenue compared to 2 years ago to where we are today in terms of -- so it's going to be a few hundred million dollar revenue already happening today, and the opportunity continues to grow for us.

Okay. So annualized, it's already hundreds of millions?

Annualized, hundreds of millions. And if I compare from 2 years ago to now, it's probably, like I said, it's gone up more than 2x revenue.

Okay, great. Okay, super helpful. Okay, and then just going back to the audio line, and we are getting close to the end of the Q&A session. But going back to the audio line, do we have a question from C.J. Muse? And I'm not hearing you, C.J. So if your line is muted, please check it. Otherwise, I'd like to go back to the write-in question that we have queued up. And so we have here a question that has to do with competition in some of these new spaces. So I won't name the competitor. Although it's in the question. But a competitor has talked about gate-all-around and significant growth in the epitaxy markets, also in ALD, those kinds of areas. So I think the question really gets to, how is Applied positioned in epitaxy in these new areas where it's being used in gate-all-around in new step? So is that something where the company will do well or will there be a lot more competition? Maybe if there was a way to characterize that. And then there's a follow-up.

Yes. Mike, I'll take that question, too. Gate-all-around is a great opportunity. I think we shared today, the number of epi steps are increasing. But I think the most important thing though is, epi is not just epi. And what is really required to make the epi layer is critical. So there's a superlattice epi, which requires very abrupt interfaces like what we shared today. But also, it requires -- to actually have a good epitaxy film, you need to have really good interface engineering. This thing needs to be done at a much lower temperature. So there is some critical technology in what we call the blanket-type film. The second type of film we covered is the selective type of epi. And this is something where we have been participating over the last 15 years, enabling the industry to make selective epi work. But what's important in selective epis, as you start scaling more and more and actually started getting to the gate-all-around, actually the depth, the aspect ratio of how we treat with epi becomes important. The interface treatments get more and more critical. So having the ability to actually do interface treatments, interface engineering and having the best epi technology to grow is super important. I just want to give a relative size of the market. I mean, we shared something today, it's about probably 80%, 85% is the selective market. About 15%, 20% is the blanket market. But both markets have critical requirements, and I think they need an ability to treat the surfaces to get the best quality film to make it work. And these are areas, I think, we are working very closely with the customers. We have a long history of the product on the epi side but also on the integrated side. We feel very strongly about our position. We feel very strongly about the momentum and the opportunities we're going to capture in this market. This is a market we have been playing in for a while. We understand their challenges, their requirement, what needs to make it done. The second question you had, Mike, was on ALD, right? ALD, I think, is classified as a stand-alone application, a stand-alone market, if you look at a lot of the third-party reports. But the way we have been looking at ALD is how do we bring value to solve a problem. So a lot of the ALD solutions we do actually gets integrated as part of other solutions. I talked about the wiring example. And one of the steps in the wiring example is ALD layers. We talked about metal gates. Metal gate example uses a lot of ALD layers. These are, in the third-party reports, characterized as a part of the PVD or the metals business we have. But we have a strong ALD technology, but our focus has been on creating the high-value enabling ALD technology and integrating with everything else we have. If I just peel it off and say, like, hey, how much revenue does this bring? I mean, you're talking about a few hundred million dollars of revenue this brings to the table. But it comes as part of an integrated solution we do. And we are really focusing on creating the technology which actually adds value and drive more adoption. So our focus has been on trying to get the ALDs more on the integrated side of the thing. What you see in the outside market is we have a semi batch product. That's the only revenue you see. And that market is probably, I mean, in the high hundreds, close to $200 million range for last year, if you want to look at it. So we have an offering again, even that market, we are solving a critical solution for the customer. So we are picking and choosing where we want to compete, how do we create value, how do we drive the solutions forward in this market space.

Okay. So if it were stand-alone, it would be several hundred million dollars annualized?

Right.

Okay, got it. Okay, super helpful. Great. So we're coming up to the end of the session. I'd like to go to the audio line and see if we have a question from Rob Sanders with Deutsche Bank. And Rob, if you could unmute your line if you're there.

So actually, my other question was asked, actually. Thank you. But I would like to ask about intensity of deposition and etch from 2025 to 2030, given the inflections that you're looking at 3D DRAM and of course, everything we've discussed today. Do you think that deposition and etch will grow faster than WFE in that sort of second half of the decade? And would that be at the expense of litho?

Yes. Let me take this, and then I'll ask my colleagues to join in. So I think what we're going to see, Rob, I think complexity is increasing. So if I look at device segment by device segment, right, few things are happening. Like I said, when 3D DRAM comes in, it's definitely going to be a lot more depth etch-intensive, very similar to what the NAND happened. The only difference in the intensity side, if we go to 3D DRAM, based on the material requirements and the electrical requirements, a lot of them are conductor material. So you'll end up seeing more of a conductor etch-type intensity growth. So that will be a variation, but if you look at etch, etch intensity will increase but the intensity will switch to something else. The second piece of it is probably not really appreciated because the segment don't get called out is, you will end up seeing a lot more integrated applications, which means you're looking at etch, depth are all getting integrated to form these solutions. So they may not be called out as a dep market or etch market, but you end up seeing these things coming together. Even today, we shared some examples of depping and etching in the same chamber because to make some of these things happening, you're actually doing some of the depping and etching on the same chamber, right? So you're seeing the market evolve into different things. So will the overall intensity go up? We think these are highly enabling solutions, so we see the intensity increasing. We also see a slightly different approach to which type of the market will grow. The third thing is, they will all get combined in some form together for the intensity to increase, right? So we do see dep and etch increasing. One of the areas we've been focusing on is a co-optimization. This like can you bring them together? Because putting these and optimizing and making sure the variability really becomes important, so intensity does increase and the complexity does increase. And I think we see different ways the technologies are going to get combined to make unique solutions. So I don't know, Ofer, Uday, if you guys -- or Regina, if you guys want to add on something.

Yes, maybe I can just add on. I think just echo some of the things which you already mentioned. But not only it's dep and etch, but how you integrate everything, not only just deposition and etch, but things like plasma treatments, interface treatments, thermal treatments, selective removal. And as the processes get so complex, the ability to do it and having an integrated material solution, having everything under a vacuum, along with the metrology. Again, we gave one example today about the gate, and earlier, we had the -- I think, in the Analyst Day, we had talked about the metal step, how we reduce resistance by integrated material solution, which actually had 7 steps in it. So all of these, as we look at 3D DRAM, as we look at advanced logic over the nodes, you'll see more and more of this integrated material solutions coming in using all this process as well as metrologic capabilities.

Let me add on that. So we talked in the October Master Class about moving from the traditional metrology that's looking layer by layer. And now in this Master Class, we expanded on measuring the edge placement layers across the layers. And as my colleague Raman mentioned, things are going to be more integrated, so you look more and more in the 3D space, the interactions between the edges of the different layers. And again, there is a very good proof point next week in the conference by Applied and Hynix, where they compared measuring the CD uniformity in the traditional layer by layer and the optical metrology. And they will have some cases where you think you're out of spec on either the CD uniformity or the optical overlay. But when you measure the edge placement there across the layers, you see you're okay. So imagine that you would scrap wafers for no good reason. And also the opposite, where you think you're doing okay with your CD uniformity and overlay, but when you measure through those layers, the edge placement areas, you're seeing you're out of spec. So you think -- you'll only find that at the end of your process that you're actually needing to scrap wafers you completed. So I think that looking forward into the future, more of these measurements will take place. And I think it's a good place to come with this to 2D to 3D transition in metrology, in the workhorse metrology.

Great. Okay. So -- and Rob, did we manage your question well?

Yes, you did. Thanks, everyone, for a great panel.

No, I appreciate you saying that. So that is our final question today. We'd like to thank everybody for joining us today. I appreciate it. When you sign off, you're going to see a 1-minute survey. We hope you'll share your feedback with us, in that way, we can help make events like this a little bit more responsive to your needs. Speaking of which, the next event is scheduled for May 26. It's going to be about new ways to wire and package chips. And finally, I'd like to thank you, Raman, Regina, Uday, Ofer, for your presentations today, for answering everybody's questions. I'd like to say take care, everybody, and enjoy the rest of your week.