Applied Materials, Inc. (AMAT) Earnings Call Transcript & Summary

Hello, and welcome to today's event. I'm Mike Sullivan, Head of Investor Relations at Applied Materials. We are launching 2 new products today during the SPIE lithography and patterning conference. Before we begin, I'd like to give you some context on how today's product introductions fit within the industry. What I'm showing you here are 3 ways to segment the wafer fab equipment market. You're probably familiar with the segmentation on the left, which is by equipment type. You can see the Applied Materials' segments and share in blue. In the middle, you can see the equipment markets by device type, DRAM and NAND, along with foundry logic, both leading edge and ICAPS. On the right is the way engineers often segment the market, which is by application. The 4 major applications are patterning, which is used to define the features on each layer of the chip, along with transistor formation, interconnect formation and advanced packaging. Patterning includes lithography and track tools, but these tools primarily transfer patterns from masks to photoresists. Patterning depends on many other tools as well, for example, to deposit patterning films, measure pattern accuracy and etch patterns into patterning films as well as into wafers. On the right side of this chart, you can see that Applied offers 8 kinds of tools for these other patterning applications, including a brand-new kind of tool that we'll introduce to you in a moment. Patterning has been a big focus for our company since 2013, and we anticipated at that time that our patterning markets would grow faster than WFE overall. Our opportunity has grown from around $1.5 billion in 2013 to over $7 billion in 2021. And our share of this opportunity has grown from less than 10% to nearly 30% over this period. So today, we're going to introduce 2 new products, the newest member of our eBeam metrology family and this brand-new technology called Pattern-Shaping. And here is today's agenda. So first, Steve Sherman will introduce you to the new technology called Pattern-Shaping that can replace EUV steps. Then Keith Wells will introduce you to a new metrology system that will help to enable High-NA EUV. And then finally, we'll help answer your questions. A quick housekeeping notice. We've already posted all of the slides and the supporting materials from today's presentation on the IR page of our website at appliedmaterials.com. And now I'd like to hand the meeting over to Steve Sherman. Steve?

Thanks, Mike. Before we get into Pattern-Shaping, I'd like to introduce a few simple patterning concepts that will help it make it easier to understand what we talk about later. On the upper left is a simple line space pattern sometimes called a grading pattern. Many of today's critical patterning layers start with a simple line space pattern. Next is a cut mask. These are holes or trenches that are used to segment the lines in the line space pattern. And last, we have vias. These are holes that are later filled with metal and are used in interconnect wiring. They connect one metal layer to the next. On the left graph, we illustrate what we call the lithography gap. This is a gap between lithography resolution, which is the green line and the minimum critical dimensions that chip makers would like to pattern, which is the blue line. Over many decades now, different material's engineering techniques have been used to close the lithography gap. Today, we're going to talk about one specific critical dimension called tip-to-tip spacing. In the lower right is a cartoon with a line space pattern. The gray lines can be thought of as trenches in the blue material. Also, you'll see an x and a y axis next to the image. In order to shrink die size, you have to reduce dimensions or shrink dimensions in both the x direction and the y direction. In the y direction, this is done by shrinking pitch. in the x direction, this is done by shrinking tip-to-tip spacing, which is the space between opposing line ends. In today's EUV lithography equipment, many optical tricks are used to improve resolution in one direction only. In this case, you could say the y direction, which is used to reduce pitch and pattern the tightest pitch possible. Most of these tricks that are played to improve resolution in one direction, end up sacrificing resolution in the opposite direction. So, the tighter pitch that you try to pattern, your ability to pattern tight tip-to-tip decreases. I put some numbers to that in the table above. These are for a line-spaced pattern of about 32-nanometer pitch. That is a 16-nanometer line and a 16-nanometer space. This is about the practical limit of what can be patterned today with a single EUV pass. For a 32-nanometer pitch line space, the tightest tip-to-tip that can be patterned is in the range of about 25 to 30 nanometers. However, if chip makers want to pattern a tighter tip-to-tip spacing of about 15 or 20 nanometers, EUV double-patterning is required. And we'll talk about a couple of different examples of EUV double-patterning in the next couple of slides. On the left is a 2-scale image of interconnect wiring. The metal lines wrote signals and power within each layer of a chip. The lower metal layers are critical layers where chip makers are pushing the resolution of EUV lithography. This is where we want to pattern dimensions that are beyond the resolution that can be done in a single EUV mask. On the right, we show one example of EUV double-patterning. We start with one EUV mask, which is a simple line-space pattern as we described before. Here, the gray lines, again, are the spaces and can also be thought of as trenches. Then we go to a second EUV pass or a second EUV mask to print what we call a block mask where we add material and effectively segment the trenches and define the tip-to-tip spacing of those trenches. And here, we have the full pattern. And we've created a tip-to-tip spacing that is not possible with a single EUV mask because it's beyond the resolution of one EUV mask. In this slide, we show a similar example for vias. Again, the lower via layers are critical layers where we're trying to print dimensions that are beyond the resolution of a single EUV mask. And this is where multi-patterning is used. On the right, we show a different example of EUV double-patterning. Here, we start with the first EUV mask where we print only half of the pattern. So, only about half of the vias are patterned here. And in this way, we can get a tip-to-tip spacing between the vias that is well within the lithography, the resolution limits of a single EUV mask. Then we follow with a second EUV mask where we print the second-half of the pattern. In this way, we can achieve a tip-to-tip spacing that's beyond the resolution of a single EUV mask. In both of those examples, we went through the EUV lithography twice. Here, we show a simplified process flow of EUV double-patterning. You can see the 2 lithography steps and also all the associated steps, including patterning layer depositions, etches, cleans and metrology. As we've explained, this technique is effective at getting all the critical dimensions that we require. However, there are undesired consequences, and those are shown in the boxes at the bottom. First is alignment errors. Because we have 2 masks, the second mask must be aligned precisely to the first. If it's not, this can cause a litho rework where the photolithography is measured for alignment and the photoresist can be cleaned off, respond and get a second try through patterning. Any alignment errors that remain as the wafer goes downstream will result in chip performance and power issues and if the alignment is very bad, yield loss. The middle box, we described the energy and materials used for each EUV LE loop. LE stands for litho etch. So, we estimate about 25 kilowatt hours per wafer, about 0.5 kilograms of CO2 equivalent emissions per wafer and about 15 liters of water per wafer per LE loop. And on the right box, we show the cost. We estimate about $350 million of capital cost per 100,000 wafer starts per month and about $70 per wafer manufacturing or OpEx cost per wafer per EUV loop. Now I'll talk about Pattern-Shaping. On the left is the same EUV double-patterning we talked about earlier with a line space pattern and a block mask. On the right is today's news or Pattern-Shaping. Here, we pattern with 1 EUV pass only where we pattern the line space pattern as before, but including the tip-to-tip spacing. But the tip-to-tip spacing is patterned wider than desired, but within the resolution limit of a single EUV mask. Then we move to the Pattern-Shaping tool where we elongate the trenches, thus shrinking the tip-to-tip space to the desired spacing. In this way, we're delivering all the dimensions, the pitch and the tip-to-tip facing that we desire, but with only 1 trip through the EUV tool. And here is the similar for the via example. On the left is the same double-patterning technique we talked about earlier with a first EUV pass with half of via's pattern and then the second in the second pattern, EUV LELE. On the right is the Pattern-Shaping example. Here, we use one EUV pass where all the vias are patterned in one mask, but with a different shape such that the tip-to-tip spacing between the vias is within the resolution of one EUV mask. Then we move again to the Pattern-Shaping tool where the vias are elongated such that the tip-to-tip spacing is reduced. In this way, again, we deliver all the dimensions of EUV double-patterning but with only one pass-through in the EUV tool. This is our first Pattern-Shaping product. It's called the Centura Sculpta patterning system. It's a breakthrough innovation for the pattern engineer's toolkit. It's a brand-new capability in the fab. It enhances EUV patterns to optimize chip area and cost without EUV double-patterning, reduces patterning complexity, reduces the environmental impact of advanced chip making by saving energy, materials and water, reduces capital on operating costs, and it's extendable to High-NA EUV patterning. This has been in development for over 6 years in collaboration with Advanced Logic/Foundry customers. And recently, we've would have been chosen production tool of record for multiple layers in leading-edge logic. Here, we'll share a 3-minute video on Pattern-Shaping technology. The first-half of it is somewhat repetitive to what we've talked about before, but in the second-half, we'll describe how the tool works. [Presentation]

Here, we show the same simplified process flow for EUV double-patterning that we showed earlier on the top. On the bottom is the simplified process flow for Pattern-Shaping. You can see the same one EUV loop, but then the second EUV loop is replaced with Pattern-Shaping. Here, we quantify some of the savings using Pattern-Shaping. First, of course, because there's only one EUV loop, there are no alignment errors. We've eliminated one opportunity for alignment errors in the overall chip making process flow. In the middle, we show the energy and material savings we estimate; about 15 kilowatt hours per wafer saved; about 0.35 kilograms of CO2 equivalent emissions per wafer saved; and all of the 15 liters of water per wafer saved. On the right, we show the cost savings. We estimate about $250 million of capital cost per 100,000 wafer starts per month and about $50 per wafer of manufacturing costs saved. In our press release, we have a few quotes that I have here. The first one is from Intel talking about what they see as the main value of Pattern-Shaping. The second is from Samsung, also describing what they think is good about Pattern-Shaping. And the third is from an industry analyst, Dan Hutchinson, talking about the importance of Pattern-Shaping. Now I'll hand it over to Keith Wells, who's going to talk about a new eBeam metrology tool.

Thank you, Steve. So back in December, we talked about the eBeam market and in particular, we focused on defect control. And we introduced 2 new products, the SEMVision G10 and the PrimeVision 10. Today, we're going to talk about the pattern in control segment and here, we're going to introduce a new tool called Verity 10, which is a critical dimension metrology tool. So, what is a CD-SEM? It's often called the ruler of the fab. And what it's used for is to make extremely precise and accurate measurements of the line and spaces that our customers are trying to print as well as the pitch. And it's even gone beyond that, it actually measures what's called line edge roughness or line with roughness on the device. Our customers use this to optimize their EUV steps in the fab today and have been highly dependent on this technology for over 30 years in order to monitor their process and get high yield. So, let's look at how it's applied in the fab. So, it's used in 2 main process steps. One is the lithography loop, where after the lithography tool exposes the resist, the CD-SEM is used to make sure that both the line widths and the pitches are patterned correctly. Here, the customer, if they do find errors, are able to rework the wafers. They're able to strip off the resist and then go back through that process. So, the CD-SEM is an important quality monitor in the lithography loop and really can end up saving our customers millions of dollars. If the lithography is patterned correctly, then the wafer is transferred to an etch step. And in the etch step, what we do is we look at the critical dimensions after the wafer has been etched. Here, the customer will make a decision whether or not to proceed forward with the wafer. If the etch step was unsuccessful, unfortunately, the customer at this point has to scrap the wafer. If the edge step was successful, the information from the CD-SEM will be transferred back to the litho cell in order to do co-optimization between the lithography module and also the etch module. And you can see the precision that customers want from this type of tool actually demanding precision inaccuracies in the sub-1 nanometer range in order to properly monitor the process. So, let's give an example of how this type of tool has been used in the litho module. So, if you go back a few years ago when we were primarily using deep UV patterning techniques, the pitches might have been on the order of, say, 70 nanometers, the process window plus or minus 1 nanometer. And the SEM Precision had to be about 1/10th of the process window or 0.1 nanometer. In general, we were using landing energies that generated resolutions of about 1.4 to 1.6 nanometers. Taking that same type of technology and using it in EUV and High-NA EUV is going to be problematic. Here, you can see the actual pitch is about half in the 30-nanometer range for most EUV steps. The process window has become tighter and therefore, the SEM precision requirement has also become tighter. If we go and we look at High-NA EUV, it's only going to get more challenging. Here, we're seeing the pitches in the 20-nanometer range, the process window of 0.5 nanometer and therefore, the precision at 0.05 nanometers. So, this represents a challenge for us in order to try to meet these types of specifications, especially in the High-NA EUV steps. So, how do we build a tool that can meet those challenges? Well, typically, what you do with a eBeam tool is you actually increase what's called the landing energy or the energy of the electrons. And the more energetic electrons you use, the higher resolution you'll have in the system. So that works for most steps. But unfortunately, when you look at EUV resists, they're actually quite delicate. And the interaction with high-energy electrons can actually damage or shrink the resists. This is a common phenomenon in the industry. So, you've got to pick a balance between using as much landing energy or as high as landing energies as you can to increase the resolution, but not damage the resist. So, this is an example of kind of the trade-offs that you have to make. And so here, we're trying to figure out what landing energies we can use in a new CD-SEM in order to meet the resolution requirements. And so, the concept is really that you have an operating range or a working, landing energy range that you have to determine. And you have to engineer the tool such that it has acceptable shrinkage of the resist when making the measurement, but also has the required resolution to meet the demands of High-NA EUV. So, let's go back to our example here. And what we saw back in the Deep-UV patterning area, that working landing energy range was fairly wide. And the SEMs used back at that time were able to meet the requirements of the Deep-UV steps. If you take that same technology and you try to apply it to EUV, it works, but then the operating range or the landing energy ranges you can use have shrunk considerably. So, the customer has far fewer options around the operating points of how they can use the CD-SEM and the fab. So, what we're trying to do with Verity 10 is reengineer a tool that will expand the landing energy working ranges for the High-NA EUV. And so today, we've introduced this product for EUV, but we've also future-proofed it such that it can be applicable to high-NA EUV with these wider landing energy ranges. And so, the Verity 10 to recap, really has lower landing energy in order not to damage the delicate EUV resist. But what we had to also do was to redesign the column in order to get the resolution to the requirements of EUV patterning. And so, we've done both in this tool, both given our customer's lower landing energy operating points as well as increasing the overall resolution of the tool. This leads to minimum resist shrinkage, and we've also made the tool faster. So, it's going to be also 30% more productive versus earlier versions of the CD metrology tool. And so, if we go back to our example and we look at what this tool will be able to do as we go forward and adopt more EUV patterning steps and then finally adopt High-NA EUV patterning steps, here, we're able to almost double the resolution going down to sub-1-nanometer resolution and deliver an overall range of 0.8 to 1.2 nanometers resolution, and we're able to do that at landing energies that are far below 300 volts. And that will give us the resolution needed to monitor the High-NA EUV steps. Now we did a lot of engineering of this tool to address, obviously, the litho module, but what else did we do in the tool? And there's 2 other applications that we targeted for this tool. One is Gate-All-Around applications where we've added in back scattered electrons to enhance our ability to give us contrast on these critical Gate-All-Around steps. And we've also enhanced the product for 3D NAND in order to give customers the capabilities they need to properly monitor their 3D NAND steps. So, let's take a look at a few examples here. But before I do that, I want to talk a little bit about what backscattered electrons are. Again, back in our webinar in December, we introduced this slide. And traditionally, what a CD-SEM does is it collects secondary electrons. Secondary electrons are generated at the surface of the material that's being monitored and they're very sensitive to things like contact openings. And that's how traditionally CD-SEMs have been designed, to mainly collect the secondary electrons. But you can gather more information if you use back scattered electrons. Backscattered electrons can penetrate down deep into vias and they can give you information about material in the bottom of the vias or the bottom of trenches. And getting that information and back up and detecting it gives you much sharper contrast between the holes at the top and the structures at the bottom of the wafer and then allows you to make more precise CD measurements. And we've applied this type of concept to our Gate-All-Around structure. So, here what you're seeing in the Gate-All-Around structure is an example of epitaxial fill down in the trenches. Now because the epitaxy is clearly a different material than the gate on top, we're able to use backscattered electrons to generate contrast to the epitaxial material. And that tells us whether the fill of the epi has been done correctly. We can obviously check for ideal fill, overfill, underfill, things as partial fill and avoiding down in the epi layer. So, what we're giving our customers is not only the ability to measure CD-SEMs in this step, but we're also giving an ability to monitor another process when they use the Verity 10 and apply it to this type of application. And here's an example of how the VeritySEM is helping our customers in 3D NAND. Here, a critical part of the 3D NAND patterning is what's called the staircase step. Here, they're very complex interconnects, and they're patterned over a very large area at the semiconductor device level, over 60 microns in area. And also, the overall aspect ratio in z dimension can be over 10 microns. And so, what our customers want to be able to do is to use Verity 10 to go in and in a single imaging step, image that 60-micron field of view in x and y as well as get information across the whole depth of field of the 10-micron step. So, we've engineered the tool with a wide field of view as well as a very generous depth of focus in order to allow our customers to do this type of monitoring step. And therefore, we've made the Verity 10 much more flexible than just a CD-SEM. And so today, we've introduced this product to the market. We have over 30 systems shipped. We have tools of record in development for data around at leading-edge Foundry and Logic customers. We have placed multiple tools at customers doing DRAM for both production steps and the EUV modules in those production steps. And finally, we also have both a development tool of record and production tool of record wins at 3D NAND customers. And so, here's an example of kind of the history of the CD-SEM within the PDC business unit. If you go back 10 years ago in 2013, we had barely 14% of the market back then. And you can see for Logic and Foundry, we had only 5% of the market. But starting with the Verity 5i, approximately 6 years ago, we built a tool where our customers found it very productive and basically started applying it more and more to critical Foundry and Logic steps. So, our market share increased to roughly 25% in that area. With the introduction of the SEM 6i and even 7i, we further gained market share in 2021, approaching 40% of the overall market in foundry logic and 34% of the entire semi market. So, with the introduction of Verity10, today, we believe we can extend our market share gains in this segment. And today or during this week, SPIE is taking place, and we have 4 customers that are presenting papers around how they're using the Verity10 in their applications and their fabs. So, if you have a chance this week, check out these talks. And with that, I'm going to turn it back over to Mike for question and answers.

Great. So, thank you, Keith, and we hope you really enjoyed learning about Sculpta and the new Verity 10 from Steve and Keith. Now it's time for the Q&A portion of the meeting.

[Operator Instructions] So, we believe we do have a question in the audio queue and that will come from Krish Sankar with Cowen.

I have a few of them. First one, just to clarify, Steven, when I saw the animation for the Sculpta, it said it was a ribbon beam. So, is this not an etch or a [indiscernible] technology? Is it more like laser or something like that? And then I have a couple of follow-ups.

Yes, it's a good question. It's a plasma ribbon beam. It's similar to etch and that it's material removal. But that's probably where the analogy ends. Etch is mainly used to transfer an existing pattern in photoresist and transfer it into the wafer, whereas here, we're shaping the mask itself.

Got it. And then is there a way you can help us quantify today how many double [indiscernible] are there in EUV in the N5, N3, N2 nodes and with that on shaping, what would that be for each of those 3 nodes?

Yes, I won't get into specifics about the nodes. It varies widely between customers. Everyone has different patterning schemes. Certainly, through those nodes, the number of multi-patterning layers goes up, node by node, everywhere. And I would say---you said 5,4,3, by the time you get to 3 and beyond 3 and 2-nanometers, it's a few. It's more than a few, I will say, more than a few in the advanced nodes.

Got it. And then maybe a final question, and I'll get back to the queue. How should we think about this? For example, like [indiscernible] 5 or 3, like, let's say, like [indiscernible] publicly said at 3-nanometer, they have like 24 EUV layers at 3 [indiscernible] more like 18 or 19. So you've seen a reduction in number of EUV layers. Is there a way to quantify how much EUV layer reduction you would see or litho [indiscernible] reduction you would see as you use AMAT pattern-shaping?

Yes. That really depends on how aggressively do the customers adopt Pattern-Shaping. So yes, hard to answer.

And then maybe one last thing and I can get back in the queue, Mike. Sorry about that. Historically, you folks have had some market share in patterning through your [indiscernible] volume [indiscernible] products. So now with Pattern Shaping, is it cannibalizing some of that opportunity?

Yes, it's a good question, too. I would say --- and I'll let Mike jump in, too. But I'd say it's net positive for Applied Materials, the more Pattern-Shaping that gets adopted, most of the cost savings is in the lithography. But really, the main goal here is just to reduce cost of chip making overall, the overall cost. So, in the end, we think this really helps everyone. It helps our customers and then that should make it possible for them to continue to invest across the board.

And next, in the audio queue, we have a question from C.J. Muse, we believe, from Evercore ISI.

I guess just a follow-up on the last answer. You talked about the main goal being reducing costs, yet the number you put up $250 million on 100,000 wafers is really about 1%. And so that doesn't seem like very much. So, I would think that there would be other benefits that would really drive adoption here. Can you kind of speak to how you came up with this cost savings number? And is it truly cost that will determine kind of adoption? Or are there other factors in your view?

Yes. Certainly, there are other factors. I think cost is the main factor, though. A couple of notes---the estimates we gave there are per layer adopted, per critical layer that's adopted. So, for each time you adopt a layer or use Pattern-Shaping in a layer, you would save those and it scales with the number of layers that you adopt. So, the cost can add up, and it is significant. But also, there are many other factors we mentioned. The complexity is probably number one. The complexity of multi-patterning, it's very difficult for our customers and it leads to longer development time. And eventually, those alignment errors can lead to performance and power issues. I think all of those are important.

Yes. And so hypothetically, let's say there's a customer in a future node who had 8 steps that were EUV double-patterning steps, and they chose to deploy our technology for just 4 of those steps. -- they'd be saving $1 billion for a 100,000 wafer start fab. So it can add up to some very large numbers and what customers do will, of course, be their choice. But it can -- the savings can be very large. And that's the capital savings. We also talked about the per wafer savings. So, if you care about your gross margin per wafer, this can really help. And then the other trend that we're seeing is that a lot of people have become interested in the energy consumption, the electricity needed to run a fab, especially if that uses EUV technology, tons of electricity, the materials and the carbon equivalent of those materials, water people care about, fabs are being built in the desert and this tool is able to save on all of those areas as well, not to mention the technical and the economic aspects. So, I hope that makes sense.

Yes. So, the follow-up question is really around customer adoption, you know entry into design tool of record pretty much well formed, right? So, I would think that this is very much incorporated into customer's kind of road maps and planned with the layers. So, can you speak to kind of what this kind of status is in terms of the big 3 and maybe size what this opportunity could look like for you guys in the coming handful of years?

Yes. We'll see how it goes. But I would say we're engaged at various levels with all the leading logic foundry customers and we've just started, at the very early stages. We've got our first adoption and shipping our first revenue systems. But we'll just have to see how the other customers, how all the customers adopt.

Yes. No, it's a great point. And a lot of times what happens, CJ, is we'll work for years, especially on a technology like this. This is something that only comes along once every great while. It's a brand-new kind of tool. It's something that didn't exist on the menu at all. And the idea was there. Steve talked about 6 years working with customers, actually working with them, introducing them to the idea and getting comfortable with the idea. And we've kind of kept this in our back pocket until we began to get commercial orders and now that we're shipping for revenue into production. So, we have enough confidence that we're willing to go ahead and make public what we've been talking about. But we'll have to see at this point, what customers do, how broadly, at what pace? And then the other thing that's interesting is because it's a new capability, it will take months and years for people to discover what they can do with it. And we'll probably be surprised by some of the applications that people come up with. Okay. So, I'd like to take the next question from the audio line and it's Vivek Arya from Bank of America.

My question is actually related to the prior 2 questions as to when does this start impacting Applied Materials? Is this a growth opportunity for you in the next 1 or 2 years? Does it become more impactful when [indiscernible] rolls out a lot more, right? You mentioned that you're just getting started. It sounds like a very exciting technology. But how much time will it take for the customers to [indiscernible] this in into their process. So, is this something that we should, let's say, pencil into our models for '25 or '26 or is it something that is more kind of medium-term than that?

Yes. I would say -- again, I'll let Mike jump in. But first revenue is now. It's relatively small, but we expect this to grow over the years and I would say, medium-term years. The next 2 to 3 to 4 years, we should see this start to ramp.

And one way I could add to what Steve said, so, we have had a longer-term financial model. And with revenue expectations through 2024, there is a little bit that was already in that model for this product. But of course, most of the growth of this product would be beyond that. And maybe the other thing, maybe I could ask it this way, Steve, would you be disappointed if you didn't generate lifetime revenue that was well over $1 billion?

Yes, I would be disappointed. A good way to put it. Yes, we vision this to be a $1 billion product. I think it's safe to say it will be hundreds of millions of dollars per year in that time-frame.

Yes. And then earlier, at the beginning, I walked you through our patterning served available market opportunity in our share, and that gave you something like a ballpark number of around $2 billion in revenue in 2021. So, this product alone has the opportunity to greatly accelerate our penetration into this part of the market.

Got it. And for my follow-up Mike, you guys said something interesting that, let's say, a customer would adopt this out of x out of 8 layers. What would make a customer not adopt this? If the value proposition is so clear, what would be the other factors that would cause them to not adopt this solution?

Yes, it's a good question. I think patterning, there's just dozens of different patterning schemes that customers develop themselves and choose between different layers and some of them are very, I'll say, straightforward to implement Pattern-Shaping for and others are not as straightforward and will take a longer time to engineer in. So that's one reason.

And the final one, this is probably a dumb question, but is this beneficial outside of the EUV environment also like somebody is using DUV or other litho? Or does this only have benefit in EUV?

Yes, it's a great question. Theoretically, it can benefit any type of lithography. It could be used for any note, any type of patterning schemes or any type of patterns. It's just that in EUV is where the value is the highest. So that's where we're going to see, I think, for the foreseeable future, that's where we'll see all of the adoption. But theoretically, there's no reason it can't be adopted anywhere.

And there's no China restriction of any kind, right on all this?

So for the same reason, currently, as far as we can see, we're only targeting the leading-edge customers that are using multi EUV patterning.

So the next question is going to come from Toshiya Hari with Goldman Sachs.

Maybe bring Keith into the conversation here, a question on Verity 10, if I may. Based on one of the slides that you showed, you guys have done really, really good. A good job in gaining market share in CD-SEM broadly over the past 7, 8 years. You talked about the breadth of customer interest in the Verity 10. I guess, can you speak to the differentiation of this tool vis-a-vis your nearest competitor in Asia? Do they have anything sort of close to what you're introducing today from a technology and cost performance perspective?

Great question. Thank you. So, the Verity 10, I think the differentiation that we see is the ability to go to these very low landing energies. So, in the slides, we said below 300 EUV, but the tool really operates quite a bit further below that. And so, what we're seeing is we're able to do very precise and accurate measurements with very limited resist shrinkage. And from what we can tell, we think we're ahead of our competition somewhere on the order of 1 to 2 years with this type of technology. And every place that we've gone and introduced the product, you saw there were over 30 systems out there, we tend to validate the fact that this is a unique capability for the tool.

Understood. And then one for Steve on the Pattern-Shaping side of the portfolio. Maybe ask the market opportunity question in a different way. With the customer where you've secured the PTOR, can you speak to how many of these tools that they would need to buy from you guys for every 100,000 wafer starts per month, assuming 1 layer or 2 or 3 layers, what have you?

Yes, I probably shouldn't answer that question. Two things we don't like to talk about, 1 is the throughput of our tools and yes, I don't think we can answer that.

To your prior comment and Mike's comment, a couple of hundred million dollars in a couple of years I think you said today, that's sort of how we should think about the opportunity at a high level.

Yes. I think a few hundred million dollars per year for the next few years is roughly right. Reasonable goal.

Your question Toshiya was really a good one, but just as a matter of principle, we don't disclose average selling prices. And I think if we were to give units for---you'd pretty soon be able to back into it. I think what you probably can tell is that there's a great deal of value that's being delivered when a customer chooses to deploy this. And so, you would have to imagine that we're going to do our best to share in that value as well. So, our next question is going to come from the line of Harlan Sur with JPMorgan.

So on the Sculpta patterning product, good to see the team unveil and commercialize this product and your directional etching technology. You guys did give us a sneak peek back in April. So, thanks for that. You articulated manufacturing cost savings, which I assume brings in faster process module throughput advantages of your single-pass solution. So, can you guys just give us a rough sense on the throughput differences let's say, a [indiscernible] formation in a foundry logic process, your Sculpta based approach versus the EUV double-patterning approach?

Yes. throughput might not be the right question to ask, maybe cycle time. Cycle time. So yes, cycle time is significant. It's a good question. Really should be -- is more something to ask the customers -- it's the customer's process flow that's going to determine that. It can vary widely, but to save a whole EUV loop, I hesitate to answer. It's significant. It takes a lot of time to get a lot of wafers through that loop. But yes, I think it's too hard to answer. It really depends on the customer and their scheme.

Okay. And then back in April, there was another innovative use case, which was more kind of manufacturability focus, which was hard mask defect removal. Can you guys just give us an update on potential commercialization of such a solution?

Yes, absolutely. I would say all of the customers we work with explore all the different kinds of applications we've worked together on and so I'd say mask elimination is always #1. It's the most compelling and it's the one that we thought would get adopted first, and it is, in fact, the one that was adopted first. But I think the, stochastic bridge defect reduction is right behind it. All the customers are exploring it or working on it.

Yes. Thanks for remembering that, Harlan. I believe that's in the new ways to shrink master class that we did Yes. So those slides are still out there. Somebody is not familiar with this and doesn't remember the way you do. We did depict what those bridge defects would look like and how we could clean those up prior to etch.

Okay, so I'll stay tuned. Just one last question. In process control, the team, as you mentioned has driven strong market share momentum in eBeam. You guys do a really great job of leveraging your foundational technologies across all of your platforms. Again, you guys had a master class actually back in December, right, on your field emission technology, a lot of advantages of CFP, right, narrow beam, higher resolution, which actually seems to be the key features integrated into the Verity 10 platform. So, is Verity 10 based on this differentiated CFE technology?

It's a really good question. And the answer very simply is no, it's actually based upon TFE technology. We were able to get the performance of the resolution and the low landing energy without using the CFE technology. And the reason we made that decision is because this segment is somewhat cost sensitive, and there is a strong competition in this segment. So, we decided that to have a tool at the right price point, it would be better to try to engineer it to use the TFE technology. The CFE technology would be better. You're correct in that assumption. But it does drive fairly significant cost into the engineering of the product. So, I wouldn't rule out us eventually taking the CFE technology to the Verity platform and using it in CD applications. But today, we didn't need to do that in order to meet the high EUV NA a requirement. So, we didn't build the cost into the tool.

Our next question is going to come from the line of Pierre Ferragu, who is with New Street Research.

Steve, I was wondering on this question of [indiscernible] and like the pattern-shaping technology you adopted like the limitation, I can understand from my very very light knowledge of the technology that you have like a unique, like a single direction ability to increase the size of the pattern. And then of course, you can increase it, you can get it smaller. So, is that the right way to think about which layers are going to be more challenging for the technology to be adopted? And would you be able to give us an example of a specific layer that would never be a candidate because the size of the PTOs are too small or like elongating in only one dimension is never going to make it work? Or is everything potentially a candidate?

Yes, it's a good question. In general, I think every layer is a candidate. There's no real limitation. And like I mentioned earlier in a different question, there are some customers with certain patterning layers that --- in certain schemes where it's not so straightforward to implement Pattern-Shaping, it's not simple, but there's always opportunity to rethink the scheme for those layers. And this is a brand-new technology. So, all of our customers have been marching down their road maps without this capability. And so, everyone's road map from the beginning doesn't include it. Once you have the capability, our customers --- if you --- from the beginning of a node, say, for example, if you know you have this capability, you can start to think about what's the best patterning schemes and best ways to take advantage of Pattern-Shaping. So yes, I don't think there's any layer that there's no feature size too small or a size limitation or anything like that. It could be applied to any. It's just some are easier than others.

And when you say easier than others, it means there is like a kind of a redesign, kind of like changing the way you design that?

Exactly.

Okay. Then I have another question on like the [indiscernible] application of the technology because today, you've presented it as you can believe [indiscernible] by a single patterning layer. Another way to think about it is to say it's enhancing a single patterning layer. And in this way, would you be able to enhance the dual patterning layer? And imagine that in a couple of years from now, some of our clients are going to introduce a kind of like artificial like triple patterning EUV where you have actually 2 patterning plus levels of shaping on the back of that. Is that the right way to think about that?

Absolutely. Yes, it's absolutely the right way to think about it. Like I mentioned earlier, eliminating an EUV layer is just a very compelling value statement. And so that's where the early adoption is. But there are dozens of ideas or different ways we can, like you say, enhance a patterning capability or even create device structures that aren't possible to be created otherwise. Lots of ideas we have for other applications that I think will come down the road when our customers get comfortable with the technology. And this probably dozens more that we haven't thought of yet. So, you are thinking about it the right way, yes.

And one last question, maybe a bit of a stretch. When I look at the picture of your tool, I think you have like one chamber and then you have 4 units around the chamber. So, are you going through like an integrated process steps to achieve that? Or is that just splitting the workload.

Yes, yes. It's a good question. Yes. No, there are not 4 separate kind of process steps. It's just the same --- that's the same kind of chamber replicated 4 times -- just purely to get as much productivity out of a small footprint. So, it's just clustering for identical systems. You could just have one and do the same job, yes.

So, I'd like to take a writing question from one of our buy-side analysts on the East Coast. And the question is that EUV is here, but High-NA EUV is coming. And one of the benefits that we're hearing about with High-NA EUV is that it can replace EUV double-patterning. Therefore, is the Sculpta product, something that has a relatively short life span in the industry? Or is it not obviated by High-NA EUV when that comes in?

Yes. It's another good question. So, for sure, high NA improves resolution. It enables smaller dimensions, and it's going to mainly be used to shrink pitch. But one thing it doesn't address is this tip-to-tip trade-off. So, as you squeeze pitch, it will continue to be more and more difficult to pattern-type tip-to-tip spacing. So, we think that Sculpta will be applicable for high NA layers just as it is for low NA. Okay. Great.

So our next question will be from the audio queue. And I have a question from Atif Malik from Citibank.

Yes [indiscernible] a very big deal. And Mike, I was at SPIE yesterday, and I could not help notice how much time [indiscernible] CTO spent on the need to improve the productivity of EUV for double patterning and multiple patterning at least through the High-NA. So, all this stuff does make a lot of sense. Actually, my question is on the memory side in the [indiscernible] side, are there applications or steps where the EUV steps [indiscernible] DM devices can be replaced by Sculpta.

Yes. Right now, we aren't focused on memory but I think as memory starts to implement EUV and then maybe get into multi-EUV, then the same applications will appear. I will say we've done a little bit of work with memory customers just identifying non-mask elimination applications. So, kind of like what Pierre was saying earlier, just ways that we can enhance existing patterning even for 193i. And so, the applications are there. I think they'll be there in the future. It's just a question of value capture.

And we have a question on the line from Brian Chin, who is with Stifel.

Maybe just a couple of quick things. You referenced a $350 million capital cost in terms of the second EUV workflow and a $250 million cost savings. And so that residual is $100 million. And I guess can you break out sort of what's in that $100 million, obviously, the patterning, maybe is the highest value add of that. But there are other things like cleaning and metrology? How can you kind of help us understand how you share in that value creation of that residual?

Yes. So, for the model we use, we have an internal model for the lithography step, which is where the most of the savings are. We use kind of generally accepted numbers for lithography, ASP and productivity. Certainly, the lithography tool is the biggest chunk of it, but all the other steps that are eliminated are significant. So, they're all-important part of the savings.

So Steve, if you don't mind, I'd just kind of add in there. When you look at the adoption of Sculpta, probably does not change the metrology intensity. You're obviously doing a patterning step, and you have to go in and verify the pattern, whether the patterns created by the second EUV steps or it's created by Sculpta. So, from our perspective, I don't think our customers would save anything in their metrology budgets with this technology.

I mentioned this, there's also --- I don't know if you can quantify this as a significantly tighter footprint that this workflow would replace relative to what...[indiscernible] workflow we have?

Sure. Yes, absolutely. Yes, that's right. That's part of the model. Yes.

Yes. And does that make it even for, say, greenfield facilities in terms of being -- customers being more thoughtful, -- is that -- given the potential productivity enhancement of the [indiscernible] tools in a given that real estate, is that something where this is even more right for like greenfield facilities that haven't yet or being constructed?

Yes. I'm not sure I would say it's more right for it, but you're thinking about it the right way. It's -- when you're -- if you're designing a greenfield fab, it just it saves a lot of cost. Yes.

Yes, when you think about -- we have our ESG commitments and program and one of the things that we've endeavored to do is we want to save, we call it 3 by 30. So, 30% reduction in electricity usage, 30% reduction in materials and then a 30% increase in footprint density because the clean room and all of that is real energy intensive as well. That's half the energy used in the fab is below the clean room. So, this tool could actually help customers to meet their environmental goals as well.

Very last question. Is the lead time for this tool less than the 2-year lead time for the EUV?

Yes, it is. So I'd like to go back to the next question, and that's going to come from Joe Quatrochi, who's with Wells Fargo.

I just wanted to kind of go back to the point on High-NA. I just want to understand, too. So, I guess it seems like this product is trying to kind of maybe intersect the same kind of time-line and High-NA coming into the high-volume manufacturing. Is that the right way to think about it? And I guess, in the discussions you've had with your customers, has that changed the way that they're thinking about implementing High-NA?

No, I don't think that's the right way to think about it. So, the High-NA is a few years away and customers are adopting Sculpta now. So, I wouldn't link it to High-NA. And I would say I don't think Sculpta has any effect on High-NA adoption. I think they're independent. Like I said earlier, Sculpta is applicable to Low-NA, High-NA equivalently. And for customers, they're adopting High-NA for different reasons than they would adopt Sculpta.

Let me just see if we have another caller, Timm Schulze from Redburn out of the U.K.

I have 2. The first was you mentioned that you've been selected as process to a record that you are shipping for production. Just wanted to understand when you would expect that to start shifting into volume manufacturing. When will you get a real production volume test of this technology?

Yes, it's a good question. I think again, it sort of depends on our customer and how well they execute. But probably in the 2 years' kind of time frame, roughly.

Got it. Got it. And then my follow-up question was one around risk. There's obviously a general risk aversion within the industry. Are you sharing any commercial risks, any financial risk with your customers around adoption? And as you think about how this might be moving into volume production; would you expect the customer to maybe run it at parallel with double-patterning and then kind of dial down one and dial up the other? Just kind of how should we think about that?

Yes. So, first part of the question on risk and nothing out of the ordinary, and we're not sharing risk in any different way than we would for any other product---Oh in parallel again, I can't really speak for the customers and what they're going to do, but I wouldn't expect that.

So, we're getting quite late in the hour. We've overrun a bit. What I'd like to do is just pull 2 analysts who have not had an opportunity to ask a first question and see if they're still on the call. So, Quinn, I'm going to come back to you and see if you're still there and if you can unmute Quinn Bolton?

I just wanted to come back and ask on the High-NA, why this doesn't potentially push out adoption of High-NA. It sounds like the answer is that this improves tip-to-tip spacing, but doesn't improve resolution. So, if you want to improve pitch, you've got to go to High-NA and then you get the advantages of Sculpta on tip-to-tip. It's not exclusive, they're complementary.

Exactly right. Yes.

And then finally, I'd like to go to the line of Tammy Qiu from Berenberg in the U.K.

So my question is about when going forward, when you move from things like 3-nanometer to 2 [indiscernible] at some point below 1.4, you probably had to do CFET. How does these 2 works with the further adoption of NA and High-NA? Does it work well as it is described today with the transistor kind of patterning method changes? And also, another question is, when we actually talk about this tool is making double-patterning easier, can we actually apply this back to the ordinary, for example, if someone today is working on 10-nano, really wants to go down to 7 nano, can this to be kind of reengineered to make a [indiscernible] -based double casting easier?

Yes. I may have lost track of the different parts of the question, but I'll start with the older nodes, yes, it can theoretically could be applied to older nodes. It could be applied to 193i layers. There's nothing stopping anyone from doing that. And you would see the same kinds of application advantages. You could eliminate layers. Just the value there is lower. So, it's just a question for the customers, whether it's worth it for them to bring in a new technology and disrupt something that's already working well for them. But there's no reason you couldn't. And then the High-NA question, I think we've talked about it before, but Sculpta and Pattern-Shaping is just as applicable for High-NA as it is for Low-NA. And High-NA will suffer the same kind of tip-to-tip problem that low-NA does.

And not [indiscernible] the 2 works the same as we move to different [indiscernible] this time like, for example, if [indiscernible] will be adopted.

Yes, that's right. We got a lot of questions about different device types, Gate-All-Around CFET. This is a patterning tool. So, the patterns are sort of generic, especially, for example, in the wiring, interconnect wiring is all the same. And then even in the device patterning, contact patterning, we're just making shapes on wafers and then what's done with those shapes and what device structures you end up with afterwards is sort of independent.

Okay. Last one from this. So, this tool will help with multi-patterning or quadruple pattern besides double patterning's?

Yes, sure. Yes, it could absolutely be used for especially in 193i. In the later stages of using 193i, there were some layers that required many, many exposures, 3, 4, 5, 6, 7 exposures of 193i to make 1 pattern. And for sure, Pattern-Shaping could help take away 1 or 2 of those layers.

So we do have some follow-up calls in the queue. What we will do -- we'll close the call now, but we'll send an e-mail to each of you and see if we can help you offline today as soon as we can find you. And what I'd like to do is thank you, everybody, for attending and giving us your great questions. I'd like to as well thank Steve and Keith, for your presentations today and for helping us to answer all the questions. And if anyone still has a question for the Applied team, please just send an e-mail message to either [email protected] or [email protected], and we'll get back to you today. So, thanks for joining us today, and have a great rest of your week.