Tokyo Electron Limited (8035) Earnings Call Transcript & Summary

Now it's time for us to start Tokyo Electron IR Day. Thank you very much for joining us today despite your busy schedule. I am Yatsuda of IR department, acting as a moderator in today's session. It is the second time that Tokyo Electron holds IR Day. Last time, we organized IR Day to present our revised midterm environmental goals newly released [products] and our help of digital transformation, which moved to a new location. Today, we hold IR Day as we find it as a good timing after publishing our first integrated report in August this year. We will present various activities related to ESG, value chain and corporate value creation. We would appreciate it if you could kindly understand that we cannot talk anything about the current financial performance in this IR Day since it is before the second quarter financial announcement. Now let me introduce the 8 SMDs on our site. Mr. Tetsuo Tsuneishi, Corporate Director, Chairman of the Board.

I am Tsuneishi. Thank you very much for joining us today. We're very happy to see so many people joining in this IR Day. We're going to have 3-hour session, very long session. I really appreciate this opportunity. We'd like to share our idea and our basic strategy, including ESG -- with focus on ESG. We'd like to talk what we value and how we promote and contribute our growth and the contribution to the society. And also we'd like to talk about the semiconductor technology innovation in the future and our strategy -- product strategy. So there are so much items we want to share, taking this opportunity. I hope today's meeting will be fruitful for all the people who join us today.

Next, Mr. Toshiki Kawai, Representative Director, President and CEO.

I am Kawai. Thank you very much for participating in this session despite your very busy schedule.

Next, Mr. Yoshikazu Nunokawa, Corporate Director, Executive Finance Vice President, General Manager, Global Business Platform Division, Finance Unit.

I am Nunokawa. Thank you very much.

Next, Mr. Keiichi Akiyama, Vice President and General Manager, CTSPS Business Unit.

I am Akiyama. Thank you very much. Today, I want to talk about EUV technology, relevant technologies.

Next, Mr. Isamu Wakui, Vice President and General Manager, ES Business Unit. Next, Mr. Hiroshi Ishida, Vice President and General Manager, TFF Business Unit.

I am Ishida. Today, I'd like to present the film deposition new approach on behalf of TFF BU.

Next, Mr. Sumie Segawa, Vice Division, General Manager, Corporate Innovation Division.

I am Segawa. Thank you very much for joining us today.

And Dr. Akihisa Sekiguchi, Deputy General Manager, Corporate Innovation Division.

I am Sekiguchi. Later, I'd like to talk about the technology trends and business opportunity for our company.

Before starting the presentation, let me explain the flow of today's meeting. The agenda of today's meeting is shown on the slide. We will have 2-hour presentation session, including 10-minute break in the middle. After all presentations, we'll have a question-and-answer session. We plan to close this meeting at 5:30 Japan time. This meeting uses 2 channels on WebEx, providing simultaneous interpretation between Japanese and English. As we explained in our e-mail, you are kindly requested to use apps on PCs or mobile terminals if you plan to ask questions. But if you are not going to ask questions, you can use telephones. Since this is a meeting for institutional investors and analysts, we appreciate your understanding that we receive questions only from institutional investors and analysts as usual. We'll upload the audio contents of this meeting both in Japanese and English later. We will be happy if you also refer to them. Now Mr. Kawai, CEO, will present aiming a global excellent company, talking about our major initiatives for value creation and value chain.

Good afternoon. I am Kawai of Tokyo Electron. Thank you very much for joining us in our IR Day today despite your busy schedule. Like last year, due to the COVID-19 spread, we hold this IR Day as an online meeting. But I'm very delighted to talk with you in this opportunity. Along with the shift to data-driven society and to decarbonation society, the semiconductor devices become increasingly important. And accordingly, our company is expected to exercise more and more important roles and responsibilities. The title of my presentation today is Aiming for Global Excellent Company. I would like to present the business environment and our major initiatives. When I look back the situation of the world from last year to this year, we have been struggling with the global spread of the COVID-19 infection and a number of natural disasters in climate, such as torrential rains in Japan, hurricanes and cold waves in North America, and wildfires. There have been various issues globally, including geopolitical issues like trade frictions and human rights issues, which have had considerable impact on our society and our daily life. In parallel, digital transformation proceeded in our life and every industry last year, which highlighted the significance of the semiconductor devices essential for ICT. The transition to the data-driven society is progressing at an unprecedented speed. And also, we need to address the global environmental problems. I mean -- those circumstances, the tidal wave of digital and green is spreading across the world. What I mean by green here is carbon-neutral aiming at decarbonization to suppress CO2 emissions. In order to build a strong and resilient society in which economic activities are not disrupted in any situations, the world is implementing ICT and digital transformation and striving to realize a decarbonized society. In the future, digitalization in every industry, such as autonomous driving, smart cities, smart factories, smart agriculture and smart medicine, is expected to spread widely through the society. And it is semiconductor devices that supports all of these at their bedrock. The semiconductor devices used to be dubbed as rice of the industry in Japan, meaning the essential building block of the industry. Now as an essential building block of the industry, society and our life, it is playing wide-ranging roles. In the past, the semiconductor market was driven by products, mainly by electronic devices such as PC and smartphone. At present, various services using data, in other words, value that people want to realize, are the main drivers. It is about 70 years since the transistor was invented in 1947. The global semiconductor market was about $440 billion in 2020. And the market size is expected to reach about $1 trillion in 2030. This means the market will be more than doubled in size in the next decades. In 10 years' time, we will see another market of the equal to the current market in size. Accordingly, WFE market size is expected to exceed $90 billion in 2021, but it is just the beginning. Electric vehicle, fuel cell vehicle and autonomous driving will be spreading. In addition, 5G will be widely adopted. In parallel, post-5G development will be proceeding. To realize ICT, digital transformation and decarbonization, the semiconductor is required to have more , faster speed and higher reliability with lower power consumption. Accordingly, the WFE market will grow further more. This slide shows the trend of WFE market that our company analyzes. The blue on the left represents the past, while the green on the right represents the future. As you know, in the past, semiconductor market growth was driven by emergence of new models of PC and mobile phones. Therefore, once their supply got stabilized, the demand for semiconductor devices slowed down, which was called silicon cycle. The arrival of data-driven society, together with IoT, however, triggers an explosive increase of the semiconductor demand. Continuous capital investment to leading semiconductor devices supporting value-driven consumption is essential. The IC manufacturers having high market share are strongly aware of supply-demand balance. Based on these factors, we believe the WFE market has entered a new phase in which it will grow strongly in the staircase shape. As I said so far, due to high expectation to the semiconductor and WFE market, Tokyo Electron is expected to exercise more and more roles and responsibilities toward the future. As our corporate purpose, Tokyo Electron implements our corporate philosophy. We strive to contribute to the development of dream-inspiring society through our leading-edge technologies and reliable service and support. Specifically, the implementation of the corporate philosophy means that by leveraging the expertise of the process to manufacturer, we will make an effective use of all resources, including the employees who are the source of value creation, contribute to both digitalization and dreaming through the semiconductor technology innovation to expand the longer-term profit, enhance corporate value continuously and make all people around our company happy. Based on this concept, we published our integrated report in August this year. Today, I will touch upon our efforts for value creation. That is one of the topics presented in this integrated report. To expand the longer-term profit and enhance corporate value continuously, we have defined our materiality. Based on the management foundation, including safety, quality, governance, compliance and risk management, our materiality is composed of product competitiveness, customer responsiveness and higher productivity. To intensify this materiality, we will implement the strategy, making the maximum use of our expertise and strength. Our strengths are shown here. One and only WFE manufacturer offering process tools for the 4 consecutive processes essential for the advanced device patterning technologies. Our share in these products ranks #1 or #2 in the world. In particular, we maintain 100% share in the coater/developer for EUV lithography, which is essential for the leading-edge device nodes. We have the world's largest installed base of about 78,000 units, which increases by 4,000 units every year. Based on this, we have built a field solution business model. Based on these strengths, we will keep a proactive R&D investment to create innovative technologies leading the world. By aligning technology road map of multiple generations with the customers and supporting their manufacturing lines of the current device nodes, we will develop products with high success probability and create unique high value-added technologies that only TEL can develop to support digital and green. For manufacturing aspect as well, we have been building our infrastructure. In 2020, the new production building started operation in Tohoku plant and Yamanashi plant. And in May this year, we announced that we acquired the land in Miyagi plant, where we'll support the stable supply to address rapidly growing semiconductor demand. Towards the sustained growth of our business activities, we are building a resilient supply chain based on the solid relationship of trust with our partner companies. For our partners, we perform STQA, Supplier Total Quality Assessment. In addition, every year, we conduct CSR, BCP and survey on conflict minerals and environmental laws and regulations to promote the supply chain management. In addition, we have established Miyagi Technology Innovation Center last month, aiming at merging diversified technologies of our suppliers to create new innovation. We will keep working on sustained growth of the industry through collaboration with the partner companies. Next, I will talk about our sustainability efforts, including the ESG initiatives in our value chain. To contribute in the development of international community, we are promoting the sustainability efforts through our business operation. We have linked the United Nation's SDGs and our corporate materiality. We carry out group-wide activities and also participate in international initiatives. Along with this framework, we analyze impacts on our opportunity of our business and disclose relevant information. Our activities are highly recognized across the world. We have been selected on the list of global-leading ESG investment indices. We will make a continuous effort so that we can win trust from our stakeholders. We are working on reduction of CO2 emissions with 3 perspectives. The first perspective is to contribute to enhanced per watt performance reduced power consumption of semiconductor devices through our semiconductor manufacturing technologies. The second is energy conservation of our products and business activities. Toward the midterm environmental goals of 2030, one of the most demanding goals in the industry, we will strive for decarbonization. For 70% reduction at our sites, we mainly work on 100% renewable energy use. Yamanashi and Miyagi plants have already switched to renewable energies at 100%. Kumamoto and Iwate plants plan to switch next year. The third is the E-COMPASS initiative that we announced in June this year. This is a new initiative to build sustainable supply chain and promote global environmental conservation activities throughout the supply chain. Next, I will talk about our efforts for safety, in particular, incident. This figure shows TCIR, total case incident rate per 200,000 working hours. The dotted lines represent the average of material vendors, IC vendors and tool vendors. The solid lines indicate the value of IC vendors, A and B, and those of competitors, C and D, as well as our own values. As you can see, our company fits in world-class safety. While expanding the business size, we maintain a high level of safety. What we aim at, however, is zero incident. Under the banner of safety first, we will make every effort to improve safety in every business activity of our company. It is our employees that perform all of our business activities and realize our sustained growth. It is people that drives the company. Employees are the source of value creation. Based on the idea, we focus on the 3 things. First of all, code of conduct, which is based on the corporate culture we have committed ever since our foundation. We call it TEL Value to be shared with our employees. The second is motivation-based management. Employees performance is determined by the ability and motivation. They were screened by ability when they entered the company. Motivation is critical to raise their performance. To enhance their motivation, it's important that they have dreams and expectations for the future of the company. They have an opportunity to challenge without fear based on strong financial basis. They are fairly evaluated and recognized with globally competitive reward. And they can communicate openly. We are taking various measures to enhance the employee engagement, such as introduction of new HR system designed to facilitate dialogue between supervisors and subordinates. The third is diversity and inclusion, focusing on perspective 3G, namely global, generation and gender. We will announce specific goals this year to reflect them in the corporate governance guideline. This slide shows the Code of Conduct, TEL Value that I talked about. Pride, challenge, ownership, teamwork and awareness. You can see the idea of each of 5. In challenge, for example, it states we will be generous for failure and highlight importance to learn from its process and results. This represents our basic idea in TEL. Fiscal year 60 starts in April 2022. Based on TEL Value, we will explore a new era to keep being dream-inspiring and vivid company. At present, we are operating 76 sites in 18 countries throughout the world. Looking at the customer's future investment plan, however, we expect our sites, employees and suppliers will further increase. We are determined to be highly aware of human right, including employment conditions, work environment and occupational health and safety throughout our supply chain and contribute to development of dream-inspiring society. To increase our longer-term profit and enhance our corporate value. We set the goals of operating margin and ROE in the midterm management plan, which is our offence management strategy. In parallel, we are committed to safety, quality, compliance, employee engagement, risk assessment and security. These activities, essential for our business sustainability, our defense strategy and, at the same time, it's our strength. Each one of the employees will work on these to further strengthen our management foundation. future the semiconductor device realize ever-evolving semiconductor device, the WFE market supporting semiconductor devices now in the further growth phase. The corporate growth is driven by people. The employees are the source of value creation. Tokyo Electron will implement the corporate philosophy, leverage our expertise and diversified resources, create innovative, high value-added technologies that only TEL can create and provide these technologies to the society. We will keep challenging and evolving from now on. And we aim at true global excellent company strongly trusted by all these stakeholders. Thank you very much for your kind attention.

Next, Ms. Segawa, Vice Division General Manager, will present supply chain initiatives for the environment.

I am Segawa, Vice Division General Manager of Corporate Innovation division. I will present E-COMPASS, our supply chain initiative designed to enhance the environmental conservation efforts. On June 16, 2021, we announced initiation of E-COMPASS, the supply chain initiative focusing on the environment. E-COMPASS is an abbreviation of Environmental Co-creation by Material Process and Subcomponent Solutions. E-COMPASS also represent environment compass. We want to make this initiative a real compass leading our community. The logos shown in this slide expresses our resolution towards this initiative. C of Compass uses a symbol of infinity, expressing sustainable use of resources and energy and permanent relationship with our stakeholders. The color gradation from blue to green represents our future journey toward environmental footprint reduction through co-creation with our partners. This is one of the important initiatives in pursuing our corporate philosophy to realize digital and green society that Kawai-san said earlier. I will present the 3 underlying factors of this new initiative foundation. The first one is climate change. As you know, over the past few years, unprecedented massive disaster took place in many parts of the world. Climate change induced by global warming is one of the factors to cause these disasters. The international community is raising awareness of environmental issues, regarding them as intimate crisis for us. As all business across the world are expected to address the environmental issues, the IT industry is no exception. Our customers, namely IC manufacturers, become increasingly aware of the environment. Tokyo Electron, as a global citizen doing business on this planet, is determined to be responsible for building the supply chain with high level of awareness of the impacts on climate change. The second factor is an increasing trend of international treaties and legal requirements for the environment. This figure shows that international treaties, laws and regulations for the environment have been increasing year by year, which is on the horizontal axis. Some of these legal requirements have significant impact on business activities. In order to prevent the legal requirements from becoming our business risks, we need to assess the future trend and take proactive approach. An effort to minimize business risk in the entire supplier chain will become increasingly important. This slide shows the third factor. Now that the semiconductor industry becomes essential in the society, Tokyo Electron must take responsibility as a company aiming at the global excellent company and take leadership in achieving sustainability in the entire industry. We deliver our products to IC manufacturers to help them realize leading-edge devices featuring high-performance and low power consumption. As IC devices manufactured by applying our leading-edge manufacturing technologies are widely used in the society, they will contribute to reduction of environmental impact for years to come. Dr. Sekiguchi will present the details of reduction of environmental impact through our manufacturing technologies. Our business activities to pursue both digital and green are supported by the alliance with many partners. In order to raise awareness of the environment, together with the partners, we launched E-COMPASS as a supply chain initiative focusing on the environment. This shows mission, vision and value of E-COMPASS. The mission is that we will promote green performance enhancement of microelectronic industry through supply chain-wide collaboration to reduce global environmental impacts. The vision is that we will work on the green technologies in the entire supply chain to co-create sustainable and affluent future where humans and nature coexist. The value is that we will provide high green performance microelectronics manufacturing technologies and process tool technologies, address legal regulatory requirements and reduce environmental footprints in our operations under this mission and vision. By implementing the mission, vision and value of E-COMPASS through our business activities, TEL will make use of all resources realize both digitalization and greening in the society. By promoting our active environmental initiative, we will pursue our corporate philosophy. We strive to contribute the development of dream-inspiring society through our leading-edge technologies and reliable service and support. Next, let me talk about specific E-COMPASS activities. There are 3 major pillars. The first one is to pursue sustainability in the entire industry through enhancement of partnership. The second one is to provide environmentally conscious products by realizing process tools free from environmentally hazardous materials. And third one is to accelerate innovation of manufacturing technology by proactively developing green technologies. We will work on these activities to promote environmental impact reduction and green technology innovation in the entire supply chain. Next, I will talk about what we are doing in these 3 activities. The first activity is the enhancement of partnership. This slide shows CO2 emissions in the entire value chain of our company. In comparison with CO2 emissions of TEL itself, which is 186,000 tons, the CO2 emissions in Scope 3, which covers upstream and downstream of supply chain is more significant. The CO2 emissions in downstream, in particular attributed mainly to use of our products. Enhancing environmental performance of our product directly lead to the reduction of the environmental impacts of entire semiconductor industry. We will encourage our partners to understand the mission of E-COMPASS to enhance green performance of microelectronics industry and strive to establish solid partnership. This shows examples reduction of environmental impact in procurement distribution. The example on the left is model shift between the suppliers in Western Japan and our Kyushu and Miyagi sites. Truck transportation has been replaced by railroad transportation to reduce CO2 emissions. From this fiscal year, model shift effort will be expanded to the suppliers in Kyushu so that we can further reduce CO2 emissions. The example on the right is the introduction of returnable packages and containers, such as plastic trays, and innovation of packaging materials to reduce consumption of air caps and disposable carton boxes. In the upstream of our value chain, each one of these activities may look insignificant. But we will review each business activity and accumulate small improvement little by little, so that we will raise awareness among ourselves and our partners. The second activity is to develop process tool free from environmental hazardous substances. Our process tools are composed of parts manufactured by many partners to be delivered to our customers. We believe it is important to build supply chain pursuing minimization of environmental impacts since the environmental regulations are rapidly increasing. By enhancing the alliance with our partners, we'll be able to eliminate substances of environmental concern from the component we purchase and provide environmentally friendly products to our customers, so that customers can use our products for years with peace of mind. We can build a solid relationship of trust, not only with the customers but also with all stakeholders and eventually enhance our corporate value. Now let me show you some specifics. As a first step, we will learn from Europe and the United States, which are advanced in the environmental initiative, to proactively identify substances of concern for negative impacts on environment and human body and share information with the partners. For the substances of very high concern, we will proactively find alternatives and develop a method to minimize their release to the environment. Joint technology innovation with partners may be very useful for us. The third activity, the last one, is to develop the green technologies proactively. The traditional product specifications were composed of hardware and process performance specifications and operation safety specifications. We will add environmental specifications to accelerate development green technologies for our best products and best technical services. The green technologies will serve as our competitive edge to facilitate the technology innovation. Use of energy, water and chemicals require drastic technology innovation. We will enhance the alliance with our partners so that we can propose attractive solutions leading to reduction of environmental impacts. Every site of TEL has accelerated development of green technologies. Let me present an open innovation together with the partners. This is Miyagi Technology Innovation Center whose construction was completed on September 22, 2021. This center was built to enhance development of innovative manufacturing technologies at TEL Miyagi, which manufactures etching systems. The center leads the development to drastically improve performance, quality and lead time of our products. And it also have lab area and open innovation areas where we can use for the collaboration development. Making active use of this co-creation area, where we'll promote development of green technologies in the E-COMPASS initiative. So in my presentation, I presented our activities of E-COMPASS initiative. To implement the value of E-COMPASS, that is we will provide high green performance microelectronics manufacturing technologies and process to technologies, address legal and regulatory requirements and reduce environmental footprint in our operations, we will explore new partners and seize technologies in the world to facilitate the activities. Really appreciate your continued support. Thank you very much for your kind attention.

Next, Dr. Sekiguchi, Deputy General Manager, will present technology trends and TEL's business opportunities.

Thank you very much, Yatsuda-san. I'm Sekiguchi, Deputy General Manager of Corporate Innovation Division. I will talk about technology trends and TEL's business opportunities. This is today's agenda. Firstly, I will talk about the recent market trends. Then I will share my ideas about how these market needs will impact development of semiconductor devices and how logic, memory, sensor and other leading devices would evolve. And finally, I will present the direction of our development activities and future needs. Before getting into the complicated topics, however, let me warm up a little bit. I use these 2 photographs quite often in the conferences recently. On the right, you can see Ford Model T, a car more than one century ago. It was manufactured in an innovative process of low-cost, high-volume production. It features 20 horsepower. Maximum speed was about 70 kilometers per hour. It is quite fast. But in terms of safety, the Model T is far behind the autonomous driving vehicle, which uses numerous sensors to bring its passengers safely, without any stress, to their destination. The autonomous driving vehicle is the kind of collection of semiconductor technologies. However, Ford did have one unique feature, the evil supercar on the left cannot match. That is, it can operate and can be made without any semiconductor devices. But what I want to highlight here is not about the restriction due to the tight supply of semiconductor devices, but about the auto models have grown to become a platform to drive the semiconductor industry, although it took some time so far. Some more information. I'm sorry, let me add some more. Semiconductor radio was mounted to Chevrolet model in 1922. At that time, price of the car was $850, while the radio was $200. Electric vehicle was originally invented in 1830. Its share grew gradually until 1870, but it was driven out of the market by cheap Model T. I sense something in common with semiconductor technology in this story, such as technology innovation and cost reduction. At present, semiconductor device is essential for a car, logic, memory, sensor, communication and display. Various semiconductor devices are mounted on a car. An instantaneous decision made by AI on each site, which is essential for autonomous driving. Building communication infrastructure to send data collected by sensor through high-speed network is also essential. The cloud computing infrastructure, which efficiently process the data, evolving by using various innovative accelerators. AI accelerator, Quantum Accelerator are featured in the media, but they are not free from problems. The server farm shown on the right, which looks a little bit untidy have many problems. Increasing power consumption, heat dissipation, delay taking place every time data are transferred. There are so much room for improvement. But this is why there is no end in the research activities. Now that a car is equipped with leading-edge technology node devices, both logic and memory, the car is driving the semiconductor industry as one of the launching platform of the semiconductor technology. Machine and devices generate a huge amount of information. The same applies to mobile devices, which has been driving the industry so far. People with wearable devices, in a sense, is also a platform for the technology. Health monitoring is the promising category to grow in the future. are also important, though they are not essential. Bio-logging, such as Internet of cats, may generate more data than people in some areas where people like pets. How do these market needs impact the semiconductor device development? This shows our corporate technology vision. I have shown this before several times. The arrow in the middle represent continuation of Moore's Law. The arrow indicating main device evolution is very healthy. The green arrow indicates customization. While the purple arrow represents hyper-mass. In other words, the purple represents the needs of productivity enhancement or continuation of legacy nodes. The blue in the middle represents device scaling, 3D device structure and new material development. The green represents SDTCO, namely System Device Technology Optimization and new architecture. The system integration supporting device hybridization is part of this green arrow. Next, I will present more about the system integration. For system integration, there are 4 different categories. From the left, logic, memory, back end of line and other options such as bonding, I'll go one by one. First, logic. You can see 2D shrink as an extension of device scaling, new structure and DTCO to co-optimize device design and process technology. This shows memory. Here again, 2D shrink, more stacking for storage enhancement and 3D DRAM to break through the planar device shrink The third one, this is back end-of-line interconnect in process. To reduce data transfer delay, a new technology to embed memory and accelerator on chip instead of off chip is in progress. As many of next-generation memories can be embedded to interconnect structure, technologies to various memory structures to back end of line is being developed now. NPU or neural processing unit is developed to make device have multiple functions. In addition to the conventional SoC with CPU and GPU embedded, we can also see SoC with NPU dedicated to machine learning embedded. Number four, this shows heterogeneous integration, which is driven by evolution of bonders. I'll talk about it later on in my presentation. We must not forget SDGs, Sustainable Development Goals, initiated by the United Nations. Tokyo Electron is working mainly on 7 items. Our contribution is not limited to our own premises or products. This is the information we borrow from IMEC, a Belgium consortia and our development partner. On the left, the vertical axis shows the normalized environmental KPI, while the horizontal axis shows logic technology node. Energy, cost and water consumption and the logic production are plotted here. Leading-edge logic features the lowest environmental impacts. The environmental impact per device, when it's produced by using leading-edge technology, is lowest. And our process tools are essential for the production of leading-edge devices. I'll talk about this issue later in GAA. Now I will talk about details of development of major devices. So direction of the development of semiconductor devices, you can see important message under each device. The logic, the scaling with its structure change for cost reduction per transistor, lower power and faster device. NAND, higher stacking to reduce cost per bit. DRAM, scaling and new structure will enable reduction of cost per bit, lower power and faster device. And CIS, CMOS image sensor, increase of pigments by scaling, faster speed, high image quality driven by new structure and materials. Now let me talk about trend and business opportunities of logic device. On the right, you can see smartphone CPU evolution from 2014 to 2020. Over the past 5 generations, the number of transistors has been increased 6x using the same die size. And the number of cores has been tripled. And now you can see brand-new 16 NPUs as well. Memory cache size has been increased by about 6x due to evolution of structure, material and patterning technologies so integration and functioning improved drastically. Similarly, GPU performance has dramatically improved at the same time. There was another option to reduce number of transistors to reduce ship area. But in the case of HPC, priority was placed on improvement of PPAC performance. Scaling is essential to increase the level of integration. The key enabler is the patterning using EUV lithography and gap fill technology. For the final patterns, etching technologies with high selectivity suitable for various materials and dry technology to prevent pattern clubs. So these are very important technologies. What is essential to realize DTCO is various etching technologies with high selectivity and dielectric film and metallic film deposition technologies. This shows the logic road map from N7 node to N0.7 from left to right, showing major device parameters. When PP, poly pitch, times MP, metal pitch, are compared, integration will increase by a factor of 5.7. If DTCO cell height is included, integration per unit volume will be 23x. To increase integration that much, we need to develop GAA, the gate all around the new device structure. The GAA is also called Nanosheet. The vertical fin channel is placed horizontally to be made in a state of sheet to increase the number of stacking layers to meet performance specifications. A major characteristics is that fin width, one of the critical dimensions determined by patterning in the case of fin device, will be replaced by sheet thickness determined by silicon epitaxial growth. A large number of our technologies are used for formation of GAA, the core of the device. I'll talk about it later on. The major modules for the GAA formation are shown on the right-hand side, starting with mold-stack and etch, next formation of inner spacer followed by Nanosheet release, and after that, we'll see the replacement gate process. This is what we borrowed from IBM research in New York State, one of our development partners. The cross-section of 2-nanometer gate all around technology, you can see very good nanometer profile. This GAA requires advanced process technologies to make. The GAA device fabrication process is divided into 4 process modules. Number one, from the left to right, the first one is mold stack and etch. STI, shallow trench installation and silicon/silicon germanium stacking layer are extensionally grown. The second is Inner space module. This includes recess processing to control device characteristics and space formation -- spacer formation. The third is Nanosheet release module, depending on device time, silicon or silicon germanium layer is removed. This requires high selectivity etching process. And the last one is replacement gate module to fabricate gate electrode. Here, film deposition and etching technologies play an important role. Here are actual examples, but because of time limitation, let me just skip this slide. This shows patterning technology used in EUV, which is also essential for GAA device. As you know, EUV lithography features high resolution due to its short wavelength. Compared with ArF, however, the number of EUV photons per dose is limited to 1/14 as EUV features lower photon absorption reaction rate than ArF. EUV allows stochastic noise generation, which makes pattern rougher. Our company succeeded to reduce the roughness by co-optimizing conditions of exposure and etching. What we need is global development sites. There are limited source or routes that we can get EUV-exposed wafers by collaborating with European, American consortia and our customers, Tokyo Electron is promoting advanced process technology document. This shows the deliverables of the collaboration. Could you follow the series of images from left to right. Originally, this nano pattern featured critical dimension of 14.7 and line etch roughness of 2.25. This area was reduced to half and line etch roughness has been also improved, 1.5-nanometer by using our technologies. In the previous slides, I presented next-generation GAA logic. Next, I'll talk about 2 generations ahead, stacking of GAA structure. This is CFET structure shown on the right, and bonding technology is a key. Bonders have been widely used for CMOS image sensors. For logic, it's used to fabricate backside PDN. Today, unfortunately, because of the time limitation, I cannot give you any details. If you are interested in, please let us know to our 3DI Group. Now I take so much time for logic. I'd like to talk of memory and CMOS image sensor. As shown here, DRAM is full of high aspect ratio structures. Degree of freedom on the X-Y axis is very much limited. Pitch scaling is very difficult. Therefore, common strength and scaling are very difficult. However, there have been evolutions over the past 6 years from 2014 to 2020, data rate has been tripled and capacity has been raised by about 5x. Packaging technology with logic has evolved as well. Combining with GPU, DRAM can be dramatically increased the amount of data that GPU can process at the time by using silicon interposer technology. As you can see from this road map of DRAM, DRAM changes milder compared with logic. Recently, 3D DRAM development has been getting active recently. It's too early to present the details, but previously capacitor structure was vertical. The capacitor is placed now horizontally to be stacked. So that's how it's changed. As you can see here, we are developing processes required for formation of stack capacitor, cell transistor and word line and bit line. I'm getting close to the end of my presentation. NAND integration can be enhanced by increasing the number of stacking layers. Device footprint can be reduced by putting logic cell under memory array. Thickness using monolithic and bonding tool have been established. This shows the NAND technology road map. From left to right, year-by-year, the number of layers per stack keeps increasing, the number of tiers also show a mild increase. Materials for word line are expected to change in the future. Challenges for 3D NAND technology includes etching to cope with increasing number of stacking layers, film deposition essential for device formation, cleaning without patent collapse and bonding technology again here. Finally, I will briefly touch up on the CMOS image sensor. Just like other devices, device hybridization is proceeding for image sensor. The sensor and logic are combined, and AI processing is also added, and you can see increasing applications. This shows challenges and solutions for CIS technology. The first one is hybridization. Hybridization is supported by bonding technology to support hybrid product of logic circuit and CIS. Silicon trench etching for device isolation and film deposition and etching for global shutter rare also very important. I'd like to summarize my presentation. The semiconductor manufacturer processing is getting diversified and complex, which raises at value of SPE. This shows an update of WFE investment per monthly wafer stats of 100,000 that I presented 2 years ago. Though there are some cases investment drops from 2 years ago, this is a result of improvement of the tool performance and productivity. This leads to the development technology in the industry, including customers. This is my summary slide. The market needs are getting more and more complex. And in order to address those needs, including the multi-functionality, the device evolution is accelerated. In the multifunction of functionality, of course, some of them can be addressed by existing process, but further technology innovation is essential. So as Ms. Segawa said earlier, environment, SDGs need to be very important when we develop new technologies. This is what I want to emphasize. And when we develop the leading etch devices, actually that has a lot to do with SDGs. That's one of the messages I want to convey today. Our company is implementing the process development on a worldwide basis, and we are working on the global collaboration inside and outside the company. So the following 3 presentations given my business unit, will give you more detailed examples. Thank you very much for your kind attention.

Now it's a time for us to start the second half of the presentations. Mr. Akiyama, General Manager of CTSPS BU will present challenges and solution for advanced EUV resist process technology.

I am Akiyama, General Manager of CTSPS Business Unit. The title of my presentation today is challenges and solution advanced EUV resist process technology. I'll talk about process technology using leading-edge coater and developer. This slide shows the features of clean track LITHIUS Pro Z EUV, our coater/developer for EUV lithography. In these days, as you know, there have been growing demand from IC manufacturers for final resist patterning technology. EUV lithography is a solution for this demand, and LITHIUS Pro Z EUV is essential to implement the EUV lithography. The primary strength of LITHIUS Pro Z EUV are high reliability, high productivity and high versatility. As an in-line process tool, LITHIUS' Pro Z EUV maintains 100% share. We have shipped more than 100 systems so far. High reliability and productivity are realized by 2 factors: the first is LITHIUS Pro Z platform, featuring high-speed transportation and processing capability. Over the past 9 years, more than 1,600 LITHIUS Pro Z platform have been shipped for exposure system using various light sources. The second factor is that we have developed and installed EUV-specific functions to this system. I will explain the details of high versatility to address next-generation EUV lithography in the next 2 slides. This slide shows the logic technology road map and corresponding advanced lithography technologies. As of 2021, the EUV lithography has already been used in high-volume manufacturing lines. Scaling of minimum metal pattern pitch is going on. In the 5-nanometer node, about 28-nanometer pitch is used, which requires EUV multi-patterning. Final resist patterning is essential to realize further device scaling. Metal oxide resist, a new high resolution resist is expected to be introduced from the 3-nanometer node. An innovative high NA EUV lithography is to be introduced from the device node of 1.4 nanometer. Tokyo Electron is promoting R&D of our coater/developer to enhance its versatility to address new EUV lithography technologies, including metal oxide resist and high-NA EUV. This figure shows the proportion of layers using chemically amplified resist and metal oxide resist in each device node. For logic device, it is expected that the proportion of metal oxide resist featuring higher resolution will gradually increase along with the device scaling. For the time being, however, we think the proportion of chemically amplified resist remains high. The dry resist system of the competitor only addresses metal containing resist. By contrast, our coater/developer is designed to address all EUV resist process, including chemical, the amplified resist, which accounts for the majority of the EUV lithography. High-NA lithography is expected to grow in number. We are currently developing technologies. There are still various challenges in establishing the next-generation EUV lithography process. The first challenge is trade-off of RLS namely resolution, line edge, roughness and sensitivity. The second is patterning defects, which become increasingly challenging along with further device scaling. The third is a challenge for high-volume manufacturing, the necessary resist film thickness. When resist film thickness is reduced for better lithography performance, thin resist film will be damaged by etching to close defects. When resist film thickness is increased, however, resist pattern will collapse, and resist remains at the bottom of hole after development process. In an attempt to overcome these technological challenges, we are working on total optimization of the patterning technology by combining the measures for the coater/developer technology and etching technology. Today, I would like to present some examples of those engineering efforts. Firstly, I will talk about the measures taken for chemically amplified resist, which has been used for a long time. In particular, today, I will present how we address resist pattern collapse and increase process margin through the optimization of patterning processes, including etching. This shows the technology to prevent resist patent collapse, one example of chemically amplified resist optimization. Along with pattern size scaling, resist pattern collapse become a critical problem in the wet development process. As shown in the upper images, 14-nanometer resist pattern with high aspect ratio collapse after conventional post-development rinsing process. The lower image show the patterns treated with newly developed post development rinsing process, as you can see, even at 11.8-nanometer patterns, which are much finer than the target 40-nanometer resist pattern do not collapse. By using the new post-development rinsing process jointly developed with material manufacturer, we have succeeded in preventing the pattern collapse problem and increase in process latitude, process margin suitable for high-volume manufacturing. Next, I will talk about formation of fine holes realized by optimizing lithography and etching process. As I said before, residual resist at the bottom hole after development process is one of the challenges. If the residue can be removed at etching process, the device yield will be enhanced. As a result of etching process optimization, 18-nanometer holes with 36-nanometer pitch of accessories transferred without any defects such as resist residue or kissing of 2 neighboring holes. The hole of 36-nanometer pitch will be used in the device node of 1.4-nanometer. Another example is shown in the figure on the right. In the lithography process, 23-nanometer holes are fabricated with pitch of 46 nanometer. This hole size was reduced to 13-nanometer through the optimized etching process. This technology to reduce hole size will be presented by ES BU later. We believe it is our prominent strength to realize this kind of optimization promptly because we have not only a detection technology, but also coater/developer technology connected with the advanced exposure system. So far, I presented several examples of process optimization for chemically amplified resist, which has been used in high-volume manufacturing line for years. Next, I will talk about our initiatives for metal-oxide resist or MOR. Today, I will present improvement of EUV exposure sensitivity, roughness reduction, countermeasures for defects and resist pattern collapse. This slide shows the demonstrated performance of our newly developed post-exposure bake oven. By applying optimum baking conditions, exposure and sensitivity has been improved by about 25% without negative impacts on resist patterns. The exposure sensitivity enhancement will lead to higher throughput of EUV lithography system, drastic COO reduction is expected. The new oven will also improve the within wafers CD uniformity of resist patterns to 0.2 nanometer. For the metal contamination in the baking module, which is a specific concern of metal containing resist, the new oven means the target for high-volume manufacturing line. The new oven is suitable for the MOR oxide baking process. This shows the newly developed wet development technology. The conventional wet development process closes the resist pattern collapse problem, when it is used for final pillar patterns with 36-nanometer pitch for the future nodes of DRAM devices. The newly developed wet development technology is able to suppress the resist pattern collapse. This technology also improves exposure sensitivity by 25% without deteriorating uniformity of resist pattern sites. This technology is expected to considerably reduce our customers' cost of ownership of EUV lithography by increasing EUV lithography system throughput through improved exposure sensitivity. We are also working on module solution for metal oxide resist incorporating etching technology. By optimizing our etching technology, we have improved the uniformity of post-etching pattern with us to 1.8 nanometer or less, which is essential to raise device reliability. For a bridge defects breaking interconnects, the defect density has been reduced below the initial target of 0.1 defects per 1 square centimeter. Through this improvement, even in the case of verifying interconnect of 15-nanometer, yield of almost 100% has been achieved. Our coater/developer technology has been highly optimized for metal oxide resist. We are on track in preparing for the introduction to high-volume manufacturing line. Now I'd like to change the topic from technology to cost. Roughly speaking, there are 2 types of metal-containing resist process being developed for high resolution. One is wet resist process of metal oxide resist that TEL is now developing. The other is dry resist process, in which resist film is developed by film deposition system and then dry developing -- development is performed by etching system. The latter is being developed by our competitor. In the dry resist process using CVD film deposition and dry development, it is essential to remove metal contamination from etch and backside of the wafers, which results in more process steps and higher manufacturing costs. By contrast, the wet resist process, which TEL is developing does not need any additional process to remove metal contamination. It also feature shorter turnaround time. Therefore, cost of ownership of wet resist process is expected to be about 1/3 of that of dry resist process. In addition to the benefit of cost of ownership and operating cost, the wet resist process is also found advantageous in terms of process performance, for example, it raises sensitivity to reduce EUV exposure time. It's easy for customers to adopt it. The final topic of my presentation is our activities for high-NA EUV to further enhance resolution. In June 2021, TEL announced that we will deliver our in-line coater/developer for high-NA EUV lithography system, which will be installed in the imec ASML joint high-NA EUV research laboratory in 2023. Leveraging this research environment, we will collaborate with the partners to establish fine patterning technology for high NA EUV lithography ahead of others. We are working on optimization of patent scaling solution to prepare for the high-NA EUV lithography. This shows fine metal oxide resist pattern processed with the conventional EUV lithography system. The fine patterns of 12-millimeter half pitch are fabricated by combining the wet resist process and our etching technology. It's demonstrated that wet development process realizes 12-nanometer half-pitch patterns with line edge roughness and line with the roughness of 2-nanometer or less without closing any patent collapse. This demonstrates that our new systems are promising for further pattern scaling in the future. We are planning to identify and overcome challenges together with our partners. This is a summary of my presentation. To address pattern scaling by using EUV chemically amplified resist, we have developed a new technology by leveraging synergy obtained through a combination of the lithography technology and etching technology. We have developed a new technology for metal oxide resist to be used in high-volume manufacturing with high performance and low cost. The same system can be used both for chemically amplified resist and metal oxide resist, which our customers will find convenient. To address high-NA EUV lithography, we collaborate with the partners to provide advanced coater/developer process solution to be used in high-volume manufacturing of the future generation devices. This concludes the CTSPS business unit presentation on technologies for future EUV lithography. Thank you very much for your kind attention.

Next, Mr. Wakui, General Manager of ES will present the latest technological challenges and TEL's activities in etch.

I am Wakui. I will present the etching system business. First of all, I will talk about overall strategy for etching systems. We will continue making an effort to win PORs for hard process, high aspect ratio contact process, patterning process, interconnect and contact process and gas chemical etching process. For MLC and slit of NAND and capacitor of DRAM, we will maintain differentiation in processing performance and productivity. For Channel 4 of NAND, we will introduce new equipment. For patterning, we will promote differentiation through combined etching and film deposition etching collaboration. For the interconnect and contact process, our expertise for logic, which is our strength, will be deployed to DRAM. For the gas chemical etching process, we'll expand its applications to new market segment. Let me start with memory business opportunity. We will address business opportunities for dry etching, which is increasingly adopted both in NAND and DRAM. For NAND, as shown in the slide, further multilayer stacking is going on by dividing layers into multiple tiers in processing. Aspect ratio is reaching 70:1. In order to win PORs in the hot process, which increases along with the stacking, we will enhance etching performance, address high aspect ratio and help our customers improve productivity to mitigate their costs. This shows higher stacking of memory devices. As shown on the left-hand side figure, 3D stacking up NAND keeps going. The number of layers is expected to increase further from the current 1 next generation and accordingly, NAND device will get higher and higher. For DRAM as well, when the current plan of structure is replaced by the 3D dimensional -- 3-dimensional structure, high-aspect ratio etching process is expected to increase, just like the case of 3D NAND. Ongoing 3D stacking will help the etching market keep growing. This slide shows the challenges of the etching process we face, along with the trend of higher aspect ratio. From the left, you can see the etch profile of capacitor of DRAM, channel hole, slit and MLC of NAND. As aspect ratio increases, along with multilayer stacking, there will be more demanding challenges such as formation of deep vertical profile, control of dimensional variation and selectivity against underlying layer. As shown in the right figure, a problem of depth loading, which suppresses etch rate at deeper area, has a negative impact on etch performance and productivity. I will talk about our efforts to address these challenges. The figure on the right show how ions enter deep hole trench -- deep hole and trench. By making an ion instant angle closer to plumb down before, we have enabled ions to reach deeper areas, which realizes accurate processing control and improved productivity. By leveraging this technology, we will win more PORs in the critical processes for which processing of high aspect ratio profile is essential. Next, I will talk about our efforts to enhance productivity. As I presented in the last IR Day, we introduced new platform, Episode UL into the market. It features flexibility to select the number of chambers to be mounted. It saves space by reducing footprint. And it realized smart tool through an autonomous process control, including automatic part replacement and big data analysis. Episode ULs were delivered to multiple customers this year, helping the customers enhance their productivity. Next, I will present logic business opportunities. In addition to multilayer interconnect process, which is our strength, along with further device scaling, device structure will be varied as shown on the right and also EUV lithography will be introduced. To address these trends, we will provide appropriate patterning solutions. Today, I will present how we address EUV lithography and gate all around Nanosheet. This slide shows etching in the EUV lithography. Introduction of EUV lithography drives device scaling. But as shown on the right, the EUV lithography process induces defects and poor local critical dimension uniformity. Since EUV resist film is 2 things for dry etching and features poor plasma resistance, there are problems such as poor hard mask performance and pattern collapse in patterning. To tackle with these challenges, we think it's important to complement the patterning process with etching technology. We will merge the film deposition technology and etching technology to overcome the challenges of the EUV lithography. The defects on poor local critical dimension uniformity caused by EUV lithography are traced by repeating the film deposition and etching process as shown on the top. Specifically, uniformity of hole size has improved in this case. Next selectivity in etching process has improved by depositing protection film on the resist and selectively remove it as shown on the bottom. We also collaborate with imec and ASML, planning to provide patterning solutions for the future high-NA lithography. This shows how we address the transition of transistor structure from fin structure to Nanosheet. As one of the efforts to address the Nanosheet fabrication process, we are starting the possibility to use chemical dry etching system to multiple applications. In these processes, it's necessary to etch silicon germanium, the black portion in the upper figure and leave uniform and smooth silicon film untouched. We plan to the chemical dry etching, which can isotopically etch silicon germanium with high selectivity against silicon and suppress surface roughness, so that we can win PORs. Finally, I will present initiatives to enhance our development and production capability in the etching business. Last month, construction of Miyagi Technology Innovation Center that was completed in Tokyo Electron Miyagi, as we announced. This center aims at creating innovative technologies and drastically enhance productivity. One of the options to achieve this aim, is collaboration with our partners. This shows the roles of Miyagi Technology Innovation Center. The center is expected to play the following 3 roles to promote innovative manufacturing technology in our entire plants. Firstly, FIL, or future tech incubation lab is founded to develop technologies to enhance performance of process to component, reduce lead time and mitigate environmental footprint as well as to develop new materials. The second role is innovation of manufacturing technology. We built PIL or production innovation lab to study DX technologies to sense and analyze field data and explore possibility to use robot technology in assembly. To prepare for increasing demand and raise efficiency, we will develop new production systems and enhance automation of manufacturing lines. The third role is TC or training center to provide highest standard training. By leveraging virtual reality and mixed reality, we will organize remote training as well. This is how we can enhance our strength. In this way, we can enhance the strength of the field, not only our company, but also our customers. Here's the summary. Driven by 3D NAND patterning, high level of investment is expected for etching system. Adapting to changes of device and addressing customer needs, we will continue with technology innovation for both memory and logic customers. We will enhance our development capability and production capability to be prepared for the further market growth in the future. Thank you very much for your kind attention. This concludes my presentation.

Next, Mr. Ishida, General Manager of TFF will present TEL's approaches for the next-generation deposition technology.

I am Ishida of TFF Business Unit. I Present our approach to next-generation film deposition technology needs in thin film formation business unit. In order to realize next-generation devices with high performance, various changes of device structure are being studied. For logic device, Nanosheet is one of the promising options and all logic device manufacturers are expected to adopt it. On the right, you can see the structure of Nanosheet. For Nanosheet, multiple very thin dielectric firms are essential. They must be resistant to chemicals and feature extremely low parasitic capacitance. Their thickness must be uniform in every direction. We must develop a directed film to meet all these requirements. TFF business unit is studying possibility to use a batch process. Why batch? We propose batch process taking account of all the requirements, the clear advantage of batch process is its cost advantage and stable film thickness and quality. To control characteristics of the dielectric film, we are also evaluating possibility to use boron. As we currently think thermal treatment can be used, we are planning to perform the process in batch furnace. Toward the future, we will find the way to expand its applications. In order to expand process options, such as film deposition, etching and inhibitor of absorption and in parallel to maintain good film quality at low temperature region, we are evaluating multi-processes by using single wafer processing. As low may become necessary in the future, we are evaluating new materials in batch furnace, which we didn't conduct before. We are prepared to cope with future change of the needs and to address more demanding needs. We will compare the batch furnace and single processing system in terms of technological needs and cost, based on which we will provide most appropriate system to the customers. It is our strength that we can start this evaluation project together with the customer at earlier stage and discuss the direction of the new system. Next, I will talk about multilayer stacking, which is the technology inflection point in 3D NAND. As stacked oxide and nitrate film need to be etched multiple times, it's difficult to obtain perfectly vertical profile in trenches and holes to their bottom. As a result, gapfill gets varied. Atomic layer deposition features an ideal surface reaction. So NT333, our semi-batch system using ALD technology has been widely used for 3D NAND. In the case of multilayer stacking structure, however, because of its bottleneck profile and bowing it's very difficult to deposit firm without any voids in holes and trenches. To overcome this problem, we have developed a new technique to locally reduce film deposition rate. Specifically, film deposition rate is reduced only at the top of the profile to keep its top open, and then ALD film is deposited. This method can be used in single wafer processing system, but we decided to use semi-batch system because the semi-batch system can increase productivity, and it has been used in high-volume manufacturing line. Next, I will talk about new initiative of silicon film deposition using batch furnace. Along with logic device scaling at the stage just before shift to Nanosheet structure, dimensions of fin structure are getting extremely small. Due to the minute dimensions, we encountered the problem of fin structure erosion. And it becomes necessary to introduce a new process to tackle with this problem. Intel, we introduced extensional growth of sacrificial film. As fin is located at the substrate, the sacrificial film need to feature comparable quality to the substrate. To realize good quality film, we have integrated precleaning process into batch CVD silicon system, which is widely recognized in the market. As we successfully realized the new process by using cost-effective batch fairness, the new process has been adopted in our customers' high-volume manufacturing lines. The new initiative of silicon film deposition that I've described in the previous slide might potentially have other applications. For example, silicon/silicon germanium stacking film used for Nanosheet, boron doped silicon film used a stock for filming backside PDN and silicon/silicon germanium stacking film used for 3D DRAM. These potential applications, however, are extremely demanding in terms of technology because these films are required to feature outstanding quality. They need to be stacked and they need to be thick. Having said that, if these films can be deposited in batch furnace, such process will have very high cost advantage. As the batch process was precleaned and combined is proven in high-volume manufacturing line we keep working on development to expand these applications. What I will present next is not film deposition, but film quality improvement by means of thermal treatment. High-quality film must be deposited to enhance electric characteristics and reliability. It is also necessary to fix damages induced by film deposition process. To overcome these challenges, we are studying various treatment. Today, I will talk about D2 deuterium annealing. This process has been developed for 3D NAND. Through collaboration with the customers, TEL has developed various processes to improve device performance and also develop hardware optimal for process conditions. Since this process performed in batch furnace, it features high productivity and can provide cost-effective means to improve device performance. This is another example of film quality improvement. In the previous case, as 3D NAND features high thermal resistance, batch furnaces is adopted. In the case of logic device, however, many processes except for some front end of line process are subject to temperature restriction. There is an increasing need to deposit dielectric film at extremely low temperature, an innovative approach to use plasma treatment to modify deposit film is being actively evaluated. Our product, SPAi is one of the promising technologies as it can generate high-density radicals at low temperatures. And this technology is now being evaluated. Potential applications of SPAi includes modification of interlayer dielectric film in Nanosheet and dielectric film for substructive metal interconnect. Depending on technological requirements, we proposed batch, semi-batch system or single wafer processing system and evaluated. Here's another technique for film improvement. This uses single wafer processing system. By combining UV lamp and remote plasma, a very thin dielectric film can be deposited. Reaction of reactive spaces activated by UV lamp is very slow. And therefore, it features high controllability suitable for depositing thin high-quality films. This technique has been adopted in high-volume manufacturing line of some devices and by some customers. To address further scaling and oxidation of interface of thin film, this technique might be applied to logic Nanosheet and 3D NAND as well. This is a module solution to be realized by using TEL's corporate assets. It is not similar effort of TFF. We intend to provide the solution to improve post-etch local CD uniformity by using TFF's XM, a PVD system developed for MRAM. This hard mask film deposited in our PVD process features higher selectivity than currently adopted hard mask film. The film can be formed at temperatures, which CVD cannot handle and features outstanding selectivity. We need to evaluate etching performance using this new hard mask. It's also necessary to evaluate removal of film at level in order to check whether the new hard mask material causes any problems for the integration. We are currently taking cross-BU approach in these evaluations. We also have started sharing evaluation results with the customers. Here's a summary. In the next-generation devices, demand for film deposition technology will be increasingly diversified. Though it is extremely difficult to develop new technologies, we are always required to reduce costs. TEL will pursue an optimum solution in terms of both performance and cost out of many options. We will provide technology solutions by combining the film deposition technology with pretreatment etching and modification. We will expand cross-BU and cross-product collaboration as we introduced at the final portion of my presentation. We will provide an appropriate solution at the appropriate timing by sharing information with the customers in the evaluation process. Our customers agree and support this strategy of TFF business unit. New initiatives of technology development are in progress in many fields. We will develop leading-edge technologies and corresponding process tools to raise the customers' trust and expectations and expand our own business. This concludes my presentation. Thank you very much for your kind attention.

Now we'll have a question-and-answer session till 5:30. We will receive questions both in Japanese and English. But as our attendees on the Japanese channel, please allow us to restrict verbally asked questions to only in Japanese. When you ask questions in Japanese, please hit raise hand button on Webex. For details, you are kindly requested to refer to the instructions attached to the e-mail. I will call name of the person who ask a question one by one. Please check the chatbox on Webex as our Secretariat will inform you in advance that you will be the next person to ask a question. Our Secretary will unmute you when you ask question. If you ask a question in English, please use the chatbox to send the question in text, together with your name and affiliation to Secretariat. We will refrain from answering your question if no name or affiliation is given. On the Japanese channel, I will read out the question translated into Japanese, and our attendees will give an answer in Japanese. While on the English channel, it will be simultaneously translated into English on a real-time basis. For questions verbally asked in Japanese, please allow us to limit 1 question with 1 follow-up question. For English questions sent in text, I'm very sorry, but we will receive 1 question without a follow-up question -- as a first question, sorry. So Mr. Yoshida of CLSA Securities, Japan. Mr. Yoshida, please.

I am Yoshida of CLSA Securities Japan. The first question is about Slide 101, WFE investment per 100,000 wafer starts per month. For logic, in the past, you presented the value for 5-nanometer, $20 billion. However, this time, for 2-nanometer, $21 billion. Because of the efforts of the 2 vendors, the focus has been revised downward for 5-nanometer to 3-nanometer and 2-nanometer, when look at the investment, the increase is rather mild. So lithography intensity increases, some manufacturers has said that. What costs have been -- will be reduced according to your prediction? In the past, about 15% to 20% increase is expected for investment from one generation to another. I want to understand the reason for memory, NAND, and 3D DRAM. When they start, what happens to WFE investment and breakdown by process too? I want to hear about some future of the memory. Mr. -- Dr. Sekiguchi, please.

It's a difficult question. So the cost increase is driven by exposure and patterning. I think patterning and exposure lithography accounts for the huge amount of the -- very big amount of costs. But the 3-nanometer and beyond, in order to reduce cost, there are various method, combination of various tools to produce the devices that will become more important in the future. For patterning technology, as you heard from the business unit, we are now focusing the combination of different devices, at the same time, the production technology. So the productivity is enhanced where you can reduce cost as well. So there is one addition from IR. So this is the prediction based on our process flow. So this is capital intensity based on our estimations. So customers, 3-nanometer or 2-nanometer node, are way in future. So they are not fixed one. This is just the estimation prepared by TEL, our company.

So for memory, in that sense, you haven't produced your own estimated flow yet? Is that correct? 3D DRAM, for example?

For 3D DRAM, Dr. Sekiguchi, please?

For 3D DRAM, actually, it's way ahead. So things are not yet fixed. That's what I said in my presentation. On Page 92, key modules, you can see the stack formation, cell transistor formation, capacitor formation, all those area, there is room for technology innovation. So as of today, we can just give this number based on current assumptions.

One follow-up question. So etching technology, Slide 130 -- Page 130, gate all around nanosheet, selective etching. Gas chemical etching advantage is shown over here. But for the wet etching, I think there is another option using the wet etching. What is the difference in cost between the two? And which technology will be more promising at this stage?

So , please?

Again, a difficult question again. So technologically speaking, so etching selectivity and high uniformity, we need to pursue those 2 requirements. So that's gas chemical etching. I think that gas chemical etching has some advantage because of those 2 reasons. But your question is about whether wet etching or gas chemical etching, that is very difficult to answer, but we believe there are some processes which only gas chemical etch can handle.

Thank you very much, Mr. Yoshida, for your question. Next question is from Mr. Wadaki from Nomura Securities.

I learned a lot from today's session. I have a question for etching system to Dr. Sekiguchi and Mr. [ Wakui ]. So now we are talking about etch step -- number of steps because what happens for high-NA with SPIE, I saw some information for 3-nanometer or 2-nanometer M2 for EUV with to be used. If that's the case, maybe we should use etching system 10x, then you can sell a lot of etches. And after that, all those things will be replaced by high-NA. That's the road map. Then all of certain etch order will be decreased. But in the case of 3-nanometer or 3-nanometer high-NA for logic etching, how do you view the number of etching processes in logic in 3-nanometer or 2-nanometer by using high-nano -- NA? For 2-nanometer, 3-nanometer, things are still uncertain in the customer side. But -- so I think they gradually come up with some integration flow.

So in your question, you pointed out the patterning, it's getting more complicated in the beginning. So number of etching will increase. That is the starting point. However, ultimately, customer will adapt. In order to reduce device cost, so we need to provide the most simplified process. Integration flow should be designed by using customers' wisdom. And ultimately, maybe a number of the processes -- a bit difficult for us to give you the number of processes, but we don't see the explosive growth of the etching process when we see the next generation up to until M3 or M2. So self-aligned block, I think that require 10 etching process. I think this estimation should be not so wrong. For patterning, maybe Dr. Sekiguchi, please?

Mr. Wadaki, could you repeat your question once again, please, for self-aligned?

I said self-aligned block 2. One block requires full etching processes. And when you carry out 2 blocks that require 4 etch processes, in addition, you need to carry in advance. So 10 etching process might be required.

I think your estimation is not so wrong. So for 3D DRAM, when 3DRAM will come and different from etch, bitline etching the word line is to be etched and capacitors to be etched. So number of etch process will be increased, and I think there will be good news for the etching business. What do you view Mr. Sekiguchi and Mr. [ Wakui ] for timing, 90 -- Page 91 -- Slide 91, HVM for 3D DRAM, 2026 or '27. That's estimation. So that's when the 3D DRAM might appear. So number of etching processes, it goes vertically in the past, but it go now laterally. So each required film deposition and etching for each layer, so number of process. Of course, it depends on the number of capacitor, but I'm sure that the [ develop ] process increases. That's true.

Thank you very much. Thank you very much for your answers. Thank you very much for your question, Mr. Wadaki. Next question is from Mr. Yamamoto from Mizuho Securities. Mr. Yamamoto, please. Can you hear me?

Yes. I'm sorry. I am Yamamoto of Mizuho Securities. For ESG and to development, my question is rather vague, I'm sorry for that. So CO2 emission Scope -- when you think about Scope 3 for CO2 emission, so direction of the tool development, what change or not in order to improve the CO2 emission in Scope 3? Do you have any idea to include something new in the development process? Or the direction -- conventional direction remain unchanged, and as a result, the CO2 emissions will be reducing? So some [ competitors at ] green, but they try to enhance or appeal their process performance or -- to performance. Do you think direction of development will change to reduce CO2 emission in Scope 3?

, please?

I am ]. Let me answer to your question. At present, the productivity enhancement, that direction -- conventional direction is to be pursued. And at the same time, we can enhance green. And I think we can pursue those 2 targets at the same time. And as I said earlier in my presentation, the regulations are getting more and more stringent and customers' environment. There are different customer requirement depending on their environment. So we need to focus on the situation to decide but to do -- where we need to focus in our development.

So in the past, do you have the conventional reduction of the development? And there is no big change in your direction of development?

For mainstream development, yes, that's correct.

So users -- so green -- for green, when they select the tool, do they have any -- are there any users who focus on green? Or even if for the critical ones, they cannot prioritize green, but for other area, some leases just focused on green when they select the tools. Do you have any information getting from the customers?

I am Kawai. Right. So there are 3 stages. So tool performance in the ESG CO2 emission reduction for semiconductor device performance, tool performance and the site activities, we are focusing on those 3 areas for CO2 emission. So customers, when -- from the viewpoint of the customers, for example, low-power consumption device and to merge device -- 2 devices into 1, that thing is required. But the green performance, it should be part of the tool performance. That's how we understand and how like you to understand situation. In other words, so the per-unit area -- so when a green room is operating, the device output per unit area green room, that has a lot to do with the productivity of the manufacturing line. That should be one of the keys in the tool selection done by customers. So within the limited space, how much devices they can produce. That's very big factor in the customers' selection process. At the same time, in our company, concurrent development is now going on, so development and production. So we are always thinking about the mass production when we design the process tools because in the future, so 3-nanometer, 2-nanometer, 3D NAND, 200 or 300 layers era comes then [ tool-to-tool ] matching and chamber-to-chamber matching. So that requirement will be getting more and more severe. So the matching should be considered when we design a new tool. So tool uptime should increase, yield is enhanced. These things also has a lot to do with the green or CO2 emission reduction. And for the customer to establish the fab with lower CO2 emissions, that will become more and more important. So each customer has their own formula for green. So they have -- I think green's specification should be one of the criteria for selection of tool, and that is required. And also legal requirement for environment, we need to pay attention to the legal requirements for environment. Chemical recycling need to be considered as well, so when we make a proposal to the customer. At the same time, we need to enhance the alliance with our partners. So this is how I can answer to your question. And e-compass, we have established the new initiative, and that is one of the background why we're establishing compass.

Mr. Yamamoto, thank you very much for your question. One request from us, at present, the simultaneous translation is carried out. So could you speak a bit slower for the interpretation? So next question is Mr. Shimamoto of Okasan Securities.

I am Shimamoto of Okasan Securities. Can you hear me?

Yes, we can hear you.

So from me, so about the growth story, I heard your growth story now, so '30 -- [ 2020-'30 ]. For each device, you have the device road map. And for each process tool up to until 2030, what is your expectations for the growth? And could you show me some order of the coater/developer, dry etch, film deposition, cleaning, prober? So you have various products. So for those different -- could you just give me some clue about the growth story towards 2030?

Mr. Shimamoto, so it's the general road map -- so your question is about general road map. What would you like to know about specifics about the process [ tool ] specific road map?

Rather than specific, I want to understand general road map until 2030, logic, memory. You have presented the road map for logic and memory. So what is your expectations for growth? I want to know which tool has the high expectation for the growth? That's the gist of my question.

], please.

So I think the President, Mr. Kawai, will give you the answer on behalf of the company. But the number of processes, from the point of the number of processes increase the logic road map on Page 75. Could you refer to Page 75? So the Fin structure, front end of line, will be replaced by Nanosheet. In this area, film deposition and etching to -- so the CD, the critical dimensions, have been determined by dry etch plus dry-etch [ searches ]. So they were important. So Nanosheet structure is as Forksheet, so etching proportion growing. At the same time, film deposition proportion also increase. Also cleaning, the wet process increased as well in number. So I think all of them will be growing, not evenly, but each process increases. And defined patterning will become required. So that's the story for logic. As for DRAM, so the scaling -- device scaling will get slowed down. That's what I said. On Page 91 -- you can see the road map on Page 91. And device scaling, the patterning ArF emerging lithography and EUV lithography will be used more and more. So basic structure remained unchanged, and 2026 3D DRAM comes out. So that's when the changes occur. And after that, as I said, so film deposition and etching are expected to grow. For NAND, road map on Page 95, over here, what is increasing its number of tiers and the number of stacking -- number of layers for stacking. So when more and more layers are stacked, the capacity increase. That's what the current structure is. That remain unchanged. Thank you. Understand? So for each device, depending on the use, so the important process tools are different.

May I? I am Kawai. I would like to give some additional answer. As we said before, 2020, the semiconductor device market is about $400 billion. But 2030 -- yes, 2030, $1 trillion or more is expected for 2030. Semiconductor market grows above $1 trillion. So our customers' market, when you look at next decade, the market will be doubled. That's the current situation. So when I look at WFE, so WFE market also has the strong potential for growing. So in the future, now there are 4 products: coater/developer, etch, cleaning and film deposition. So in those 4 products, they are our core products, and we are focusing on those 4 area. Higher capacity, higher reliability, higher speed and lower power consumption, so these -- a lot to do is the partnering performance, and those 4 are expected to grow drastically. And this area -- for our company, they are the core business at this moment. And in our company -- so we have the broad portfolio, plasma technology and pressure control, thermal control, chemical technology and also bonding technology as well. So we have various technologies as well. So we are going to provide the technology that customer will need in the future by leveraging our strength. And the semiconductor market is expected to be doubled in size toward that kind of high-potential market. We are going to promote the technology innovation so that we can contribute to the semiconductor market. At the same time, we'd like to expand our business. That's my additional answer.

Mr. Shimamoto, thank you very much for your question. Next question is from Mr. Hirakawa from BofA Securities. Mr. Hirakawa, please?

I am Hirakawa of BofA Securities. I have a question for etching. 100 -- Page 125, 1-2-5, this time, the Ion vertical entry, so the Ion incident, get closer to 90 degrees. That's what you said in your presentation. So what sort of TEL proprietary technologies are employed? If possible, I want you to explain your technology and your competitive technology. And as a result, at present, current aspect ratio compared with your competitor, what is your status for the high aspect ratio? So this includes my follow-up question actually.

So [ Wakui Isamu ], please?

So for the incident angle of Ions are getting closer to 90 degree. That's what we are working on, as I said in my -- as for the direction, that's of Ions. We should reduce frequency and increase power and also the [ pulse ] technology. So out of those options, we try to come up with optimum solution. That is the uniqueness of our company. Our competitors -- the comparison with our competitor, so the information that we have, it's a bit difficult for me to answer to that question. So as far as our company is concerned, 3 technologies are to be combined in the optimal way. This is how we try to differentiate ourselves from our competition -- competitors.

So for technology, it might be difficult to compare your technology with your competitors, but current aspect ratio, could you just give us some comments on the aspect ratio, please?

In my presentation, I said 70:1. That's what I said. At present, current aspect ratio specification is 70:1, and we are developing technology to satisfy that specification. And we try to differentiate ourselves from the competitors' technologies to satisfy the aspect ratio of 70:1. I think in a future generation, aspect ratio gets much higher and higher. So we are working on the current specification for 70:1. And I cannot give you any more answers about the future -- technologies for future aspect ratio.

Mr. Hirakawa, thank you very much for your question. Next question is from Mr. Yasui of UBS Securities. Mr. Yasui, please?

I am Yasui from UBS Securities. My question is about the technology road map toward year 2030. For logic, DRAM and NAND, you presented the road maps toward 2030. As for plan B, for example, there is a game changer device for 2030, are there any possibility of changes as game changer from 2D to 3D NAND. Flat memory is putting forward, the device manufacturer, competition changed and etching demand increased. So 5 years to come or 10 years come. If this comes, the demand might change. Do you have such kind of potential game changer? That's my first question.

, please?

Okay? Actually, one after another I encountered a very difficult question. It is true that floating gate -- from floating gate to 3D NAND, when the change occur from floating NAND to 3D, the change was rather drastic. And customers didn't expect such high speed of change, rate of change. For 3D DRAM -- as for 3D DRAM as well, as for the possibility, yes, there is a possibility. We cannot say anything decisive and technology development. We need to refer to the future technology development. That's first thing. And second one is system integration. So that's what I said in the beginning of my presentation, system integration. So what we are very active is back end of line. So various memories are to be embedded. That's the development working -- we are working hard. For example, memory and logic embedded together. So that type of device hybridization. So we have that sort of activities. So device competitive edge increases in that way. So shift takes place and maybe in the future, hybrid device might increase. That is another possibility for the future.

And my follow-up question is for memory. So you talked about next-generation memory. There are many of next-generation memory. So I think that possibility is a bit behind. Do you think -- you don't think application not -- does not grow so much?

At present, the existing devices will continue to be evolved. That's how we view the future, DRAM continue, NAND also continue. However, for early , actually they are the application for embedded area, and we are working on development steadily. So it's a bit bad nodes a little bit, but nonvolatile memory and is also included.

Thank you very much, Mr. Yasui, for your question. Next question is from Mr. Nakanomyo of Jefferies Japan Limited.

I am Nakanomyo from Jefferies Japan. So Page 115, 1-1-5, the dry resist -- comparison with dry resist. On the bottom, I can see that the cost and operation benefits, at the same time, performance the -- compared with dry process/wet process is more advantageous. That's what you say in your slide. So when the device scaling moving on, are there any theological limits? Are there any potential for dry resist?

, please?

For dry resist, the performance potential or advantages not only for performance, I think on Page 115, what is more advantageous. But generally speaking -- so dry processing -- when you use dry processing, the patterns are resistant to the pattern collapse. That's what we said in the past. However, we are working on wet process development. And we are now working on challenges, and that's what I said in my presentation. The pattern collapse can be prevented. Even for the future scaling, we have -- we tried to develop such kind of technology. As I said in my presentation, there are some data as far as the data considered. As for the pattern collapse, the wet process performs as good as dry process to prevent pattern collapse. So against dry process, what we are concerned a lot is the pattern collapse when we developed with process.

So up to until when? Are there any limit, theoretical limit or something? So do you mean the wet process can prevent the collapse -- pattern collapse?

So in the case of wet process, the surface tension takes place. So surface tension -- the lateral force will cause the pattern collapse. However, if the surface tension is prevented by adding the development process. In the development process, we have additional chemicals, coating or in process. We have some technology incorporated to cancel -- offset the surface tension. So we are doing some collaboration with chemical manufacturer. I'm sorry. I cannot say any limit, but this is what we are working on to take actions against the pattern collapse by developing new technology.

My follow-up question is about on slide -- maybe a similar question to Yamamoto-san, the Slide 38. Total downstream CO2 emissions, I can see some figures. When I look at figures of CO2 emissions in downstream, so I think your products generate CO2 a lot in the usage. But those figures do not have so much big meaning. For example, depending on the amount of products to be shipped or the number of devices to be produced, when more devices are manufactured, the CO2 emission increases naturally. So what users are concerned is the CO2 emission per device or per consumption per device. My question is, so those figures reduced -- as for KPI, reducing those figures of CO2 emission does not have so much meaning. Well, how do you view this CO2 emission in downstream compared with the -- your competitors?

, please?

So quantitative comparison with competitors, I cannot give you any answer to that. When we sell more products, as you said in your question, the amount of CO2 emission increases naturally. And the customer fab, the CO2 emission increases when they produce more devices. But as I said earlier, the power consumption, water consumption and CF gas and chemical, if by reducing those consumption -- so when we converted to the CO2 emission, we can reduce converted equivalent. So as a whole industry, we can make some contribution to the reduction of the CO2 emission. At the same time, we can contribute to the mitigation of the global warming.

May I -- I am Sekiguchi. May I add some comments? On Page 67, you can see the environmental KPI. And on the left-hand side -- when you look at the left-hand side, there is a fake figure, you can see normalized KPI metric on the , and you can see technology node on that horizontal access. What is plotted over here is -- so performance changes from one node to another. The number of transistor element per transistor element, the performance takes place or area per transistor and energy to be consumed for production, how they are reduced and process cost and [ per water or the per ] water consumption. So when you look at this figure, per transistor, one unit transistor, environmental footprint impacts are expected to reduce. Of course, the number of transistor -- when the number of transistor to be produced increase, overall, environmental impact increase. But when you use the leading-edge node, you can reduce the CO2 or environmental impacts as a whole. That's the message that I wanted to convey by using this slide on Page 67. So this plot might be changed depending on each individual device. This is total cost. So this includes all the process costs. So of course, for each product -- we have the figures, of course, for each product and cost impact might be different depending on the type of the process.

I am Kawai. For ESG, CO2 emission reduction, for that -- for competitiveness edge of our company from the viewpoint of the competitiveness, so year 2030 CO2 emission reduction. So 30% reduction is our target toward year 2030 when our process tool is in operation. And also -- so in this area, in this industry, these figures or targets are the highest compared with other competitors. Among the goals announced by other competitors, this is the highest level of the goals. The importance, so semiconductor WFE, semiconductor wafer fabrication equipment, that has a lot to do with the competitive edge. So for each production, the productivity is enhanced. At the same time, when -- for patterning, other than our company, the number of processes than our process, for example, EUV lithography process. So when we propose some idea to contribute to EUV lithography, we want to come up with some solution in terms of environment to cost and production. So I would like to work on those areas as well. I'm sorry. This is my additional comment to you. So I'm afraid, I didn't answer to your question properly.

I'm sorry, my question was not so well organized.

No. No, thank you very much for your good question.

Thank you very much, Mr. Nakanomyo for your question. Next question is from Mr. Ishino of Tokyo -- Tokai Tokyo Research Center.

I am Ishino from Tokai Tokyo Research Center. My question is slightly different from technology. But generally speaking, 5-nanometer foundry/logic price, logic price is about $15,000; 3-nanometer, $25,000. So the chip manufacturers, the chip cost is about $50 to $80, about 60% increase in chip cost from the viewpoint of the IC manufacturers. So ultimately, the semiconductor supply tight and end user, the consumers, pay more through the cost transfer, about 60% increase will have the impact on the final retail price. So now in this, our -- today's presentation, 3-nanometer -- you talked about EUV lithography as well. At the same time, as you -- on Page 115, cost of wet process using metal oxide resist is 1/3 of cost of dry resist process. Then the 3-nanometer foundry cost increases, then high-NA lithography needs are getting -- putting forward or metal oxide resist from the initial estimation, the needs for metal oxide resist are appearing faster or sooner, and many other companies are emphasizing their effort on metal oxide resist. So there is some breakthrough in cost. So which product is more affected and 1/3 by -- are there any drastic reduction cost by introducing cost? And could you just explain that sort of cost trend, please?

Thank you very much for your question. , please?

So on Page 115, 1-1-5, this figure -- as for this figure, I would like to give you my detailed explanation on this figure on Page 115. So you said 3x. The major difference is, as you know, -- so the coater/developer at present is connected in line with EUV lithography system. Therefore, after resist is coated, the exposure and baking and development. For that process, they are connected in line. So all those 4 process steps are completed within the in-line system. Compared with that, when we use the dry process, the CVD tool used for the resist film deposition. And after the cleaning, process is necessary to clean the wafer. And after that, wafer comes into the exposure system. And after that, wafers are transported to another system for baking. And after that, the dry etch is conducted. And after that, cleaning need to be conducted. So as I said now, there are 5 or 6 more additional processes are necessary in the case of dry process. So those additional processes are major factors of the 3x difference of the cost between wet and dry. And another thing, you just asked me high-NA lithography. As I said in my presentation, imec, ASML, together with those 2 organizations, we are now evaluating technology in joint laboratory that will start from 2023. So when this technology will be used in the mass production, maybe from N1.4 or beyond, year 2025 or '26. So that is the fastest timing, and I don't think that will change. And metal oxide resist application, the metal 30-nanometer pitch and beyond, the metal oxide resist will be actively adopted by our customers. That is the general trend among our customers.

My follow-up question is -- so ASML IR Day, the other day, so high-NA 2025. These are 5 units to be shipped. But according to your presentation, yes, '26 and beyond. High-NA lithography is not to be used for the mass production or a large amount of metal oxide where this will be used beyond 2026. Is that correct understanding? And existing EUV lithography system is about JPY 20 billion. High-NA lithography is JPY 30 billion for one unit. So in such a case, your process -- also process tool price increased by 50%, just like the lithography system. So that will not contribute to the cost conservation or cost savings. Could you share your idea with us, please, on those 2 regard points?

Your first point, as for your first question, imec -- from imec -- imec announced some information, as I said earlier, 2023 EUV high-NA lithography system started operation. And they are going to develop technologies to install that to the high-volume production area for 3 years. And against that, ASML, the TEL and the chemical vendors are supporting that technology. So year 2026 is the target here. And so conventional EUV lithography innovation speed, I think that 3-year can, say, plan is rather aggressive plan. When it comes to price, from our company, we are not able to give you any comments on price. But one thing for the coater/developer, as far as coater/developer is concerned, as I said earlier, so wet process -- for this wet process, so the chemically amplified resist, metal oxide resist, those 2 can be processed in 1 system, 1 equipment, which is rather unique. Therefore -- so our system can handle both, then the number of module increases. So the compare with -- the process -- only processing chemical-amplified process compared with that configuration, the process tool price is expected to increase slightly. But it depends on the configuration or specification of the process tool, which affect the process. I cannot say how many percentage of the increase is expected. I cannot give you any specific numbers. One more, high-NA EUV are not to be used for all layers. So even if we say high-NA EUV is introduced, maybe several layers for the first node. So it does not mean they need to invest several hundred billion yen for additional investment. So including front end and back end, it depends on devices. There are tens of layers, and all of them will use -- not all of them will use the high-NA EUV lithography.

So the cost increase, how do you think about cost increase?

Could you repeat your question once again, please?

From 5-nanometer to 3-nanometer, foundry cost is expected to grow -- increase. And how do I need to understand that? From the process to vendor, you don't see that as a big problem. Is that correct understanding?

The foundry cost?

Yes, please.

So 3-nanometer foundry cost or price. So the set manufacturer and design company to be -- the manufacturing are contracted out to the foundry. So when foundry received the manufacturing from , maybe that should be $15,000 for 5-nanometer.

So when it comes to this 3-nanometer, the price goes up by 60%. Does that affect your business as the tool vendor?

For the node, for example, 3-nanometer, the cost is so and so. So for our customers' design and integration methodology, depending on the choice of the design and integration techniques, the cost is different. So we are not able to give you any comments on that regard as a tool vendor. But as I said earlier, the -- but when we increase the productivity of process tool, what enhance the yield, this is how we can support our customers to reduce their production and manufacturing cost.

I am Kawai. I am Kawai. So for semiconductor -- so now we are shifting from the product to the value. So semiconductor used to be device of the industry -- the essential building block of the industry and high-end area, so high-value added -- the added value is increasing higher and higher. In order to realize some solution of value, this technology is essential in that area -- critical area. As for the process tool vendor, of course, we are working hard to enhance productivity and yield enhancement. So we try to pursue the technology innovation, which is essential for us as a tool vendor. But we provide -- so that provide the values, and customer can recognize that sort of values sufficiently. The customers -- and we are supposed to reduce costs. That's not the story. And digitalization and green digital and green, and we try to contribute the dream-inspiring society. So I think we can provide sufficiently high added value in our business environment, and there is a huge growth potential. And the technology innovation in semiconductor continuously more accelerated, according to my understanding. And as said in the beginning, the hyper-mass area, for that particular area, there are legacy nodes are to be handled. In that area, hyper-mass area, the cost reduction or price reduction is deposit options, and our solution business contributed a lot there. So this is how -- this is not the concern, but we think there is a huge potential for growth about your question.

Thank you very much for very thorough -- sorry, thank you very much for your question. There are quite a few questions, but now it's time for us to close the session and disclose the Tokyo Electron IR Day. For those questions, we are not able to answer today, we will upload answers to Q&A page of our website. And if -- please send the text of the questions, if you want to raise questions in text. Thank you very much for joining us despite your busy schedule today. Statements in English on this transcript were Spoken by an interpreter present on the live call.