Advantest Corporation (6857) Earnings Call Transcript & Summary

Welcome to Advantest Corporation's IR technical briefing. Thank you all for taking the time to be here. I'm Yoshitake Kobayashi from the IR Department of the Corporate Planning Group and I'll be your moderator today. Our technical briefings are designed as deep dives into the technological and the performance evolution of the semiconductors that we test which affects demand for our products as much as growth in semiconductor production volumes. Exploring these connections can yield important insights about the market. Today, we'll focus on high-end SoC devices and test technology. Let me introduce today's presenters. First, Koichi Tsukui, Director and Executive Officer, CTO or Chief Technology Officer, and leader of our ATE Business Group. Mr. Tsukui was involved in the development of measuring instruments and later served as the sales representative in Japan and overseas as well as general manager of the President's office. Currently, as the leader of the ATE Business Group, he directs the whole Group's tester business from research and development to customer support. Next, Ralf Stoffels, our Senior Vice President at Advantest Europe, who is in charge of V93000 marketing within the SoC Test Business Unit. Mr. Stoffels got his start in the semiconductor test business at HP 1994, and has been involved with the V93000 from its initial ramp. He has held various leadership positions in marketing. And today, he has world-wide responsibility for the V93000 platform as the Senior Vice President of Marketing at Advantest. Today, Koichi and Ralf will give a presentation titled, Test Needs and Solutions in the high-end SoC Semiconductor Market. After that, we will take your questions, we will deliver their presentation only in English. Presentation materials are in English only, but its notes are prepared in English and also in Japanese. Please refer to the Investors section of our website, where the materials are posted under news. Before we start, I'd like to emphasize that the future outlook described in the session is based on the current forecast, which naturally involve risks and uncertainties. Please be aware that actual results may differ from our forecast. Well, Mr. Tsukui, go ahead, please.

Good afternoon. My name is Koichi Tsukui and I'm the CTO of Advantest. Thank you very much for taking the time to attend our technical briefing today. I will explain how the SoC test business has changed and how our R&D management is responding to these changes. And I will explain our dynamic SoC test business and how I have been working on R&D management. After that, Mr. Ralf Stoffels, Senior VP of Marketing for the V93000, will speak about the market environment for SoC semiconductors, future test needs related to high-performance computing which will drive the Soc test market in the future, and the solutions we provide. Let's start with a look at SoC test business environment. Semiconductors support global safety, security and comfort. The use of semiconductors is expanding and technological progress is making our lives more convenient and comfortable. Amid these changes, semiconductors are being used in more applications, and the demand for semiconductor test is increasing as the technology evolves. Looking at the direction of technological evolution, in addition to the trend toward miniaturization of advanced process devices, there is a trend called 2.5D/3D scaling, intended to boost energy efficiency through improvements in circuit integration. All these changes in various semiconductor technologies, which we call waves, accelerate the difficulty and the complexity of test. Next, I will explain the R&D management for capturing these waves. We maintain a high level of R&D investment as a driving force for value creation and social contribution. During the period of our second midterm management plan from year 2021 to '23. We plan to invest a total of JPY 170 billion in R&D, an increase of JPY 50 billion from the previous midterm plan period. I will briefly introduce our R&D management efforts since 2018 when we launched our first midterm management plan. Plus, we promoted R&D based on a long-term road map that takes its shape from semiconductor technology trends. We are striving to expand our platform strategy to a wider variety of customers and applications. Secondly, we provide integrated solutions. We are expanding our business domain from semiconductor mass production test to the design and evaluation and system-level test processes, which are adjacent markets. We are also working to strengthen our test interface business. Third, we are seeking to develop a test business that utilizes the cloud software and data analytics. We have launched Advantest Cloud Solutions, a cloud service, and are working on commercialization with other advanced semiconductor companies and partner companies that develop and provide solutions. In addition to these 3 initiatives, we collaborate with leading customers and participate in industry consortia and work to solve customer problems. Next, I'd like to introduce our R&D network. Our main R&D base located in Boeblingen, Germany and the Gunma Prefecture, Japan. About 30% of Advantest total 6,500 employees are in R&D. Boeblingen mainly develops the V93000, and the Gunma develops the T2000 and memory testers. Previously the V93000 R&D and T2000 and memory tester R&D were separated. But in fiscal year 2018, we integrated them into a single organization and the global personnel rotations were implemented to speed up information sharing and development efficiency. I'm here in Boeblingen today and we have about 600 employees here. Whilst various waves of technological evolution in our business environment, today's focus is high-end SoC test. HPC devices, a market growing year-by-year, represent only a small fraction of all semiconductors, but the test intensity is much higher than other devices. Test technology requires not only measurement accuracy, but also technology such as thermal and power control. In response to these needs, in addition to our SoC tester platforms, we have strengthened our test interface and systems level test with integrated solutions. Ralf will now introduce our V93000 test solutions.

Good afternoon. Konnichiwa. This is Ralf Stoffels and I'm going to introduce our strategy and the market situation in the area of high-performance compute, which is one of the major drivers for SoC test and in that way, very important for our corporate strategies. Let's take, first of all, a look into the overall market. And I have chosen a very historical view here starting from the '80s of the last century. And it shows the semiconductor revenue growth over that long period. And it also, in a very simplified way, connects the major growth waves with the technology, which was introduced in that era. And when you look at the early phase, the dark blue era, that was the era of PC and internet and that drove the first big consumer wave in computation. And later then, it was added by the eras, so the era came on top of the era of mobility, which actually added a lot capacity and a lot of equipment for the next big wave. So that was basically driven by the mobile phone and all the mobile Internet applications. And I think we can very clearly see where the next wave, and that is this upper part in this greenish color is going to be driven by -- it is the area of high-performance compute and the area of artificial intelligence, AI. And you can see very clearly that the speed of innovation and the speed of growth have increased over time because each of those segments of those technologies have made it even more into the lives of everyday people. So it is -- while the era of PC was very much driven by commercial applications, only one family per PC, the era of mobility was driven by a phone per person, so the quantity went up significantly while the coming era is even further driven by proliferation in almost every aspects of life and every aspect of industry. And you will later on see that there are other drivers as well, not just only the volume to -- which drives the growth of that market. And this is also a history of our own product line. And I'm just showing here the history of the V93000. So the test system for SoCs, which actually got started with the era of the PC. So the V93000 was introduced in 1999. And with the first generation, we call it Pin Scale, and this actually enabled us to serve the test requirements of the PC and the internet connected devices. And then as the next generation of devices came up, the big SoCs driven by mobility, driven by smartphones, we actually introduced smart scale, so like the smartphone, we actually addressed this with a smart scale generation. And that generation of the V93000 tester platform actually drove a tremendous growth in the industry and also a tremendous growth of our own product, the V93000. And we just recently a bit more than a year ago, introduced EXA Scale. EXA Scale, the generation, which actually adds the capabilities, which are required to test new upcoming supercomputers and AI engines. And most of my presentation here will deal with the challenges and the upcoming opportunities which this gives us by our position in the market. And one of the reasons why we had such a successful growth of our platform was the ability to offer a compatible and upgradable system and a path for our customers to go from one innovation to the next innovation without having to change the essentials of their test programs and the investments they have made in the ATE. So we could always move our customers with a very little effort from one generation to the next generation of their technology and also from one generation to the next generation of our tester. And this is also the case for our newest EXA Scale generation, which seamlessly fits into that platform family. It was not only the compatibility, but also the innovations we have driven during that time, so which brought us basically as it's shown here to 10,000 systems. And that is just an estimation. So it's -- we are, of course, continuously growing. So we are probably already beyond that number. So the innovations, I would like to introduce also to you here on this page. We started already in 2000 as one of the first or we were, I think, the first who actually could already address 1 gigabit per second test speed for high-performance devices at a time when most of the other testers in the market were at far lower speeds. It was also very essential that around 2005, we were the first ones to introduce an instrument, which could have 160-amp of power supply, and we could actually add this to more than 1,000 amps, which was especially important for the big graphics chips, which were arising at that point in time. And you will later hear also a bit more about what I expect, what we expect the future is going to be in terms of power. In 2012, that was also the time when the V93000 became part of Advantest and Advantest platform strategy. We introduced the first card, which on every channel of the system could offer 1.6 gigabit per second. So that was also, again, the fastest ATE in the market. And we also, at that time, had the fastest and also deepest scan capabilities, the most vector memory in the market. And this was actually complemented by high-speed cards, which actually had an I/O capability of 16 gigabit per second. Also, again, at that time, the fastest in the market. And to an extent, it is still the fastest today. And just recently, as I mentioned before, we introduced EXA Scale. And EXA Scale actually adds the capabilities for the coming 5 to 10 years in terms of capabilities, speed, vector memory and power. And with the new cards, Pin Scale 5000, which goes to 5 gigabit per second. We are offering a card, which actually offers the headroom our customers need for the development during that AI and high-performance computing phase, which I showed on the previous slides. And the power supply is the other very important thing in this era here. So we are talking here about devices which consume hundreds, if not thousands of amps of power. And with the new power supplies, the XPS256, we are offering that capability and we offer a growth path to even more. And again, this is all in one scalable and compatible platform family. So even innovations we have actually driven into the previous generation can be leveraged into the new one, and it is all compatible so that our customers can very easily move from one generation to the next without a big break and for our OSAT customers, so the contract manufacturing customers, it is also a way preserve their investments in the previous generation, which is a big factor for them to choose the V93000 because they can actually really earn money continuously even after we have introduced a new platform generation. With that, I would like to also take a look into the technology changes and the market. So before I talk a bit more about the really technical innovations. We find for quite some time, a market situation where which is very much distributed into key players already. So we segment the market into PCs and server CPUs, into PC graphics and into mobile APUs and modems. So we use this segmentation because customers, but also technology needs are different in these different areas. So let's start very briefly talking about the PCs and CPUs. That's mainly the classic players. We're talking about 2 big companies serving that market as -- which are our customers. In PC graphics, it's very much the same situation. We're talking about maybe mainly 2 big drivers and a few very small ones. And in mobile, it is also very much the same. We are talking about let's say, 3 to 4 big players, which serve the entire market of application processors and modems for mobile phones today. But it is very easy to foresee change here. So let's actually look first at the upper segment, the PCs and server CPUs. So we find ourselves already today in a situation where, first of all, of course, the existing players are still the strongest ones. That's the upper box here. So that's the CPUs based on the Intel x86 architecture. But of course, it is very obvious already and visible today, we're seeing new computing architectures coming up, most prominent, of course, ARM which is already in a very, very strong position in the market for several years now and actually serving a lot components into the internet, into mobile devices and so on. And there's also an upcoming new architecture called Risk 5, which is an open architecture and offers new opportunities. And definitely, both can be seen as a competition and an add-on to the classical X86 architecture. And also here, we see a different way of segmenting. That's why I show 2 boxes here. One is that we have the PCs and servers driven by the classical chip makers, and we see a lot of them coming up. Especially in China, we see many start-ups arising right now, serving those processors, while on the other side, and that is the second box, we also see many system builders, so the big hyperscalers in the industry doing their own processing engines, not only processing, but also AI accelerators. They get integrated by those who, in the end, operate the servers. And that is basically their competitive advantage to build chips exactly to their needs. It has a lot to do also with power consumption and efficient use of power, which is 1 of the big key performance indicators in that market. Let's also take a look at the PC graphics. There is less of an architectural change. I think the big graphics players will stay the same, but they will actually get new competitors, especially in China, because China is on the path towards independence from the traditional technology. And therefore, there are a lot of start-ups coming up, which actually also engage in computer graphics, which is, of course, for us a new opportunity, a new market segment to serve as well. And then finally, for the modems and application processes, we also noticed a change towards more players, especially also, again, China, and in 2 different business models. One business model is again, the chip makers, the classical ones who are serving chips to those phone makers, but the phone makers themselves start more and more to design and manufacture their own chips. And that is also a new development which leads to more growth, but also to a different set of requirements by them to the ATE. So they require, for example, much more turnkey services. It's a very important development, which we take into account for our strategies as well. So having actually shown the changes in the market as such, let's also take a look at the technology moves. This is a very important view. Although I need to carry you a bit into technology details, it is the driver for innovation. It is the driver why we invest into new versions and new generations of our ATE. Let's actually pick these 6 different ones and start with the upper left one, the integration. So as mentioned earlier, integration is going on, especially for the big servers. And as one means to do this, we see much more Chiplets, so multiple singulated chips onto one package, in one package as the solution to grow the complexity as it is needed for those servers. That is also a very important fact for us as a test equipment vendor, because it has new requirements for tests. I mentioned already the ARM CPUs here shown, which is mainly a source for new players, enabling new computer architectures, and it's actually a very strong competition to the classical X86 architectures. On the complexity axis, you see that on the upper right, as just illustrated by this picture, we have with each major semiconductor generation change, so the node change, basically miniaturization change from, for example, 5 to 3. With each of those, we also have new technologies coming in. For example, some of the big foundries will change their technology already for 3-nanometer from these FinFET transistors to gate-all-around transistors, while others will do this in the 2-nanometer generation. That means that failure simulation models they use to design test for those transistors are changing. That means there's a long period of time where a learning phase needs to be overcome for testing those or producing those technology nodes. And testing is the major tool for them to learn how to ramp the yield towards the next generation. And that is where test is very much a fundamental helper and the test systems are being bought especially in those phases. Other areas like on the lower part of this slide, like 3D packaging, increased complexity, like power and thermal is driven by the fact that all this, what I described before, happens at the same time. So more transistors, 3D packaging, and also the next nodes are always driving for more power, and that is a big challenge, not only in operation of the device, but also during test of the device, which means that we actually are very closely working with our customers to find solutions to test those supercomputer chips in their next generation. And then finally, on the right lower corner here of this slide, we have, of course, a lot of interconnecting problems. So the larger a data center becomes, the more our customers are dealing with fabrics of data communication between the different computing engines. And that is, to big extent, high-speed technology challenge, but to another extent, also a power question. A lot of the power in today's data centers is actually used for the interconnect. And so therefore, naturally, the industry is looking for better solutions, including optical connections. And we, of course, are very closely working with them to see what is the next larger trend, and we'll be talking a bit about that, what are the challenges, and to what extent we need to extend our offer also to optical solutions to test those kinds of fabrics? Just zooming here a bit into the complexity of the transistors. I think I said before, it is not so much driven by the sheer volume of devices, whether we grow, whether ATE needs to provide more testers, it is to a big extent driven by the complexity of the devices as well. And when you look at those different segments here in the growth of, let's say, the millions of transistors here, and you see that the biggest driver per chip is the server's CPU and GPU, while the next one is then more the client, so that means the personal computer. And then the least of the drivers, and it is still a super big driver, is smartphone APU. And in a very simple way, you could say the test depends on the number of transistors. The more transistor, the more testers required, because every transistor ideally gets tested. And that means that the test times and the requirement for more testers are driven by the numbers of transistors tested. So that means we need to always keep the equation in mind, number of devices tested times the number of transistors per device. That's probably a very good approximation. It is not exact, but approximation of how much test is required. And we see this. So for the past several years, the test times of individual devices went up significantly by factors, maybe a factor of 100 in the last 10 years. And we also noticed that we have more tester insertion. So the device gets put many times, several times on testers during the initial production phase of a device. So for a long time, this was actually tackled by reducing data by compression. But it is very hard to achieve in the future. So therefore, we expect that the test times will even further increase. Of course, in very close cooperation with our customers, we try to reduce test time in order to make it always a commercially viable solution for our customers. But the big gains in terms of data compression are not to be expected in the future. So therefore, we believe that this gain will be on the number of testers required. And this is, of course, driven by new failure mechanisms, by 3D integration as well, as I mentioned earlier. Also new methodologies need to come up, and I will talk a bit about them. All in all, I think we can say, with what I showed before and with this transistor model here, that it is very fair to believe that the increase of semiconductors, which is projected from now until 2030, will also be an equivalent growth -- or will cause equivalent growth in ATE as well. So we believe that testing will actually track the growth of the semiconductor market, which I've shown on my initial slide. So let's take a look a bit into the challenges for ATE and what kinds of solutions we actually introduce and are envisioning for the future. I talked about complexity, and I think it can be actually twofold. It can be the transistors as such, so the type of transistors, the challenges with testing those transistors, but also the sheer amount, Moore's Law, more or less. And Moore's Law together with stacking devices, I talked about Chiplets, here we see a picture of 3D stacked devices. So we go in the third -- or our customers go into the third dimension, will actually increase the data volume to be tested by a factor of about 100. So this is easily foreseeable. It could be even more. This requires testers to also use the technologies which our customers use. And with the V93000, we have chosen a path where we use the same way of integration in order to grow the capabilities of our tester without making it more expensive in the same way. So you see here a picture of our test processor. And the test processor is an engine which actually we have in every resource of the test. So we have thousands of these test processes in the system. And you see the system is a very compact one. I think it has actually the smallest footprint in the industry. So this is only possible because we use the same level of integration like our customers do. Here, for example, a 2.5D integrated multicore processor together with the memory. And this device is actually developed by us, by our own R&D. So it is one of the core engines which power the growth and the capabilities of the V93000. This is, by the way, our latest generation, the EXA Scale. And you see here that, that way, again, we're the first ones and the only one so far who can actually, on every channel of the system, offer 5 Gigabit per second, so the fastest in the industry. And we also have the deepest vector memory, which, by all this complexity, driven by that complexity, is required to test those devices which are today coming up. And I talked about power. And it is easy to imagine that those supercomputer devices, even though designed for consuming less and less power by their complexity, drive power requirements. So we are talking here about 1,000 watts or thousands of amps current, which those devices draw. Not only the current consumption as a static variable or static value are the challenge, but also the dynamics of power. So depending on what kind of test is done, or during operation of those devices, what kind of load changes the devices have, the power can vary significantly. And the challenge is that this power gets actually controlled very, very rigidly. If the voltages of those devices change when the power changes, then you can't be sure that you really tested the device correctly. So it means during test it is one of the big challenges and the big requirements to keep the voltage very, very stable while you change the power in huge steps. And also here, we have chosen a technology which so far has not been deployed to test before. With the XPS 256, our new power supply, with the industry's highest power integration, which has 256 amp per card and where we can go far beyond 2000, could even be more amps in the system, we can actually combine many, many channels to actually provide those high currents and this maximum power to the devices. But not only that, we are first time using a full digital control loop. So it is basically, also again, computing and performance digital architecture, which we apply to our cards, which enable us to regulate the power faster than it can be done with the traditional ways of analog regulation circuits. And with that come also some other advantages like, for example, we can protect the probe card of our customers from being destroyed by high currents. So that is something which you can only do if you have high computing power even in such as an analog card like a power supply for the devices. The other big challenge our customers have is the test coverage. I mentioned already more and more test vectors, but there is also a new trend being very clearly visible. The devices -- like it's shown here in this very simplified picture of a computing engine, the devices are now dependent on software, even during their early phases and even during tests when they are not even in their system yet. And they show a much more system-like behavior, even when they are still on the wafer. Traditional ATE tests with digital inputs and gets digital inputs out, and this is all very much synchronized to the tester. We are foreseeing an era, and we are just entering this era, where software even has to be loaded into the device at the stages of test, which is a completely new way of approaching those complex systems. That requires innovation at the tester as well. So traditional test architectures cannot deal with the fact that the device is actually driven by something very, let's say, unpredictable like software algorithms. So traditional scan technologies need to be augmented by new software-based technologies. So that doesn't mean scan will actually replace, but it is an augmentation by new methodologies. And one of the new methodology is to actually provide a link partner to the device under test on the tester. And we just recently introduced the first of the industry's link scale cards. So we call it link scale because, as I said, is a link partner to the device. It links to the device and can actually interact with the device with native protocols and native ports, like, for example, PCI Express, used in PCs, or USB, like it is in many devices like mobile phones being used as a wired interconnect. And with this, we are actually offering the first time in this industry, a card, which goes, like every other instrument in our test head, here also in our very small form factor test heads, and it actually offers a functional test coverage on the tester at a stage of the device where it is still on the wafer, for example. In that way, we can find failures before the devices go into the expensive package and would basically cost a lot if we found those errors when they are already packaged. So we moved test content towards probe, towards wafer sort, and we also enable our customers with this card in the early stage of their design process to interact with the device much better than they could if they just had a normal test access like we have it for many years. Again, this will not replace our today's test methodologies, but it will complement, it will add to those methodologies we are using today. With that, I would like to summarize my speech here. So I think we have seen the market has a lot of potential. This picture shows the semiconductor market, but it was also very clear foreseeable that the ATE, the tester market will track this growth very much. So we believe that the tester market will grow by the same factors. And some analysts actually say we are seeing a semiconductor market of about $1 trillion by the year 2030. And as I said, we see the same percentage growth in that same period also for ATE. And a lot of this will be driven by digital integration. Of course, there are other important areas as well, but the major growth comes from computing engines, from integration of digital structures into devices, which actually drives the complexity for test. I talked a bit about the challenges and opportunities and this 100x complexity growth is one of the big driver engines. Of course, it is also the amount of devices being tested, but it is to a big extent also the -- or even bigger extent the complexity, which requires us to offer more and more clever ways of dealing with that. Also, the nature of the market is going to change. So like, for example, big system players who operate usually the data centers are becoming system designers and even chip designers. They have different requirements than the classical ones. So we are talking here about turnkey test, which demands from us as a tester supplier to also change our ways of doing business with those customers. And for them, of course, time to market becomes more and more a major challenge because competition has gone up. So you have seen that on those pictures. And again, the way of doing this, we believe, can only be by evolving our systems the same way the market evolves. So the V93000 did that for many years. You could see that we developed the V93000 with the leaders in this industry and for those leaders in the industry. And we always used very similar ways because we believe in integration in silicon. So the more we can use the Moore's Law integration and 3D or 2.5D integration for packages, the more we can offer those innovations at a cost for our customers, which actually makes sense for their cost measures. And so also here, we have proven this by being basically the market leader in the segment of computation. So we have a major market share today, and there are good signs that we can continue this because we are right now, again, in the leading positions. And with EXA Scale, that is basically the step into that next generation. We have chosen the name. So we go with our scale, so like Smart Scale and now EXA Scale, with a same name, but EXA Scale definitely also relates to the area of EXA Scale computing, which is basically the driver for the growth, but also the driver for a lot of challenges which we address with our technology. And with that, I would like to thank you for your attention and available to answer questions afterwards. Thank you.