Aldec, Inc. (MCHP) Earnings Call Transcript & Summary

Hello, and welcome to Episode 3 of the [ My 5 ] Unleashed Training Series. My name is Alicia. I'd like to start off today by playing a quick housekeeping video. [Presentation]

Awesome. Now that we've got our housekeeping items covered, I'd like to introduce our presenter for today's session, Alexander Gnusin. Alexander will be discussing the linting and clock domain crossing analysis for Microchip FPGA designs. Before we get started, please take a moment to access the menu bar at the bottom of your screen to see all the engagement tools we have available for you to use throughout today's session. Also, as a reminder, our session will be available on demand to view. Now without further ado, I'm going to pass it over to our presenter. Alexander, please take the way.

Hello, and welcome to our webinar. Today's webinar is about linting, which is static analysis and CDC verification or Microchip FPGAs. First of all, let's start with webinar agenda. The first [ section ] we will cover is what static linting means as well as what CDC analysis? So we just ramp overview of static linting and CDC analysis. Then we will introduce [ L dex ] tool static verification tool, ALINT-PRO. We will ramp [ to ] overview and present you a few examples -- simple examples. Then we will switch to static verification of Microchip icicle design. We will show how to apply static verification on Microchip icicle design on Libero projects. We will show you automated project conversion as well as we will run automated printing of Microchip icicle design as well as CDC analysis. And then we will -- at the end, we will run -- we will do a conclusion and Q&A session. Let's start from the first topic, linting. What linting means? Linting actually -- and what -- how it helps to design us to -- in design process? Linting designers to uncover batch early in -- very early in design flow. Even before the simulation, once you only run [indiscernible] [ your TR ] code, you can run linting on this code and find very different issues starting from naming conventions and up to synthesis issues and maybe even long combinational passes, if you have them in your [ logic ]. And this process is very tough, and it can be run very early in design stages. And by doing that, you will actually save a lot of time because if you find bugs or inefficiencies as soon as possible in design process, then you will save your money and your time and don't propagate this box to the later design stages, especially the implementation stage. Definitely, it will save time on the implementation iterations once -- for example, running synthesis with Libero, you can run [ a stupid ] amount of tests once you've solved lots of implementation issues before lint tool. Also, it helps to implement automated [ code reviews ] and reduce cost of review, basically manual labor. And most of the tools are based on comprehensive knowledge based on industry best practices and also our growth engines later on, which we used in ALINT-PRO. And this can be applied to automate [ code reviews ]. And what is the technology of linting? Basically, if you think about lint tool, it's a kind of lightweight and very simple implementation tool, which runs parse, elaboration and then high level synthesis. High level means you don't run synthesis mapped -- basically, don't map your design on [ specific side ] library. So basically, you just [ admit one ] technology [ independent ] library like basically [ float moccasin ] and so on. But this process takes more amount of time. It generates [ net list ] and linting with the static analysis, analyzes design and different presentation level starting from [indiscernible] parse, you basically run parse specific rules, when you check for [ several ] naming conventions from marking commands and so on. Then you go to elaboration, and then you extract [indiscernible], you build your design and then you check other rules related to the [ DRT ]. Then you synthesize and once you've synthesized, you have to check different synthesis-related issues and [ make check ] designs and stability as well as your design is suitable to synthesize with different synthesis, too, which is usable between different synthesis, too. And then you generate [ net list ]. And [ while not to generate net list ] you can also check [ net list ]. Here, we have -- you can apply part of much of technology on [ net list ], and we do that. And this is part of [ martian ] technology, we can extract different issues. For example, we extract run clock [ trace ], we extract the [ set trace ], we extract [indiscernible] issues, for example, [ run clock ] that is data is [ 3 o'clock ] and so on, which -- basically we extract clock [ trace ], and you can also see them in [ graphical ] form in our viewers. We have clock [ in set viewers ]. Then we also attract clock domains, [ extract all ] domains. We also -- there is also a need to supply a [ gen constraint fob ]. Then we understand clocks. We understand clock boundaries. And then we understand passes. Going from one clock to another clock domain, and then we will look on specific design patterns, correct synchronizers between those clock domains. And once we extract them, [ which helps them ]. And if they are not [ exist ] there, we can generate [ an error forcing the see ] analysis. And that's basically -- that's our technology underneath the 2. And also ALINT-PRO contains complete FPGA vendor primitive support for most FPGA vendors such as Microchip. If you talk about clock, the main cross analysis, and this problem is twofold. First of all, we have to analyze static -- [ metastatic levels of ] design, extract log domains, [ recognition ] patterns and so on. And secondly -- second part of the analysis is ensure proper behavior of signals cross and clock domains. For the first part, we use ALINT-PRO, and ALINT-PRO runs static verification, extraction clock domain, identifies clock generation, [ identifies ] clock domains, ensure clock domains [ crossing properly with -- carted with static ] synchronizers. And once we do that and we pass through all the stages, then we can also generate [ system log assertions ], the world's functional simulation and then can be added to verification -- to regressions or test environments to make sure that signals don't violate -- signals [ closed ] cross and clock domain. Don't [ transgress particular rules ]. For example, [ poor pulse ] is too short, the signal going from slower clock domain to higher clock domain -- sorry, opposite and so on. Now let's talk about ALINT-PRO and its features. static -- as I already mentioned, ALINT-PRO [ is a static ] verification tool, which means its performs analysis, and the input of this analysis is [ up tiered ] alone or [indiscernible] sources [ as the Siemons demonstrates ], okay? And without -- our total [ structure ] require complicated setup. Setup is very easy. And then you can just run with kind of push button approach to start linting. ALINT-PRO container has the [ auto 50 port ] support, [ includes a ] dedicated rule set for companies actually running [ the auto 50 port ] compliance. And ALINT-PRO contains a number of different and very useful visualization windows. In addition to generating violations, it also provides different means to visualize design. And one of them is, as I mentioned already, clock schematic -- reviewing the clock to extraction and the reset to extraction, you can see the different windows. Also, our tool is able to extract FSMs from design. And once extracted, they are also analyzed for different issues as well as you can see them graphically in -- at the same viewer. And you can see this yellow stages here. Yellow stage and positions and so on. It runs CDC and RDC verification. RDC means, what is it? Domain crossing. In this case, just for design -- designs containing a synchronous reset from different clock domain. But we're not going to talk about it this issue, but it's still there. But we just -- in this presentation, we cover only the CDC part of it. And as [ all of the ] mentioned that it contains complete FPGA libraries, so also all libraries are [ compiled ] in ALINT-PRO. All libraries -- all library components are already constrained for CDC analysis. So whenever you [ use that ] in design, you can run a CDC verification as well as we support automated project conversion. You can just click and convert -- click Libero projects and convert it to ALINT-PRO and [indiscernible]. Primarily, ALINT-PRO is able to generate -- automatically generate assisted generator constraints. In the case you don't have the extent of your design, you can run CDC analysis. At the same time, you actually generate constraints templates that can be used for the -- not only in linting and CDC analysis, but also in the implementation, the natural implementation with Libero or other implementation tools. Let's talk about ALINT projects. ALINT-PRO provides powerful [ static generated ] verification that are [ cured ] at this level. During [ parse ] stage, once [ you par the cord ], we run chips for code [ for margin ] for layout comments and so on. Naming conventions, once same as coding style and [ which construct ]. Once we run elaboration stage, we can check for design [ portability ] IP chips and so on. And then we run a very faster synthesis. I'm talking about [ independent ] synthesis, which runs actually half a minute or maybe less, depending on the design size. The ones we synthesize, it automatic checks [ for SA ] synthesis optimized for area and [ timing ]. For example, we check for a long combinational process. Those are not exact process you can see in [ mech ] synthesis. But still, you have a good idea in the very early stages of your design and development where you want have to optimize your logic for time. One of the important checks [ area checks ] is simulation, the synthesis functional [ mech ]. Here is a -- depending on coding style -- there are some dangerous coding styles, which are actually allowed by, let's say, [indiscernible] standard [indiscernible] synthesis tools, when you may get design, actual implementation functions differently from your simulation. And for example, if you use a nonblocking constructs, one like maybe nonblocking forms as one after another in sequential process and so on. So these issues may actually cause this functional mismatch. And it's very important to -- actually to avoid all these issues and making sure that your implementation actually works exactly the same as your simulated design. We already mentioned we run graphical [ extraction ] and do chips [ and also ] so you see, for example, one of the examples of introduction to ALINT-PRO, we generate design constraints and also checks for missing [ design ] constraints or uncomplete design constraints in the case customers supplied those design constraints to ALINT-PRO. We run clock and [ recepting ] verification. And also we run CDC clock domain crossing verification. ALINT-PRO contains number of plug-ins. The first plug-in is basic. It comes with the tool, there's no cost. And basic prevents simple coding mismatch [ for install ] and so on. And Aldec premium [ like actually it ] complements. Aldec basic plug-in, providing much more rules and actually making sure that you cover most of important projects. Aldec CDC plug-in is developed for CDC verification and contains about [ 60 rules], different rules also related to the clock [ trace to ios to exempt ] constraints and also CDC analysis to make sure that you basically cover all aspects of CDC and don't have any issues. [ Star crews ] are based on tutorial -- basically the book by -- that written by semiconductor technology, academic research center. And the -- those -- this in Japan and covers [ just an introduction ] based -- was set up by main companies like Fujitsu, Panasonic, Renaissance and so on. And that covers best industry practice and contains a significant amount of chips. It's very -- it covers a lot of topics of [ arterial ] design, and it's highly recommended also to use with the companies. The [ 50 ports ] plug-in basically is targeted for companies [ undergoing certification ] for standards and compliance. And RRM or [ reduced ] methodology manual [ pro ] plug-in is based on RMM manual developed by main EDA companies such as [ Synopsis ]. Let's start with ALINT-PRO. And now I will show you simple examples. And I will probably switch from slides to my screen. Here is ALINT-PRO GUI, contains a number of widgets. And that's how you see ALINT-PRO the first time, you open it up for installation. On the right side [indiscernible] flow manager, and the flow manager you see demo projects. You see those demo projects only when no workspace projects are loaded. And here, you can pick either one of them and basically train -- run CDC -- not run -- linting [ and to see ] how to [ run this]. So let's take one of them, which is a simple project [a cassette ] written with system [ with the lock ]. And it's only one file. And [ the system ] looks quite complicated if you look at [ system lock code ]. And let's run verification. In fact, [ to the ramp ] here. And you can see different -- basically, we can actually [ clean ] the project, run it again just to see the process. So you can click on this green arrow on the top or you can double click on run project. And as you can see, once you click on flow manager, you can see different phases. Parse, elaborate, synthesize, constrained and then linting and then report generation. And those are phases related how to process the code. So it starts with parse. And at the same time, it can [ trans parse ] linting. Then it goes to elaboration, and then runs elaboration and goes to synthesis and runs into this linting and so on. You can basically run altogether by double-clicking on run projects. At the same time, you can run projects and you develop different scripts with [indiscernible] based language supported by ALINT-PRO. You can run [ almost like ] project [indiscernible], for example, to run it, and you can develop scripts to run linting in a batch mode. It is highly recommended. And only in the case of debugging, you can open GUI, right? Because once you run linting, you don't get the necessarily need to open the GUI. Here, we have the violation here. And in violation, you'll receive couple violations. As I mentioned, this design is about FSM extraction. And even before going to see the rules, we can open at assembly viewer. And here, you can see different viewers [ and at these ] windows here, as you can see, violation viewer and so on. [ Notice here ] you have a schematic viewer, clock and reset viewer, [ contra ] schematic viewer, [ after assembling ] those, you can see FSM viewer. So let's open this one and see [ the schematics ] of your design, and you can see one [ the schematics ] found in the [ new ] design and two -- understand it is [ type more ]. And you have different [ controls to separate ], for example, you can require all [ that it stands ] to be owned [ with or ] type more or [ medium ]. And you want to -- you can also define and [ restrict ] at the sense, have specific states and encoding. In this case, it's binary and so on. And this is how you extract at the [ strands ] and also you can actually visualize at the [ strands ] by clicking on so [ in draft ]. And then basically, we'll see the same graph. And you can see different colors, and these different colors relate different to the same valuations. And we can those valuations in the [indiscernible] viewer start from the first relation [ avoid deadlock state and restrictions ]. And it shows S-13 state, which is marked in the red, is at [ deadlock ] state. And definitely, you won't see going out from the state. It's only going into basically it's a [ deadlock ] state. And if you want to debug it, and you don't have this window at all, so what you do is just click on it, and you can see sole source. You can see it on -- in actually source code or you can see it in [ the same ] graph and it will show you [ this actually replace it in ] the same graph. And then you can debug it and fix it. Second is [ at stand ] state is unreachable. Actually all the group of states looks like it's unreachable. Also, it has also incoming [indiscernible]. For some reason, this [indiscernible] is marked with red cross. And maybe this cross actually leads to the situation where you cannot reach those states. And you can also debug [ this arc ]. So we just click -- double click on this arc. And it [ will sit as this ] particular transition and specific expression -- condition for the transition, which is if count more than 7, then you go to S-10. Now count is a variable, defined here and it's variable -- as you can see, it's only [ 3 bit ], [ can count never can reach farther ] more than 7. And therefore, this arc never should be taken. That's why we have this red cross [ basic tool ]. So tool automatically analyze the -- it runs semiformal analysis. It runs [ BDB ] based analysis to make sure that all conditions are executable. And in the case it is not executable, it actually -- it sets -- it checks it and automatically defines this portion of sets -- states as unreachable. Same you can check eligibility -- executable conditions not only in [ the sense ] but anywhere in the code. And this basically example of [ cassette ]. Let's go to another example. And here, I will go over slides, [ see here ] with slides. And let's go to simple CDC analysis demo and open other project. In this project, we see a very simple design where -- let's just quickly run synthesis just to see what [ does that ] means. But basically, it's a very simple one. Now we also talked about flow manager. And before I showed you -- default flow. Default flow means [ defunct media ] when you're going sort of different phases, parse, elaborate, synthesize, constraint and so on and running along with -- going through those phases. Now let's choose another flow, which is CDC, [ efficient ] CDC, debug and flow. And this is another flow developed for actual CDC analysis. In this flow, you go through different steps. First of all, you go through design entry, and we can run it quickly here. And with design entry, you have actually, you just parse, elaborate and synthesize your design. Now we're already done here. You can see it in the upscale schematic. This is simple upscale schematic, you have to close clock A, clock B which are synchronous clocks, and 1 clock from there. If anything, there is the CDC valuation here because you don't have 2 [ flip clocks ] actually synchronizing data going from Q to D, you have only one of them. And also, we have design constrained files format is [ outlet ] design constrained, which is similar to SDC and [ clock ] actually enhances SDC with a few other command such as, for example, block level constraining [ weakened ] constrained, for example, [ at A ] blocks and the blocks without actual internals, protected blocks and so on as well as the research-related commands. We can define a -- similar with define create clock. We can define create reset. And with create reset command, we can define, for example, if we want to see -- to have a asynchronous reset with active law and with this specific [ chronology ] clock and so on. And then once we define reset, we actually can -- we are able to check the actual [ built ] reset within design complies to this constraint. And let's now -- and here, we see that we -- in this specific project, we have -- they have all design constraints. We have 2 clocks defined as asynchronous [ clock loops ]. We define input delay for clock A phase. For the in and clock B for [ clock ] A out. Timing here, we don't -- in fact, we don't care about timing in the CDC analysis. We just care about phases -- phase definition. But at the same time, if you develop those files, and you may already set proper timing for the implementation, and that can then be used later in implementation. Or you can bring the implementation SDC file to ALINT-PRO. ALINT-PRO understands definitely block SDC, files you can add them to project. Then we can run clock setup. During clock setup, it extracts clock 3. It checks that all clock-related constraints are available. In the case, for example, you don't have at least one of those great clock constraints, clock A, it will provide you a violation saying that one of clocks is unconstrained. And at the same time, once you run through these phases, it automatically generates [ gen ] constraint template. In the case you don't have those constraints, let's take a look at the project directory, and there is automatically generated ALINT output directory with a constrained folder. And then here, you can see chip level [ KDC ] files. Currently, it's all -- this file is automatically generated by ALINT-PRO right now, when you run this clock setup phase. And it contains kind of -- it contains commands -- basically, all of them [indiscernible] commanded like [ claw ] definitions and so on. And this information is actually extracted actually from design. So ALINT-PRO analyzes design without [ sent ] constraints, extracts clock 3, understands which ports are clock ports and actually writes this file according to our design structure. And in our specific case, we already have those constraints in design file. Therefore, all these constraints now are commented. But in the case some constraints are missing, for example [ missing ], then you won't see -- basically, they won't be commented. And then there is a task of design that just copy/paste commands from this template file to actual design constraint files of your design and move forward. For I/O setup phase -- now we are running I/O setup, which is set input delays, set output delay commands and making sure that those commands are complete. As I said, as we see here, we also have only 2 inputs, 1 input and an output, all of them are covered here, so we don't have any issues. Reset stuff is extract [ clock ]. But in our case, we don't have them. And now let's go to structural CDC analysis, which is last stage -- last step. And you can see that there is a violation here. Also, once you [indiscernible] state through [indiscernible] it's very useful to use graphical viewers like, for example, [ methods ] to visualize extracted [ clock phase ]. And here, we have [ clock phases ] those are very simple because we have direct connection from clock to input port [ 2 o'clock ]. But still, we can analyze and we can see them. But in other cases, you see complete design. There is clock going to specific blocks and the clock here [ are here obstruction ] and so on. And let's take a look on this violation. And violation [ said that all of this user synchronization ] circuit the transfer data between synchronous clock domains. Actually, I forgot to tell you before that, first of all, once you see these valuations here, you can actually read documentation about this violation. You can understand better why -- what does it mean and how to prevent it. And that's why just double-click on violation in version [ 2 ] and see the documentation. You can read the documentation, you can see different -- but then we also have 2 examples. And one example is failed example and other is corrected example. And those are real good examples. You can easily [ take them ] to your project and actually train on those examples. I think it's a very good means to train, to understand if in case you don't understand some specific rule or you have some [ lapse ] and so on. It's very useful to [ copy ] pass those examples to your project files and actually run them. And here, we have valuation instances. And here no synchronize -- there is no synchronize -- that's what we expected because only one clock [ not to flow to ] another side. So let's -- we can see them in the source code. We can see them in [ after ] schematic. In the schematic it shows the CDC pass, which actually is going from [ one ] domain because this clock is clock A, this one is clock B, and this is a crossing. And there is no here [ representation found ]. There is no 2 [ clocks ] found, only one here, right? So let's -- what we can do now -- now we can also open CDC here, which is another graphical viewer here. And you can see the clock domains. We can see crossings from and crossings to those clock domains. And we can see that from both clocks from -- basically, this is crossing to from clock A to clock B, same as basically here, to clock B from clock A, but other as an order. And we can see that there is no synchronization here. So it's not synchronized. And that's why we have this violation. And what we can do now, we can go quickly and correct the code. And just another clock to the clock B and then rerun it. And now we don't see any violations. Let's take a look at CDC viewer now. And here, we can take a look at source synchronizers. This is actually clock and reset here, [ look at ] CDC here, clock A, crossings from clock A to clock B. And you can see now that it synchronize -- proper synchronize structure is found, it's called [ NDFF ]. So basically, it's 2 or 3 [indiscernible] clocks, depending on the exact requirement, you can make it. There is just 3 stages and so on. And there is no issues and it's synchronized, and you can also visualize those synchronizers in either [ schematic ], okay? So that's the pass. And now we have 2 flip flops on other side or you can filter it in CDC schematic, and CDC schematic is another way to represent design based on clock domains. So have we clock A domain. We have clock B domain. And here, actually, we have all passes -- this pass actually combines all CDC passes going from clock A to clock B. And we can see starting point on this process, and you can see end point on this passes. And usually, those end points should go in this space to valid synchronizers so we can look inside those blocks, which is a kind of inbox. And we can see in this box actual valid synchronizer, 2 flip flops. Now let's move to other topic and then we can go to -- and first of all, let's take -- let's review where we can use ALINT and CDC in FPGA design flow, talking specifically about Microchip [ sent ] flow with Libero. First of all, the first place to use linting -- I'm not talking mostly about linting, not CDC, but linting, it's the very first -- very early stages of design development even before you bring them to Libero, you start running stuff. You can parse, elaborate. You can check syntax. You can check synthesis issues. You can check other issues, naming conventions and so on with linting. So it's really advisable to run linting as soon as possible. As soon as possible, once you have even maybe some portion of your [ tail ] block development or maybe some set of blocks development, you can run linting as soon as possible and find different design issues and correct them as soon as possible. And the second place to run linting is once you already run Libero flow and you run over the synthesis. So because after synthesis, you already have a net list, and you have full design. And this is the place where you can run CDC analysis, not only linting. Linting is also important here, but most important also is to run CDC, clock domain, crossing analysis after synthesis. And as I already mentioned, linting CDC analysis around checks and the [ up there with ] time constraints, checks for clocks, resets and so on. So basically, took place to run linting. Now let's talk about automated conversion of Libero project. And ALINT supports partner of Microchip libraries. We can go to our viewer and see design management window library viewer. And in the library viewer, we can go to global Microchip. And here, we can see all families and microchips loaded and then automatically attached to the project during conversion or you can mainly attach them once you run any projects. Then we also support automated Libero conversion. And here, I can show you under tools, we have convert [ section ]. And here, you can see we can convert from [ quartos ] as well as Microchip and [indiscernible] Microchip and select icicle design, select icicle project, file [ FTX ] format, click next. And then we will see -- now we see that all project [indiscernible] is extracted. In the viewer, in case some files are missing, which means that [indiscernible] mentioned in FTX file, but actually don't -- not exist in the [indiscernible] system [ as you see in the red ]. So it's a program. But in this case, we don't see any issues here just [ to view the ] structure and click on finish. And then it will take some time because project is a bit big, and connection takes maybe half a minute, and just wait for these project to be loaded into ALINT-PRO. Let's now -- let's just talk other topic -- talk about how -- around linting on Microchip icicle project. Just -- from now once it's loaded, I will just move to the next slide. And once we start around linting, first of all, we run parse and elaborate phases, same as you parse and elaborate your code. And ALINT-PRO has a complier, which is industry used compiler. And compiler by itself throws warrants and errors. Whenever compiler has error, definitely it stopped compilations, you have to correct the code right away. In the case of compiler throws warnings, those warnings still allows you to go to next steps like collaboration and so on. but I think it's still very important to check for those warnings even before you go to check ALINT-PRO violations because those warnings really actually point to design issues. For example, like we have not inside of the constructs, net result drivers out of French indexes here [ interspersed ] connections, which [ ports ] are unconnected. In some cases, it's okay because we just [ reuse ] some other IPs, but still it's really important before -- even before we go to actual -- to linting, to look at compiler warnings and making sure that we can eliminate or at least understand those warnings. Now you can see in our design that our project is converted, and it contains different library selection, comps, work, same structure and component in structure, as you can see, in our Libero projects. And there is a -- and so on. Now let's just open -- as I say, already, I will close this window and open our other instance of ALINT-PRO with already linted design. And the reason of that is because it takes some time. We just want to save some time. It maybe takes a couple of minutes to run linting. And here, we already have it. And this is the main project. Just a second. It's loading. It's loaded here. And here, we actually what -- linting here is already have been run, and we have our violations here. And let's talk about those violations in our slides. Those violations also are described in the slides. So we can review rules by different types. You can review by rule level, by severity level. And for example, this rule level, so we have rules, we have recommendations, and we can see them in different ways. So let's review them by rule level. And just [ kick ] back that slide. So which issues -- here, we have some connection issues. So avoid unconnected ports, you can see it here, right? And here, you can see unconnected ports, unreachable states of [ suspended ] descriptions. So design extracts in a couple of FSMs. And in fact, we can also see the FSMs extracted in the [ example ] here. We can click on them and also click on [ show them in graph ], for example. [indiscernible] And there are different issues like some -- unreachability issues, for example, for FSMs. So we can click on this violation item and debug it with FSM graph. Here, for example, we have those 4 great states. They have only arcs from the states, but arcs to those states. So those states are unreachable basically, right, from the main [ system ], maybe it's because of design reuse. But still, it's really important to analyze those -- and [ present ] those places in design. Code redundancy issues. Here, we have [not the type of things ] should be used within the -- [ in the court ]. And this is other issues. Those are in recommendation sections. But still, I think it's important to understand which [indiscernible] object are not used. We want to click on object. We will see different objects like parameter, sports and so on, which then [ not just in ] design. Maybe they are [ deposited for other ] use, but still it's important sometimes to understand, especially during early design development, it's really important to clean up your code with -- to check all those issues. [indiscernible] related issues, not duplicated, not block and signal assignment. And so let's -- probably just to go now to other topic, which is CDC analysis. I think I already showed you the value of the 2 and value of those messages, right? For example, [ index ] should not exceed [ and object ] range this one. And here, we can see that [ index ] once we click on source, we can see some unreadable source, so I don't know how to debug it. But still, we can just -- it's important to understand and analyze those issues. Reset-related issues. In one case, we have don't have both asynchronous [ set ] connected to [indiscernible] line, both synchronous and asynchronous and make sure that if you have asynchronous [indiscernible] define, so it should not be [indiscernible] both to synchronous and asynchronous reset of design. And then let's go back, so we talk about CDC. And to run CDC, I will switch to one of our icicle blocks, which is for [ inter connect ] and make it [ enough ]. Now let's -- okay. Let's go to the slide. And here we switch to CDC. And here, we already run CDC, so we have a couple of violations here. And once we analyze -- basically, this block contains [ FXI ] interconnect switch with 8 primary and 8 secondary interfaces. And those primary and secondary interfaces could be parameterized as to be pretty independent. So it can be around with different clocks. In this case, we have [ 16 ] different clocks. First of all, the work we can do here, we can take a look at CDC viewer. And you can see that in CDC viewer, we have all these clocks defined and then we have crossings from, crossings to the clocks, and we can see how they are synchronized. And ALINT-PRO is able to extract about 10 of different correct synchronization patterns, not only flip flops, but also white flip flops when they have actually memory. In this case, you can see a white flip flop and one memory and the synchronizers. And this way, you can actually see how rich -- which synchronization structures between different clock domains. We have violations. Those violations actually [indiscernible] contain pointers, which is [ left ] pointer and right pointer. And those pointers are not to beat, and we actually pass pointer [ above this ] for one clock domain to another, right? And here, basically, we have [ 4 bit ] pointers, 3 bit actually pointers [ they're both from ] clock domains. And it's possible only when the bundle of this pointer is basically [ gray ] coded. So only 1 bit changes at a time at one clock cycle. And we still [ extract that ] as warnings, but also generate assertions. And these assertions can be used in simulation. In those assessments, actually, they require. The functional behavior at this pointer has to be a gray coded or not necessarily gray coded, but every time should only 1 bit has to change time. And that's why once we run CDC, we have pre generated CDC receptions. And this file is already generated. I can show you in file browser, output, functional, CDC assertions, CDC assertion file. And here, we can see this file, and this is actually a separate module. [ In system lock ] you can just add it to the verification environment on the top of your design on the test. And it looks inside design signals, and it checks for different valuation such, for example, as a CDC 1 bit change. It's exactly the violation actually as related to those [ left ] and right pointers. So only 1 bit can change over time and other chips [indiscernible] and so on. This actually relates to only those [indiscernible] extension patterns we found in this design. And this is actually -- finally, we can generate CDC report. And I can show you the CDC report in slides. So basically, we run [indiscernible] constraints. And I already showed these stages in simple design. So we can do the same kind of generation of constraints -- missing constraints and so on here. If you want to -- if you don't have, for example, constraints. We run CDC analysis here and we analyze results, and we can see clock trees and reset trees. And also same way, as I showed you before, with CDC viewer, we can see different clock domains as kind of separate boxes. And those passes are all CDC passes going through those boxes between clock domains. And finally, we can generate a CDC report. And this CDC report for this model. And CDC report contains all information about CDC analysis, including clock domain info, asynchronization info, extracted analysis info. And also you're able to set up others [indiscernible] static signal, that's not -- that actually crossing clock domain, but it's not changing. We are guaranteed this stable during a functional operation of our design. In this case, we can kind of mark some CDC passes as [ valid ] and don't check the structures on from those passes. Basically, I already mentioned about CDC violations. And here is actually this automatically generated once you run a generated CDC assertion stage of CDC clock. And here, we are going to finish our presentation and going to recap session. And recap of points discussed include ALINT-PRO provides automated conversion mechanism for Microchip Libero projects. It performs an advanced linting right after the conversion. We can use different advanced viewers schematic FSM [ globe tree ] viewers, CDC viewer to check design structures, we check for CDC violations, can be generated [indiscernible] functional notification. And as an overall statement is linting and CDC analysis helps finding these critical design box, improving code quality and reducing implementation cycles number with Libero environment. Thank you very much. Now we can go to Q&A session.

All right. Thank you so much, Alexander, for the great presentation, and thank you to our audience for attending today's session. It does look like we have a few questions from the audience. The first question is, how do you constrain hard IP blocks for CDC analysis?

As we already mentioned, Libero and other FPGA vendors contain [indiscernible]. And this [indiscernible] basically don't provide internals [indiscernible]. So what should we do? For example, in CDC analysis? How we know that -- because in CDC analysis, we want to actually to see all CDC passes propagated through those IPs as well, right, and understand which IP input and which IP -- especially which IP output is faced with which clock. So for this purpose, we develop other kind of addition to CDC -- to SDC format, which is we call block level constraints. For example, instead of create clock command, which had clock for design port, we have create cell clock command, which creates kind of a pin, which sets the specific pin of design IP is a clock input. And then once we define clock inputs for this design IP, we can define base relation between inputs and outputs to specific clocks and so on. And this way, we can actually constrain block level designs towards CDC verification.

Great. Thank you. We do have time for one more question. And the question is, how does ALINT-PRO generate design constraints? And are they suitable for actual implementation?

I already mentioned that ALINT-PRO [ advanced ] through different CDC phases. It actually generates different portions of missing constraints, or in the case you don't have constraints, that also generates full constraints, and then they have to review it. And the only -- so yes, those constraints are fully suitable for actual implementation. The only thing that I already mentioned is that just -- you have to change timing, for example, clock frequencies and in I/O delays and so on and maybe add some other constraints, for example, [indiscernible], but still, ALINT-PRO provides kind of very suitable and convenient way to start with -- to generate [ some ] constraints, which can be used not only for CDC analysis in ALINT-PRO, but also in later stage outside of ALINT-PRO with actual design implementation.

All right. Awesome. Thank you again, Alexander, for your presentation, and thank you again to our audience for joining today's session. We ask that you please take action on your screen to stay up to date with all of our exciting [ My 5 ] ecosystem unleashed content. Thank you, and have a great day.