Applied Materials, Inc. (AMAT) Earnings Call Transcript & Summary

Hello, everyone, and welcome to today's master class. I'm Mike Sullivan, the Head of Investor Relations at Applied Materials. Back in our Investor Day in April, we talked about our idea of holding master classes to give you a deep dive on technology trends that are going to be very important to the semiconductor industry, but also very important to the growth of Applied Materials. We held our Memory Master Class in May, and that content is still available on the Investor page of our website. Today, we'll do logic. And then in the second half, we'll cover specialty semiconductors, heterogeneous design and advanced packaging and inspection and process control. And in fact, I have an update for you today. We've decided to hold our ICAPS and advanced packaging class on September 8 and that will be followed by our class on process control as well as our AIx platform technology on October 18. So we hope you'll join us for those events. Now what I'd like to do is just run you through today's agenda. So I'll talk to you in a moment about our logic thesis, and then I'll be joined here for a fireside chat with Chidi Chidambaram from Qualcomm. Then what we'll do is we'll hand things over to Uday Mitra, and he'll introduce the technical presenters, and we're going to have 3 technical presentations today: one on transistors; one on interconnects; and another on patterning, including something new called, DTCO. When we're done with that, Raman Achutharaman will be here again, and what he'll do is he'll summarize how the technology trends are going to be impacting our business in the years ahead. And when he's done, Uday and Raman and I will all be here and we'll take all of your questions today. So what are today's key messages? Well, I hope you'll take away 3 things: one, the AI era is driving secular growth in logic capacity. There's going to be a lot of spending; number two, where is that spending going to go? Our belief is that PPACt enablement with the new playbook is going to capture a growing proportion of the WFE market growth over the next several years; and number three, although the term's been around for a while, DTCO is getting a lot more attention today. And the reason why is DTCO is a great way to use materials engineering to drive continued growth in 2D scaling at existing line widths. And now what I'd like to do is remind you of our demand thesis. We believe that we are in the early stages of a transition. In years past, through the year 2018, we were an application-centric world where humans generated most of the data. That changed in 2018, there was a crossover. And now we're in the early part of a data-centric world where machines are generating most of the data. We think that by the year 2025, machines will generate 99% of the data in the world, and that's having a profound change on the semiconductor industry and also on all of the products downstream of us. In fact, what I'm showing you here is that we're seeing increasing amounts of silicon content being designed into all kinds of high-volume devices in order to enable this new data world, So for example, in high-end smartphones, between 2020 and 2025, we believe that silicon content is going up by over 60%. In automobiles, it's going up by more than 50%, and in servers, nearly 100%. And we all know around us, just looking at the world, there are shortages everywhere for components that go into these devices. And what does that mean? Well, one thing that's new, which we haven't seen in years past, is that the major customers are announcing strong multiyear capital investments in order to keep up with this demand. And what they're saying is that these are not speculative investments. These are investments they're making based on true demand that they see over the next several years. And it's not just the customers. In addition, what we're seeing are incentives being announced for domestic production by countries and regions around the world. You're seeing this in the U.S., the EU, South Korea, Japan, China. Everyone understands that having a healthy, vibrant economy today means having semiconductor supply. Now we don't believe that these investments will necessarily significantly raise wafer fab spending, but we do think it's a positive indicator. So what does this mean for Applied Materials? Now we certainly enjoy having these tailwinds at our back, but growing with the market is not our plan. What we laid out at the investor meeting was a plan to grow 50% faster than the market. And how do we do that? So our belief is that the PPACt playbook that we enable, more of the growth is going to come in these areas, and that's going to give us a chance to outgrow. And it'd be one thing if Applied was the only company talking about PPACt, but in fact, we're seeing lots of people in the industry talking about this playbook, talking about new themes like DTCO. So when you look at some of the conference proceedings recently, things like SPIE and ISSCC, you see our major customers and their customers all talking about new materials and structures, new architectures, new packaging, all of these things. So really, what you're seeing is the whole industry is beginning to converge and agree that, that is the path going forward. And that brings us to our fireside chat with Dr. Chidi Chidambaram, an IEEE fellow, who serves as Vice President of Engineering at Qualcomm, where he leads the company's process technology and foundry engineering team. Thank you for joining us today, Chidi.

It's my pleasure, Mike. Thank you.

Chidi, what trends are going to drive logic demand over, say, the next 3 to 10 years?

We at Qualcomm believe we are right in the midst of a fourth industrial revolution. The coming together of key technologies like 5G, AI-artificial intelligence, and IoT devices that are pervasive are going to enable a combination of user experience and customized demand that's near true industrial revolutions. So we are excited about the next decade.

Excellent. So next, how would you describe the state of traditional Moore's Law scaling? And although we're going to cover heterogeneous design and packaging in a future master class, what are your thoughts on those topics as well?

Yes. I think it's a pretty much industry-known secret that Moore's Law has been slowing. Clearly, if you look at the recent technologies from the foundries and IDMs, we don't get as much performance or power scaling from the new technologies. So we have to look for enabling the user experience through other means. And in that context, we look at the 2.5D and 3D integrations as real opportunities for us to engineer user experiences that are not coming from their traditional process technology itself.

I see. And Applied talks about enabling PPACt with "t" being time to market. How do you define and think about PPACt?

The PPACt is an acronym that the industry typically uses. It stands for performance, power, area, cost and time to market. We also use these benchmarks, but the one that I really like to think of as the "t" to stand for time to manufacture. Not really time to market because in the new technologies, particularly when the scale has gone up so much, we are shipping so many million units in the first couple of quarters of production in these technologies The time to manufacture is a pretty critical element. It's become much more significant even what the power, performance, and they may take some time to reach. But if you don't get enough of our production volumes in time, I think all of us pay a big price.

Okay. Thanks. So now let's dive into the technology a little bit, beginning with the transistor road map. How do you see FinFETs evolving? And then what comes after FinFET?

Yes. So in the last few generations, the power scaling has been accomplished by what's known as fin reduction, right? We went from -- 3 generations ago, 4 fin devices to 3 fin devices to 2 fin. And unfortunately, we can't scale beyond the 1 fin. So to accomplish the power reduction, we have to switch the architecture. And that's where I see like gate-all-around coming into play. It could be a sheet, people call it different names, but essentially, it is getting the gate on all 4 sides. So going from a planar to a fin, you put the gate on 3 sides and you got like 150 millivolt reduction. And when you go to gate-all-around, you get 1 more side. So going from 3 to 4 will give you not quite as much voltage reduction, but 50 millivolts or so. So we hope to catch in the power reduction from these architectures.

Okay. And then just a quick follow-up on that. About what time frame do you think we might see gate-all-around coming into the marketplace?

Yes. I think '24, '23 productions. Earliest could be '23, but '24 productions is reasonable, I think.

So we talked about the transistor, can you define what the transistor contact does and discuss some of the problems and maybe some of the solutions that you see in this area?

Yes. The contacts are really the elements that touch down into the silicon. They are the first things that contact the silicon. So everything that we can get out of is having to come through a contact. So they play a very significant role in making sure whatever the juice that silicon generates reaches the end user finally. And it's become a bigger challenge because the resistance of these contacts are limiting how much current we can get out of the silicon. And clearly, from ideology point of view, trying to find new materials and metals that can have lower resistances, and also try to thin the liner, that's kind of a barrier between the metal and the insulator that sits there, are 2 approaches that you can think of to get a better contact scaling going forward.

Okay. So we talked about transistors, contacts. Next, could you define what the interconnects are and talk about the innovations you think the industry needs with the interconnects?

Yes. Interconnects are like -- if silicon is the ground floor on a multi-story building, the interconnects are the remaining 15 floors of it. It's that large, and if you really laid out on a straight line, it can run into miles. So you can imagine how, as we thin these metal lines, the increase in the resistance is really going to affect your final performance, the frequency that you get and the thermal heating that these produce are all very, very significant. And in this context, I think backside power is a good interesting solution that's going to come in to help in the future. So we need to do all these things to get the resistances down.

Okay. Great. And we've been hearing about something called buried power rail or backside rail, can you describe what that is in a nutshell?

Right. So traditional chips, if you look at it, we put the contacts on the top, bumps on the top and power them through the top, and they go through all these many layers of metal and the contact to reach the final silicon where you are actually processing the signal. And in the process of taking the power from outside to the silicon, you lose a lot of voltage [ drop ]. Instead, if you can bring fat wires through the back and directly contact the silicon, you end up not losing so much voltage in accessing the silicon. And that's -- I think that's capable of giving at least 15% to 20% performance improvement. So it's a neat technology we are looking forward to.

Okay. And does it also reduce power as well as increased performance?

Right. It enables sudden shrink and lower capacitances. So therefore, you will see some dynamic power reduction as well.

And what about scaling, does that make the chip smaller? Or does it not affect that?

It will help scaling also because majority of the standard cell area is used up for power delivery itself. So if you can efficiently bring the power to the bottom of the cell, it will free up area to shrink the cell size itself.

Okay. So finally, how do you see patterning and scaling evolving? For example, at ISSCC, Dr. Mark Liu of TSMC said that with each advanced node, something called DTCO is playing a bigger and bigger role as compared to what he called intrinsic scaling. What are your thoughts about this?

Yes. The traditional scaling is kind of -- if you think of construction building and the scaffolding sitting right outside it, it has a rectangular X,Y grid. And if you just bring the Xs together and the Ys together and you scale the rectangle, and that's how traditional scaling or pitch scaling happens. But starting a few years ago, we cannot rely on just the pitch scaling itself because it was not resulting in a 7 -- 0.7X linear and 0.5X area scaling, so we had to do other things to achieve this end result. And those are collectively called as design technology co-optimizations. And this is actually -- this is very near and dear to me because in my IEEE Fellow citation, I was cited for DTCO as bringing those innovations to production. So that has become the larger fraction of what enables scaling going forward. Therefore, it's pretty significant that we leverage all the new ideas to explore those possibilities for upcoming technologies.

Great. So just a quick follow-up. So it sounds like the term DTCO has been around for quite a while, but it's getting a lot more attention now. Why is that happening?

Right. At the beginning, I said that the general offering from the process technology scaling itself has declined a little bit. And the main reason is the pitch scaling has slowed significantly. And since pitch scaling has slowed, we've started innovating on DTCO, and that's been going on for a couple of generations. But we are at a crossover point where the contribution from the pitch scaling is decreased in magnitude compared to what the DTCO can do. But even the DTCO today cannot achieve what it could 5 years ago. So in general, both are slowing, but today, the larger fraction is coming from DTCO.

Okay. Excellent. And then in closing, what's 1 idea that you'd especially like to impress on us today?

I think I talked a little bit about it. Manufacturability is a key idea that I would like the tool community and the foundry community to kind of partner together in achieving what we realized. Because to take innovation and create one-of-a-kind device is kind of easy and it's been done. And actually, a lot of places are working on that. But what we really need is how to -- when you make many tools and multiple process steps and a wafer that varies from center to edge, how to get all of it together. So when I ship my cell phone, every user gets the same battery life out of it all the time. That's really manufacturability, and that really needs the industry to come together.

Fantastic. Well, thank you so much, Chidi, for joining us today.

Thank you, Mike. I really appreciate it. I enjoyed the opportunity.

And now I'd like to turn it over to Dr. Uday Mitra to introduce the technical portion of the meeting.

Thank you, Chidi and Mike, and hello to everyone on the webcast. I'm Uday Mitra, Vice President of Technology Road Map and Strategies, and it's a great pleasure to introduce this technical part of the program. We certainly had an interesting time putting together the technical portion of the master class. Our goal is to help you understand the most meaningful and exciting inflections that are developing in the advanced logic road map over the next 3 to 5 years and beyond as shown on this slide. FinFET scaling for improving power and performance continues through materials engineering improvements in the channel, source drain and gate. The major inflection in the transistor road map though is gate-all-around, which is totally enabled by materials and processes and Applied Materials with our products, IMS strategies and deep customer engagements is extremely well positioned to benefit from this inflection. In a moment, you will meet Dr. Mike Chudzik, who is a Vice President of Technology and one of our top materials and device experts. Mike joined Applied 7 years ago and was at IBM for nearly 14 years before that. He'll talk about the transistor road map from FinFET scaling to gate-all-around. Apart from the transistors, there are also major changes in the back end as the interconnects are a critical scaling barrier for logic performance with a big challenge being via and contact resistance, driving the need for new ways of building devices, new materials and new processes such as selective metal fills and barriers. Addressing this will be Dr. Mehul Naik, who is a Managing Director and principal member of our technical staff. Mehul has been at Applied for 26 years and holds over 70 U.S. patents. He'll help you understand why the transistor contacts and interconnects need to scale along with the transistors and how we are going to enable that to happen. Finally, area reduction in a logic standard cell, which is essentially a group of transistors and interconnect structures that provide a Boolean logic function, today is no longer done solely by pitch scaling alone. In fact, over the nodes, DTCO, or design and materials technology co-optimization is playing a much more predominant role. Examples are, single diffusion break, contact overactive gate and in the future, buried or backside power rails. To talk about this as well as how material engineering is enabling traditional pitch scaling by enhancing EUV patterning as well as multi-patterning, I'd like to introduce Regina Freed, who is our Managing Director of Patterning Technology. Regina has been in the industry for more than 20 years, and today, she'll explain DTCO along with advanced patterning applications that enable customers to scale faster and reduce area and cost. After Raman's presentation later today, I look forward to joining Raman and Mike for the Q&A session. And now, Mike, it's time to begin the transistor session.

Thank you, Uday. My name is Mike Chudzik, I manage an integrated process module solutions group here at Applied. I'll now take you through the transistor challenges and road map as the industry continues to push the boundaries of power performance and area-cost scaling. The CPU is heart of the smartphone. It determines our user experience, and performance and battery life are paramount. So chip manufacturers are all pushing the boundaries of advanced transistor design and process technology. Drilling down into the process of the latest iPhone processor, we can see that it's based on the 5-nanometer node technology, with around 12 billion transistors and 24 billion transistor contacts. The flexible silicon design includes over 7 threshold voltages to enable both high-performance and long-life mobile computing. This 5-nanometer node technology is the culmination of a long string of process innovations that have occurred over many decades. We are now in the advanced FinFET era and looking to a new device architecture called gate-all-around. At Applied, we help enable these innovations with our leadership in equipment and process technology. Key innovations to enable the transistor road map include: epitaxy; ion implantation; metal gate formation; rapid thermal processing; chemical mechanical planarization or CMP; and a special kind of etch called selective materials removal. We can combine these leadership technologies to enable integrated material solutions where adjacent steps can be co-optimized for the best possible performance and power results. The transistor acts like a switch, and to enable the best performance, we focus primarily on reducing the switching delay. Minimizing delay is a function of maximizing drive current and reducing capacitance and resistance. In the FinFET transistor, speed can be optimized by tuning various physical parameters, including the fin height, the gate length of the channel, the mobility of the electrons that run through the channel, the threshold voltage used in switching and the thickness of the gate oxide that help control the on/off state of the switch. Typical node-to-node drive current increases are on the order of 20% to 30%. We reduce electrical resistance by implanting to achieve higher activated ion dopants. Another critical performance knob is design variability because performance is gated by the slowest transistors in a circuit. By tightening the distributions to reduce variability, we enable faster circuits. This is true even if the average speed of the transistor decreases. In this example, the red design is faster despite lower average speeds. As mentioned in the previous slide, the transistor's physical attributes determine its performance. FinFET construction can be broken down into 3 main modules: one, the channel and shallow trench isolation; two, the high-k metal gate module; and three, the transistor source drain resistance module. Listed beside these 3 modules are the key scaling levers that enable higher performance. In the channel module, we optimize channel isolation using taller and thinner fins. We optimize the channel for high mobility. In the high-k metal gate module, we optimize tunnel oxide scaling and tune the threshold voltages of the metal gate. In the transistor source drain resistance module, we optimize placement of the embedded source drain and tune the NMOS source drain using silicon arsenide layer. Now we'll talk about some of the challenging solutions to pushing FinFET designs even further. In the channel and shallow trench isolation module, we've been increasing fin height and reducing fin width over several technology nodes. These fins are becoming more fragile and tend to bend during the manufacturing process. Applied is mitigating the bending with new approaches in trench isolation and precision materials engineering of the oxides. Fins made with silicon germanium enable higher drive current, but are more susceptible to oxidation. Applied has solutions for this, including the silicon germanium epitaxy, nitridation and shallow trench isolation oxidation. We'll take a closer look at this. Taller and narrower fins are more susceptible to bending due to the strains caused by the isolation oxide that needs to be placed between the fins. This bending causes process variability and counteractive strain, which degrades the mobility and impacts the threshold voltages. Applied has developed co-optimized materials engineering solutions for fin bending that include flowable oxides, ion implantation and anneal steps, which are monitored using our PROVision eBeam metrology and inspection technology. We are able to mitigate this issue to improve the threshold voltage variability and increase the drive current upwards of 5%. Now we'll take a closer look at the high-k metal gate module, which is the heart of the transistor. These stacks are highly complex and can contain upwards of 7 layers. These include the interface, the high-k layer and the metal gate layers. Interface and high-k scaling is critical to the gate oxide reduction, which boosts the drive current. The metal gate is tuned to ensure that the transistor has the correct work function which determines the threshold voltage. We can see that since 14 nanometer, the interface layer and high-k haven't scaled at the same rate as the other physical parameters that lead to higher drive current. The physical dimensions of the interface layer at 8 angstroms the hafnium oxide at 15 angstroms illustrate how difficult this problem is to solve. Applied has a new approach that enables scaling to continue. We're combining process steps in vacuum to engineer interfaces and tune the process. This unique integration prevents the harmful exposure to the atmosphere, which creates moisture and prevent scaling. We've demonstrated a new integrated gate stack that enables an optimized interface and improves drive current by 8% to 10%. In fact, we're presenting this new technology at the VLSI conference this week. Designers can use this ability to tune threshold voltages over a greater range with a higher degree of accuracy to tune their chips for both high performance or mobile computing using a single process flow. There are 2 main ways to tune the threshold voltages using process technology. The first is thickness modulation, where the metal gate thickness' and materials are tuned using deposition and etch to provide specific work functions. The second is using dipole engineering, which uses dopants to change the work function of metals to tune the threshold voltages. This approach relies on ALD, anneals and selective etch. Applied is enabling the threshold voltage tuning with our leadership portfolio in ALD for work function metals, in-vacuum processing and anneals. The third major module we'll take a look at is the transistor source drain resistance module. The main contributors to the resistance inside the transistor is the interface resistance between the metal contact and the silicon transistor, and the external resistance of the source drain regions. Generational node scaling has reduced the contact area by roughly 25% per node. This reduced area drives up the resistance. The interfacial resistance is scaled by co-optimizing epitaxy, implant, metals and anneals. The external source-drain resistance is scaled using the sculpting of etches, epitaxy, implant and anneals. Applied is optimizing the external resistance with a new way to laterally etch beneath the spacers in a conformal fashion. This brings the embedded source-drain stressors closer to the channel to provide higher drive current. In addition to this conformal etch process, Applied has developed a novel selective silicon arsenide epitaxial layer. The silicon arsenide lowers the resistance and allows the silicon phosphorous stressor film to be deposited closer to the channel, which improves drive current up to 8%. The FinFET architecture is being pushed to the limit, narrowing the fins help produce shorter gates. Fin width is defined by traditional lithography and etch. Controlling the with is becoming harder and the variability and threshold voltages impacts performance. Gate-all-around gives the industry a new way to solve the fin width variability. We will transition away from using lithography and etch to define the fin width and instead use epitaxy, which enables very precise thickness control. In the gate-all-around approach, FinFETs are essentially turned sideways. The channels are formed with a superlattice of silicon and silicon germanium. The silicon germanium is eventually removed, leaving behind a stack of silicon channels. Let's take a closer look at the gate-all-around architecture to understand its value, construction and unique requirements. From a performance perspective, gate-all-around enables lower variability while enabling the gate length scaling, which increases drive current 10% to 15%, and reduces power consumption. As I mentioned, the process borrows heavily from the FinFET flow, but the channel is made with the superlattice of silicon and silicon germanium, and the silicon germanium is selectively removed at a later step to reveal the horizontal silicon channels. The key to well-formed channels are sharp interfaces and highly selective etches. Forming the embedded source drains requires better etch techniques and growth control. Gate-all-around devices require a new feature called an inner spacer, which is used to reduce capacitance. The spacer requires very controlled, selective etching and gap fill processes. The high-k metal gate wraps completely around the channel. Forming the uniform gate requires super-conformal interface, high-k and metal ALD processes. Additionally, we need new metrology steps to monitor and measure the formation of the superlattice. Now we'll take a closer look at that channel module. Two new process steps work in concert to create the well-formed slabs or channels. The process starts with a silicon and silicon germanium alternating superlattice that is deposited with epitaxy. The layer of thickness ends up defining the channel width. In the channel reveal process, quickly transitioning from the silicon germanium to pure silicon is critical to forming sharp channels. Applied has demonstrated the ability to transition greater than 30% germanium per nanometer of thickness. We have also developed a subsequent selective silicon germanium etch process, which reveals the silicon slabs or channels with selectivities greater than 500:1. Another unique module is used to form an inter spacer that isolates the high-k metal gate from the embedded source-drain spacers. The spacer is formed by slightly matching the silicon germanium inwards before the reveal process that I talked about, which allows for a low-case spacer to be deposited using ALD. Applied's leadership in selective etch enables this flow. Finally, the high-k metal gate module presents unique challenges due to the shape of the channel. Because the high-k metal gate wraps around 4 sides of the silicon channel, the interface, the high-k and metal gate needs to be conformal on all sides, particularly underneath the channels. Applied's technologies for these structures and the newly integrated solutions I talked about earlier provide highly conformal processes that evenly coat the undersides. We can see the uniformity of the elemental concentrations around the silicon channels. Thank you for your time today. And now I'll hand it over to Mehul to discuss the contact and interconnect modules.

Thank you, Mike. My name is a Mehul Naik, and I'm responsible for the logic module group in the semiconductor products team. To continue scaling logic, we need to do more than shrink the transistors. We also need major innovations in the transistor contact and chip interconnect modules. These will lower resistance and capacitance to maximize drive current, increase performance and reduce power. Today, we will review some of the key contact and interconnect scaling challenges the industry is facing, and how Applied Materials is helping solve that. Let me start by giving some context. As Mike showed, a leading-edge smartphone processor has over 12 billion transistors and over 24 billion via and contact connections. It also has over 15 layers of metals of varying dimensions with the ones closest to the transistor being the narrowest. So with all of this progress, why is there so much discussion in the industry about the scaling wall? Now when the transistor dimensions scale, the devices get faster. It's like having a free lunch. But this is not the case for metals. As dimensions scale, metal resistance increases and power performance scaling is negatively impacted. Left unchecked, this issue can offset the benefits of transistor improvements. Now the contacts that connect the transistor to the outside world also contribute to transistor resistance and influence the transistor's drive current. On the other hand, interconnects are the current-carrying lines that connect all of the individual devices within the chip. Since the interconnects route the signals and distribute the power, they control the RC delay or the speed of the circuit as well as the power consumption. Now as dimensions shrink, contact resistance increases by greater than a factor of 4. Because it can contribute as much as 10% to the transistor resistance, the contact also needs to be improved each node. The Interconnect is actually susceptible to a 10x increase in via resistance. Now since interconnects consume close to 1/3 of the device power and they account for more than 75% of the delay, so improving interconnect resistance is the best way to improve device performance. The key to improving contact and interconnect resistance is developing new metal fill processes that minimize or entirely eliminate high-resistivity liners and barriers. Thinning or eliminating the liner barriers reduces interface resistance and maximizes the volume available for the metal conductors. Now that we have worked through the fundamental ideas, let's look at the details in reducing contact resistance to improve drive current. Through the 10-nanometer node, the transistor contact and its middle-of-line via were filled with tungsten that was deposited with a liner that provided adhesion between the via and the insulating dielectric. If we try to use the same approach at 3-nanometer node, you would have a 4x increase in resistance and negate the benefits of transistor scaling. Applied delivered low-resistance contact engineering solutions, which has completely shifted resistance curve. We are able to maintain the 10-nanometer resistance characteristics at the 5-nanometer node. The 2x resistance reduction that was required was achieved by replacing tungsten with cobalt as the contact metal and by developing industry's first selective tungsten fill process for the middle-of-line via. We plan to further lower resistance by eliminating the liners that are needed for the contact metal fill. Now Applied was the first to market with a robust selective deposition process for metal fill. This new technique eliminates the need for volume-consuming liners and this enables scaling to continue. It also reduces via resistance by more than 40%. At the device level, something like this can reduce power consumption by close to 6%. Now this technique is integrated in an integrated material solutions platform where multiple surface preparation and deposition technologies are integrated in one system under high vacuum. Now let's discuss the interconnect performance. As we learned earlier, shrinking the dimension increases resistance, which in turn, increases signal delay and power consumption. Conceptually, we want to emulate the contact module improvements by eliminating high-resistivity interfaces and maximizing the metal volume. But the implementation is very different compared to what we saw in the contact area. One additional consideration in the interconnect module is that the low-k dielectric films that insulate the metal lines need to get stronger with scaling to eliminate patterning issues. So key focus here is in creating new low-k films with better mechanical properties. With that in mind, let's now look at a typical copper interconnect structure, which is composed of 3 different films: a tantalum nitride barrier, which is deposited between the conductor and the dielectric to maintain good addition; a cobalt liner that adheres to the tantalum nitride barrier; and facilities copper fill. Finally, copper is deposited into the remaining volume. So what is needed to further scale the interconnect? The issue here is the tantalum nitride copper interface, which is the highest resistivity interface, and this essentially controls the via resistance. So the best way to reduce via resistance would be to completely eliminate this interface, but this can only be accomplished by developing a selective barrier process. Another increasing challenge is filling this ever-smaller structures with copper. We would need an entirely new version of their existing copper reflow technology. Today, we are really excited to announce our new Endura Copper Barrier Seed IMS solution. This is an integrated material solution with new selective barrier and copper reflow technologies. This truly remarkable system combines advanced technologies from ALD, PVD, CVD, interface engineering, surface treatment, reflow and onboard metrology. All of this are integrated in vacuum. This solution reduces the via resistance by close to 50% and provides a path-to-scale copper to the 3-nanometer node. Now here is an animation that will run for about 1.5 minutes and demonstrate how this remarkable solution works.

Applied's integrated copper barrier seed solution on the proven Endura platform is the gold standard for interconnect metallization in logic and memory fabs today. We integrate multiple surface preparations, film deposition and metrology technologies on a single platform under vacuum. The process of filling copper interconnects begins with multi-chamber surface engineering. This preparation differentiates the materials and is key to achieving selective deposition. The surface preparation is followed by an atomic layer deposition or ALD process of a tantalum-based material that coats only the desired services. Integrated onboard metrology is used to measure the accuracy of the deposited thin films without breaking vacuum. ALD deposition is followed by a densification process that improves the film's barrier properties. A fin CVD cobalt liner encapsulates the copper wires, extending circuit life and enabling copper reflow. Finally, highly directional PVD deposits a thin layer of continuous copper. Our unique system enables coal deposition and high-temperature processing in the same chamber. In summary, we integrate 7 consecutive steps in one system under pristine vacuum conditions to achieve void-free interconnects that deliver world-class electrical performance.

Let's now look at how integrated material solutions are changing the way interconnects are built. In the past, we had lots of space to work with and could use conventional techniques like liners and barriers that provide good adhesion. The larger spaces were significantly easier to fill. As we transition to selective processes to enable scaling to continue, we need to carefully engineer the interfaces between the materials. We need to deploy new materials. We need to combine multiple technologies in vacuum to protect materials from the environment. And we need to prepare surfaces to make sure that they are pristine, so that selective processes work. It is now common for us to integrate 7 or more process steps, including surface preparation, CVD, PVD and ALD in a single system. On the right-hand side of the chart, you can see the results. With IMS, we have been able to significantly lower the resistance to scale dimensions, which match the resistance levels of the previous node. This is a huge PPACt improvement because each chip has over 1 billion vias per layer and at least 5 critical layers. Lowering the resistance in this way can have a huge impact on power consumption. Now let's talk about dielectric isolation. The dielectric constant of these films determine the capacitance of the circuit. Therefore, it impacts both RC delay and power consumption. Now we want to lower the dielectric constant to simultaneously increase performance and reduce power. A typical interconnect stack can have as many as 15 metal levels and 3 different dielectric films that can be used: an oxide with a dialectic constant of 4.0, may be used at the thicker upper levels; a porous film with a k value of 2.6 will be used in the intermediate levels; and a dense film with a k value of 3.0 may be used at the tightest and the lowest metal levels. A key challenge to continued scaling is improving the mechanical strength of the low-k film used at the tightest pitch, thereby avoiding patent collapse, and at the same time, making sure that the power consumption remains the same. Applied has developed a new generation of its Black Diamond family of CVD films that increases mechanical strength by 40% at the same dielectic constant. These new films are currently being proven at 3-nanometer node and are expected to extend to 2-nanometer node. Now to scale beyond 2-nanometer node, we may need major breakthroughs in interconnect design. First, let's talk about power delivery. Each logic chip is made up of standard cells, which are groups of transistors and interconnect structures that provide specific logical functions. Each cell needs space for the signal lines and a power rail. The power rail actually delivers power from an external power supply to the transistor, and this power rail is typically 3x larger than the smallest interconnect wire. Therefore, it's a major impediment to cell scaling. In addition, the power delivery network must be routed to connections at each of the metal levels of the chip, and this can easily be up to 12-plus metal levels. At each level, there will be a large drop in voltage caused by the resistance of the metal. Now designers can cope with a total voltage loss of about 10%. But the metal resistance is increasing as the node shrink. And it is projected that without a new architecture, the power distribution network would consume as much as 50% of the incoming supply voltage. So to enable scaling to continue, a new architecture is being proposed. The new buried power rail architecture moves the power rail into the backside of the silicon wafer beneath the transistors. This allows to transistor cell areas to be scaled up to 33%. It also allows the signal lines to remail larger and thus, have lower resistance. The buried power rail also eliminates the voltage drops that occur in the conventional routing schemes. Because of this, it is projected that the voltage drops can be reduced by as much as a factor of 7. Applied Materials plans to help drive this interconnect inflection with our expertise in metals, isolating dielectric, etch and CMP processes. In closing, the PPACt road map in logic needs concurrent innovations in transistors, contacts and interconnects. The conventional approaches are being pushed to the limit. But we already see new architectures that will be enabled by new materials and materials engineering techniques. Many of these are in the sweet spot of what Applied does in unit processes, in integrated solutions and with the help of eBeam metrology. I believe we will see tremendous improvements in PPACt spanning high-performance computing to ultra mobility. Thank you for joining us today. And now it's over to you, Regina.

Thank you, Mehul. My name is Regina Freed, and a Managing Director of Patterning Technology at Applied Materials. As you heard from Mehul and Mike, today's device features are already so small that as we scale them further to reduce area and cost, we risk negatively impacting power and performance. Applied Materials works closely with our customers to anticipate and understand these unwanted impacts, so we can develop new materials and material engineering solutions like the one shared by Mike and Mehul. In addition, we developed a new suite of materials and material shaping solutions that enable creative ways to simultaneously scale, area and cost while improving power and performance. Let's look at what determines the size of a logic device. Basically, a logic device is a set of individual logic cells. Each of these cells has several gates that are connected to one another by metal lines. In the vertical direction, we have the gates, which are separated from one another by the distance we call contacted gate pitch. In the horizontal direction, we have the metal wires that connect the gates to one another using a distance we call the metal pitch. By multiplying these 2 pitches together, we get a good measure of the area occupied by a single unit cell. Traditionally, the industry has focused on scaling the cells by making the gates and wires thinner and bringing them closer together. We call this pitch scaling or intrinsic scaling, and it has given us incredible gains in logic scaling. A new method is gaining our attention and will provide an increasing proportion of the scaling gains in the future. It's called design technology co-optimization, or DTCO. Since logic cell designs are relatively complicated and have many functions to perform, optimizing their layout opens up an additional degree of freedom for scaling. What if we could rearrange the elements without making them any smaller to reduce the overall footprint? A good analogy is building a house. When a lot size is limited, instead of shrinking the bedrooms to make space for an office as a game room, we can add a second story or a cellar. To do this, we need some engineering. We'll add supports for structural integrity, and we'll use excavating equipment to dig out the space for the cellar. DTCO is similar. We can move an element like a transistor contact from the side of device on top of the active area. This is called contact over active gate, and it allows us to scale the cell area without pitch scaling. We see an increasing set of opportunities to use DTCO concepts and material engineering to continue 2D scaling, and I'll give you some examples later on. But now let's shift gears and take a look at the opportunities and challenges facing intrinsic scaling today. EUV is already in production. And going forward, we can further shrink dimensions by combining EUV with multi-patterning techniques. Extremely small features can be patterned this way, if we can solve for EUV variability. I will explain. We want the edges of a feature to be straight and smooth, but in reality, there is roughness and nonuniformity at the edges of every feature. In the past, this wasn't a big concern because the features were much bigger than the edge roughness. But as we continue to scale with EUV, the features and the edge roughness are becoming more equivalent. There's a trade-off between litho resolution and line edge roughness, and we had nonuniformity where we increase the number of multi-patterning steps. The consequence is that variability is sharply increasing as a percentage of the feature sizes. This results in patterning defects. In some places, the width of the metal line becomes so small that we have a pinch off, which creates an open circuit. In other places, 2 neighboring lines can become wider than intended, and they merge into one another, creating a short circuit. Another name for this variation is stochastics. So when you hear us talking about stochastic defects, we're talking about the variations that result in these electrical opens and shorts. Fortunately, we can use material engineering to reduce these defects. Traditionally, spin-on dielectrics and furnace steps have been used to transfer the litho pattern into the device layer. We are replacing the spin-on dielectric with a high-quality CVD material that is co-optimized with our Sym3 etcher. We integrated the deposition technology into the etch chamber. We selectively deposit the thin CVD material on top of rough features, tuning the deposition to deposit more on wide openings and less on small openings. Thereby, correcting the difference between adjacent features. After the deposition, we use a specially tuned etch mode that etches small features faster than large features, once again reducing the differences. So by co-optimizing the CVD with our most advanced etch products, we can smooth the lines and eliminate many of the stochastic defects. In addition, we're taking advantage of our eBeam metrology capability. Optical defect inspection is at scanning entire wafers. But to find stochastic defects, we need to measure size variations on tiny features. Our eBeam technology has the resolution to measure this variation and is the fastest of its kind. Using smart sampling, we can get meaningful partnering insights on several wafers within an hour. In summary, because variability is becoming the key scaling limiter and causes roughness on the sidewalls as well as open and shorts, we have worked with our customers to optimize the patterning process for variability reduction. The result is a 50% reduction in local variation of the size of the features, which we call LCDU. A 30% reduction in LER, the roughness of the sidewall of a device feature and a very significant reduction in defects, enabling continued scaling with good device yield. Next, let's talk about EUV and multi-patterning. In the past, multi-patterning used extra layers of spin-on material films to compensate for poor etch selectivity, which rounded the spacers used in multi-patterning. By using the higher quality, conformal CVD films, we can create square spacers that do a better job of doubling the EUV patterns and producing straight features. DRAM customers are already using our new CVD material together with our Sym3 etcher to create better spacers and reduce variability. Now we are applying the same technology to multi-patterning and logic with EUV. Our EUV multi-patterning process reduces the number of patterning steps by 30%, and this helps to reduce patterning time, cost, variability and defects. Looking into the future, we will see a combination of intrinsic scaling and DTCO, with DTCO providing more of the incremental scaling benefit. I'll discuss one example called single diffusion break, already adopted in production, where 1 barrier is used instead of 2 to isolate individual transistors. Replacing a double diffusion break with a single break is an obvious way to reduce cell size. This is where material engineering comes in. At today's small scale, isolating transistors with a single feature is only possible using a special material with high-quality dielectric properties that can be deposited at high-aspect ratios with no seams and gaps. The size of the feature we will need to fill has an opening less than 1,000 of a diameter of a human hair. Applied has developed the Eterna CVD film and co-optimized it with our Reflexion LK CMP technology. This single diffusion break improves horizontal scaling by about 15%. Do you remember the buried power rail that Mehul discussed earlier, this is another great example of DTCO. Simple pitch scaling has a negative impact on the performance of metals, so we must reduce area and cost to scale. Material engineering will be the key to the road map, enabling our customers to improve power and performance while reducing area and cost. Moving the power rail from inside to logic cell to the silicon underneath enables 2D scaling of over 20%. In summary, advanced logic will continue to scale into the future, both using pitch scaling and DTCO. The contribution of DTCO to scaling is increasing. And material engineering techniques are going to be vital to making transistors, contacts and interconnects work at a smaller scale. Material engineering has evolved from a handful of material, blanket deposition and line-of-sight edging to conformal deposition and selective gapfill and etching. Applied Materials will make greater use of co-optimization, integrated material solutions and eBeam metrology and inspection to enable new devices and 3D structures. We're already working closely with our customers to accelerate the next several logic nodes and provide chip designers with simultaneous improvements in power, performance, area and cost. Now Raman, I'll hand it over to you.

Thank you, Regina, and thank you, Mike and Mehul. It's great to meet with you again in the second of our four-part master class series. I hope that after today's presentations, you recognize how materials engineering and the new playbook are becoming more important to enabling the road map for our customers. What I would like to do next is to help connect these technology trends to our business growth plan. As we showed at the investor meeting in April, we feel very good about the secular growth drivers in computing and semiconductors. In our base case, we see these drivers fueling equipment investments at 8% to 9% CAGR. Applied's opportunities are greater than this, and we believe our unique and broad capabilities will enable us to outgrow the market by around 50%. I hope these master classes are answering questions about how we can do this. As a quick reminder, we held our Memory Master Class on May 5. We describe how in 2020 through 2024, Applied can generate $1 billion in cumulative revenue from DRAM capacitor scaling, and how we can generate $2 million in cumulative revenue from DRAM periphery scaling. As Mike, Mehul and Regina described, similarly, we see large growth opportunities in foundry-logic as well. Let me start with a quick overview of the market. In the past 10 to 20 years on average, foundry logic spending has been over 55% of the equipment spending. So high exposure to foundry-logic spending is valuable. Enabling the foundry-logic road map with leadership technology and accelerating PPACt is even more valuable. We are already seeing this. As Gary said on our earnings call in May, "We're expecting CMP, epi, thermal and implant to all grow more than 50% this year." Over the past 10 years on average, specialty and trailing node foundry-logic has driven about 1/3 of the foundry-logic spending. We expect this ratio to hold going forward. There's a lot of business opportunity for Applied in those specialty nodes and markets. This is why, around 2 years ago, we formed the ICAPS business group focused on enabling our customers with our broad portfolio of technologies. As Dan said on the May earnings call, our revenue opportunity in ICAPS is already much greater than $3 billion this year. We will discuss the ICAPS business with you more in September. Another topic that's been gaining a lot of attention recently is advanced packaging. Companies are showing how new techniques, like hybrid bonding, allow silicon to be combined in new ways to simultaneously improve power performance area and cost. Applied has a key role to play in these efforts, and we will do over $800 million in revenue -- packaging revenue this year, which is up around 60% from last year. We'll also detail our packaging opportunity for you in September. And today, we focus on the other 2/3 of the foundry-logic market that come from investments in the 3 most advanced node, which today are 3-, 5- and 7-nanometer technologies. Foundry-logic spending is much higher today than it was just a few years ago. There are 2 big reasons for this: first, the new demand drivers associated with the big data and AI era. The data explosion is driving up silicon content in new and existing high-volume devices; second, technology is becoming more complicated. It takes more engineering to scale these devices for continued area-cost reduction, at the same time, to improve power and performance. Between 2016 and 2024, we see the number of process steps doubling, and the wafer fab equipment spending increased by 2.7x. Many of these new steps are materials engineering steps from Applied. This line of sight to new applications explains why we expect to outgrow the market. I'll highlight some of the specific growth opportunities from the presentations you saw earlier. Mike described to you the gate-all-around transistor inflection. It's great for PPAC, simultaneously improving power by 25% to 30% and performance by 10% to 15%. Much of this benefit depends on properly engineering the fin width. In FinFET, this is controlled by lithography and etch. In gate-all-around, it's defined by transitioning to epitaxy and selective materials removal. These are leadership businesses for Applied. We plan to co-optimize our technologies and deliver integrated material solutions for the gate-all-around inflection. We also plan to use eBeam metrology and inspection along with our applied AIx platform to give customers the actionable insights they need to bring gate-all-around to market faster. As compared to FinFET, GAA will provide an incremental TAM opportunity of $1 billion in our leadership areas for 100,000 wafer starts per month. In Mehul's presentation today, you learned how scaling the transistor is meaningless unless you can scale the contacts and interconnects with new materials and technologies. We officially introduced a new integrated material solution called the Endura Copper Barrier IMS system, which has new selective barrier deposition and reflow copper technologies. These are critical technologies that enable scaling to 3-nanometer and beyond. At the investor meeting, we showed you how our interconnect revenue opportunity is tripling from 20-nanometer to 3-nanometer. In fact, our interconnect opportunity grows by over 30% in the transition from 5 nanometer to 3 nanometer. Patterning has been a big growth opportunity for us in recent years. In 2012, our share in patterning process steps was in the single digits. Since then, we put a lot of R&D to work in developing new CVD films and our new Sym3 etch product, co-optimizing them and also improving our CMP products to accelerate patterning breakthroughs for our customers. Regina showed you some amazing technology where we co-optimize CVD and etch to fix EUV's stochastic errors and allows scaling to continue. We have great momentum in this area and have doubled our patterning revenue over the past 4 years. We expect to double again by 2024. Our cumulative patterning revenue opportunity over the next 4 years is greater than $3.5 billion. Regina also discussed how our eBeam metrology and inspection technologies are enabling these new patterning solutions to work. This is driving our process control revenue to grow over 50% this year, which is twice the growth we had last year and eBeam revenue will be around $900 million. I hope today's class helped you see why we have so much momentum and customer pull for our unique capabilities. We'll hold another master class in October to give you more insight into our applied AIx and process control technologies. Thank you for joining us today. We hope you are excited about the road map and can see the important role our materials engineering solutions will play in accelerating PPACt road map for our customers. Now Uday, Mike and I would like to address any of the questions you have about today's presentations. Mike, let's begin the Q&A.

Great. Thank you, Raman. Raman and Uday are both available to help with your questions about today's master class. There are 2 ways to ask a question today. [Operator Instructions] But if you'd rather have me read your question, please just send it using the Q&A button on your screen. If we run out of time to answer all of the write-in questions today, we'll be sure to follow up with you by e-mail. So assembling the roster. And our first question will come from C.J. Muse of Evercore.

Really appreciate the presentation. Lots of great detail that, of course, will take a long time, I think, to absorb. But I think 2 questions for you. The first one is, there's a lot of focus on '23 and beyond. So I think everyone feels comfortable at foundry-logic this year and obviously, next year as Intel kind of comes in. But as you look out beyond '22, how are you thinking about the demand drivers? So obviously, you talked today about rising complexity, that's going to play a role. There's leading versus trailing edge, that's going to play a role. You've got some uplift from regionalized spending. And then finally, just true end demand. Is there a way that you can kind of dig deeper into that and help us understand better what demand can look like in the out years?

Yes. So I think one thing we could do is I could start with just quickly. Our overall thesis is the data explosion thesis, right? And the growth of all the new devices that are coming on the edge, what that's doing in parallel in the cloud and then all of the silicon content that's growing in all kinds of devices, right, so smartphones, autos, servers. All of that content is going up. So that's the overall thesis that guides our view of the end markets. And what we have for wafer fab equipment as an expectation in 2024 is a base case of $85 billion, a high-end case of $100 billion. And a lot of that thinking went into place prior to governments getting involved and we believe that, that could be upside as well, but more in the latter part of the horizon, right? Not really beginning in 2022, maybe 2023 and beyond. But that's sort of the overall thesis. But I think what really guides are thinking the most is then what happens in terms of the capital intensity and then capital intensity in our served markets versus others. So I think I can hand it over to Raman to talk a little bit more about that.

I think like Mike said, right, if you just look at how the growth comes, I think what we talked about today, whether it is leading edge or trailing edge, there's broad-based growth in devices coming from the overall market exposure, whether it's data, AI, all the other pieces, right? And we've been looking at the intensity for the various devices. And I think, roughly over the last 20-year period, you look at logic to memory, what the spend is, it's still driven in almost 55% of the spend for the equipment is still logic-based. So we see strong end-market drivers. We see -- in terms of the logic spending coming in. And then within the logic spend, if you look at the leading edge, and that's what we covered a lot today for the next couple of years and going beyond is, the process complexity is releasing. Variability is becoming important. There's a lot of inflections which are playing into the market, right? So we look at end markets are strong. We look at complexity is strong, but we also look at broad-based growth. It's just not a leading edge, but it's also across all the devices we see based on the exposure of demand. So I think overall, where we look at how it's growing, what the devices are, I think we see growth in all the different segments we play in.

Very helpful. As a quick follow-up for -- specifically gate-all-around, Qualcomm suggested '23, '24 ramp. What's your view in sort of the inflection there for Applied? And then secondly, you talked about a number of steps, whether it's epi, selective removal, et cetera, that will benefit. Is there a way to kind of rank order 1, 2, 3, perhaps the biggest opportunities for Applied?

Yes. C.J., I can take that question. If you look at why gate-all-around is getting a lot of attention is because one of the important things as you start going to shrinking devices, going to the next node is the variability control. So as you start moving from FinFET, the variability is defined by what the CD and how we pattern. But the gate-all-around variability is now determined by the epi thickness, how we set, right? So that alone -- and I think there's been many publications by our customers on both power and performance gains in terms of 25% to 30% gains in power, 10% to 15% gain in performance. These are big numbers, and I think that's been a lot of attention coming. The exact timing? And I think it's going to depend on how the industry is going to adopt. So I think we are working with the customers. If you look at the opportunity, because it's materials engineering, you're looking at multilayer superlattice epi. How do you pattern this? And how do you actually tightly control? I think when we did estimate it, it's about $1 billion incremental opportunity for Applied. I think a lot of this is kind of equally spread out. Epitaxial deposition is a key step. How do you remove and selective removal becomes important. But also, how do you actually do some of the spacers and interlayer dielectrics, all of them become critical. So without really getting to the details, I think we see it's not just biased towards one of the particular applications. It's pretty broad-based, and I think that's what's pretty exciting for us.

If I can just add a little bit further. I think the gap between the nanosheets get pretty tight. So like how you do the metal gate, how you fill it, et cetera, how do you control the work functions, all those become very important. And we are playing a major role in that working closely with the customer.

Okay. Thanks, C.J., for those questions. And our next question is going to come from Stacy Rasgon with Bernstein Research.

I had a question on the leading edge versus the trailing edge forecast. So you laid out a lot of strong drivers for leading-edge equipment demand going from 7 to 5 to 3 and everything. But at the same time, you also seem to suggest that you thought the mix of equipment between leading edge and trailing would stay the same going forward, which suggests to me that you see similar drivers on the trailing edge as well. I was wondering if you could elucidate on some of those. Why do you think trailing edge can grow alongside a leading edge? What are the drivers there that make that go?

Thanks, Stacy. Thanks, Stacy, for the insightful the question. So if you look at the growth in devices, and I think, when you look at trailing edge device, there is a lot of variety of devices, whether you're looking from power electronics, you're looking at image sensors. So the variety of devices is a lot. Second thing is if you look at the demand from the end market, whether it's edge computing or how these devices are deployed, you're looking at a huge growth in volume of devices. So one is definitely the volume of devices coming in. Second thing is even in these trailing edge devices, there are some key inflections. This is why I think we want to get into more detail in one of the master classes coming forward on what we call ICAPS. So it's IoT, it's communications, it's auto, it's power, it's sensor. So again, I think it's really, really broad-based. And I think there are some things new we can do where we can really use materials engineering to enable some performance, right? So I think we'll get into the detail more, Stacy, in that particular master class. But a lot of those devices are actually -- the pitch is fixed. It's all depending on how to drive extra performance. How do you combine those devices along with memory or logic to drive more intelligence close to the edge or more capability for the customer. So we see there's an equal proportion of growth, both from volume and also complexity, that's why we kind of believe that, that [indiscernible] intensity will still stay the same. One other point I want to add also is the way we look at it is -- it's a 3-node average, so the -- what is trailing today as you start looking 3 years down the line. So the leading edge a few years ago has become trailing edge later, right? So you see a lot of the AI devices are still being run on FinFET. So some of the FinFET when gate-all-around is happening will be almost on the trailing edge. So that's where we see, I think, the overall cost efficiency, the volume, the complexity, the breadth of the devices all helps the trailing edge to continue growing.

I see, but it does sound like you don't think it's strictly a volume game. You do think that there's a capital-intensity story as well. I guess maybe because of that shift, today's leading edge becomes tomorrow's trailing. But you talked about a number of inflections as well. I don't know if you want to I don't want to steal your thunder versus the ICAPS session in a month or 2, but it does sound like [indiscernible]...

[indiscernible].

Just to clarify, it's not just volume. This is capital intensity.

Yes. No, I can just -- yes, it's not just volume, Stacy. I can just give you one example, and we'll cover more, right? If you'll just look at image sensor market. Yes, definitely, the number of image sensors are growing. So that's a volume story. But within the image sensor, you start looking at different, like adding on logic to the image sensors, looking at low-light performance, looking at dynamic shutter. There are a lot of other things which come in. And if you look at that market, it's like how do you do isolation so that you have the crosstalk within the pixels working. And if you start drilling deeper into this, what type of metallization you need, what type of etch you need. So you start getting into those devices. So definitely, there's a growth in complexity. There is a growth in combining things where you add packaging along with the sensors, along with logic put together. So definitely, there's a story of a system-level optimization happening in that market also.

Okay. Our next question is going to come from Pierre Ferragu with New Street Research.

I have one question on your competitive landscape and maybe one quick follow-up on the leading versus trailing edge debate. So on your technology, I'm always impressed by the systems you show us where you integrate different process steps around the single chamber, and you see the thing like growing every year, getting bigger and bigger and more complex. And I'm wondering with this thing. The first one is, are your competitors, your closest competitors, I would say, peers moving in the same direction? Do you see the same amount of integration happening at those other leading semi cap players? And then my second question is, what can you tell us about how your clients react to that? Because on one hand, I can see you're solving their problem. On the other hand, you're basically moving up the value chain. And so I can imagine at least some of them being worried about that and maybe being on the -- having maybe a preference, so being able to do that integration themselves versus leaving it up to you guys.

Yes. Pierre, let me answer the question here. Thanks for the questions. Let me start with the second question first. I'll come back to the first question. It fundamentally boils down to what value we are creating and what high-value problem you're trying to solve. So if you look at the example, like an interconnect, combining all those different technologies in 1 platform actually solves the real problem where, when the films are very thin, exposing the films to an air exposure actually damages the performance. So ultimately, I think having these systems, if they're able to drive value for our customers is where the customers' enthusiasm is high, and I think they want to adopt working. I think if you're just going to put things together just for the sake of putting, I don't think there is any value and that's something we don't want to pursue. We want to be able to add things which can really -- which can create value for our customers and in turn create value for us and move the industry forward. So all of our integrated systems are working on co-optimization is to be how can we speed up development for the customers, what can we do unique, and why should we do it. So there is a very rigorous approach we take on what we should put together and why we should put it together. And we work closely with our customers. And internally, we analyze that part, right? So that's been the motto for the company and how we work with customers on that. If I go to the first question, it depends on -- I think Applied has the benefit of having a broad portfolio of capabilities, not only from the process side, but also from the metrology side. So combining this unique capabilities and actually adding value has been our DNA for a long time. Definitely, I'm sure, as we add more value, I'm sure our peers are looking at what they can do. But fundamentally, I think we have had many, many years or decades of experience working on things like this. It's now that we are adding more and more things together to make things work. If you look at, 20 years ago, maybe we added 2 pieces and integrate them to work. Now we're having 7 or 8 of them working together, right? So having the breadth, having the unique knowledge of how the breadth creates the value, actually running a lot of these processes almost like a full-flow lab, which is a capability we have to really understand where we can differentiate, where we add value, it helps. And our innovation goes towards creating that capability. So I think combining the products in unique ways to see how we can differentiate has been one of the key focus for us and also combining unique ways to speed up the development for our customers.

And I have a very quick follow-up, if I may, on Stacy's very good question. If you look at the trailing edge versus leading edge today, it's basically pre-FinFET and post-FinFET. And so my question is, as we move towards like more advanced FinFET and gate-all-around, is there like the possibility that leading edge demand stays behind FinFET and doesn't move to FinFET? Just because FinFET, we know it is adding a lot of cost, adding a lot of design complexity. And that the demand for leading edge actually feels very good staying at the 28- or 20-nanometer node that is still planar. And in that case, maybe the case for increasing capital intensity on the leading edge might be less strong than the industry's kind of consensus -- than industry consensus is thinking now.

Yes. Good question. Let me just walk through a little bit of background, right? I think the way you're approaching that question, Pierre, is exactly right. So the way we think about it is there is basically based on technology inflection. You can think of pre-FinFET, you can think of pre-high-k. You can think of these devices based on major inflections. And there's an optimal cost for each of these big inflections. And the devices get optimized to the particular cost structure and the best yield and cost performance. And then on top of it, you start adding the unique variable -- unique inflections to enable, right? So If you look at image sensors, there's an optimal node. If you look at RF devices, there's not time node, right? If you look at logic, certain devices will be an optical -- an optimal node to work with. But if you look at what customers are doing, even on FinFET and others, there is these intermediate nodes, you can call internode or plus nodes, right? Customers are still adding capability and performance for the devices even when they're optimized to drive extra power performance benefits. So the way we -- I completely agree with you in the sense that there's -- the best cost economics will drive what is unique for the device, but the tendency has been to still improve the performance by adding what is unique. And typically, what is unique being added at all, typically, materials enable new materials or new performance-driven activity. And so if you look at the intensity, it's more biased towards the material side of cost intensity once you hit a particular node. And I think that's where I think we see our share of the intensity would be -- I think will be pretty good going forward on the trailing edge. Did I answer the questions, Pierre?

Yes, it does.

Okay. Thanks, Pierre. Okay. So next, we're going to go to the write-in section of the Q&A. And I have a question from Rob Sanders, who's an analyst based in Europe. And the question is, our view of lithography intensity as the industry goes from 3-nanometer FinFET to 2-nanometer and then gate-all-around, are there changes in litho intensity? And if we have any perspective on what customers are saying about the move to finer and finer types of litho?

So as you saw in the presentation, we see pitch scaling playing a smaller role there in the past. And I think also from Qualcomm, Dr. Chidambaram also said the similar thing. And this is kind of -- also supported by data presented by our customers. So another thing to note is that pitch scaling is not limited by fundamental patterning capability, which was the case when we went from like 7 to 5. But now it's more by -- limited by more fundamental materials challenges. For example, you saw in Dr. Mehul Naik's slides that the resistivity in the back end are really shooting up. So because of all of this, DTCO and power and performance scaling with materials and structural innovations, like gate-all-around and later on backside or buried power rail is becoming more and more important along with the use of integrated material solutions. So we saw that from 7 to 5 patterning was a limitation. EUV played a big role there, but now EUV is here, and it's really -- with DTCO becoming a larger fraction of the area scaling is really materials and structures which get there. So for example, in gate-all-around, as Raman mentioned a little bit earlier, the control of the channel thickness is made through epi and selective removal. And this gives a very good threshold voltage control on the devices, which is extremely key. If you contrast that in FinFET, vertical fins where the thin vertical fins was controlled mainly by [ leading ] edge. So this gives you an example of how the critical factor moves a little bit away from litho to things like structure and materials properties control.

I can just add one thing to it, right? I think I'd probably summarize what Uday said is, node to node, there is 1 key bottleneck or 1 key inflection that's got to be driven. So 7 to 5 was more of the patterning challenges to be driven. Then you go from 5 to 3, you're starting to look at more interconnect challenges, wiring resistance becomes really critical. You start looking down to 2, then you start looking at transistor becoming important. So you start looking at gate-all-around. Then once you solve that bottleneck, right, then you start looking at how do you do interconnect again with buried power rail and other inflection sides. So these inflections, if you look at it, it goes from patterning to interconnect to transistor back to interconnect. So it moves around that way. So I think it's fundamentally it's more important to look at what are the key things -- one thing opens up a challenge for something else to go work on. And I think that's how we have -- that's what the industry is approaching, and that's why we also see the same problem.

That's great. Okay. Thanks, you guys. So then the second write-in question that we have is a little bit related. It comes from [ Alan Patterson ], who's a journalist. And the question is just more far reaching, how far does the road map for planar scaling go? So you talked about nodes like 2 nanometers, gate-all-around. How far into the future you can see the scaling continuing?

Sure. Let me address that. So the scaling today is no longer kind of driven by the feature sides, but really by the power, performance, area and cost PPAC. And so scaling will continue for several generations. So you saw that FinFET has been extended for multiple generations. So gate-all-around comes in, well, there will be enhancements to gate-all-around, and that will continue. There'll be other DTCO enablers, like we talked about, buried or backside power rail, that will help. So all of these will enable the PPAC scaling to continue. The [indiscernible] may -- will defer after 2, it may be something else. But it's not really related to pitch or feature sizes so much as really getting the power performance and area, cost scaling. And this is done by really materials and structural innovations.

Okay. Thanks. So we're going to go back to the audio queue and Toshiya Hari from Goldman Sachs.

I had, I guess, 2 questions. My first one is on the Endura IMS. So sort of a follow-up. Just wanted you to clarify which applications in leading edge logic and foundry absolutely require this type of precision and performance at this point? And to the extent you have numbers around this, roughly what percentage of your logic and foundry business today are you delivering in the form of integrated solutions versus your traditional unit processing business?

Let me address the technical part, and perhaps Raman will go to the second part. And in terms of the -- if you see in Dr. Mehul Naik's presentation, he showed a system being used for a lot of the interconnects for the -- for example, the via resistance is a huge challenge. It would have gone up by 10x if it hadn't been for the solution. So it's clearly used for the back-end interconnect solutions, and there's multiple layers for those.

Uday said it right. With respect to how many products -- if you look at what we call some kind of integration, so we have many integrated systems or integrated products we have, roughly 40% of our products we sell today are -- have some form of integrated capability built into them. Some of them have a couple of different technologies integrated. Some of them have up to 7 level integrated. So just to build on what is critical from the -- what we are doing with this particular product. Endura is a key product platform for our metallization. And if you look at our metallization revenue for this year, we have said this in earnings call before, it's almost $3 billion for us or greater than $3 billion, right? So this is a key enabler for overall revenue, and this is an area where we have been leading for a while. And this particular product we talked about today is still in the early innings, and it's something we're looking forward for the next 3 years to grow. So anyway, just to summarize, 40% of our products have some form of integration and the complexity of integration depends on what application we go to.

And Toshiya, one thing we talked about is the number of steps, how much these steps are growing in the interconnect side, node to node. So it's pretty significant. And if you think about the comment that we made on the Q1 earnings call about PVD revenue being over $3 billion this year, the other thing you can note is that, it's roughly evenly split between front end of line, transistor formation and then the back end of line interconnects. And this new product is designed for the interconnect side. So it's a very large business on an annualized basis. This is a very new product. It's already being used by customers. But over the next handful of years, this is a product that will generate single-digit billions of dollars, this one product alone. So this is going to be one of Applied's real big hitter products.

And that's great. As a quick follow-up, I guess, how should we think about your profitability going forward as some of these initiatives continue to play out? My guess is, you're delivering value to your customers, but also you can kind of take advantage of these advancements that you're delivering. So I guess the hope is gross margins continue to grow in higher as integrated solutions continue to grow as a percentage of our business, how should we think about that?

Yes. I think, Toshiya, I think to answer the question, right? Profitability, definitely a focus on creating value for the customers. I mean as far as we're able to create value for the customers, it creates value for us. From the gross margin side, some of it is how we create value, and some of it is what we do internally within the company to manage how we execute. There's a lot of focus, and I think Dan covers in many of the earnings call all the focus we have on internally executing for margin. But anyway, going -- from the technical side is our focus is value creation. If we can create value for customers, that in turn, creates value for us, and I think that's how we look at it.

Great. Thanks, Toshiya. And then next, we have a write-in question from an analyst from JPMorgan named Harlan Sur. And the question is on DTCO, this approach. And the question that he has reminds me of what Chidi was talking about, which is how do we, as a company, make sure that we're addressing the manufacturability angle when these new DTCO-type schemes are put into the road map? I wonder if one of you guys have a comment on that.

Sure. I can take that. So DTCO, there are many ways of doing DTCO. So one example I'll give is gate-all-around, right, which is coming in shortly. And obviously, that's a huge enabler for the industry. It gives about 25% to 30% power reduction, 10% to 15% performance. And one example of how we are enabling that is, again, through the control, the epi superlattice. Controlling the thickness of that very precisely, right, really improves the manufacturability of the end devices. The threshold voltage control, one of our customers recently showed a few -- couple of weeks ago in the technology symposium improves by over 15% compared to FinFETs, so that's one angle. And the other thing we also do, as we work with the customers, not only on the process side, we are also working with them very closely on the metrology side. So again, in gate-all-around, things like buried defects are -- it's important to be able to see that and also eBeam technology PROVision that really enables us to do that. So that's just one example. There are many others how we are helping in the manufacturing area.

One more comment, Harlan. I think we talked about this before in our investor meeting on what we call the applied actionable insight accelerator platform. So DTCO, because we are combining multiple processes to build, it's almost a 3D kind of process. So variability becomes really important. So our focus is on actually combining unique metrologies, unique sensors, along with the machine learning, AI-type algorithm, to actually look at variability control and how to get better performance. So there's a lot of focus from an overall platform capability side of how we build this for any DTCO. And I think Uday explained one example of what we do with gate-all-around. But any of this is important. The other piece is really critical for DTCO is DTCO by nature, because you're trying to build on top on another, there's a lot more focus on selective processing. There's a lot of focus on gapfill technology. There's a lot of focus on new materials because you're trying to create these new structures where you need different selectivity. So a lot of this goes back into fundamental core capabilities on what materials and what technologies we can bring to bear. So partly, we get the process equipment capabilities correct. And partly, we connect them together using all the capabilities we have. And that's why we introduced this applied AIx platform and has the capability to bring to solve these kind of problems going forward.

Great. Okay. Thanks, you guys. Okay. So the next question on the caller line is from Krish Sankar with Cowen Securities.

I had a couple of questions. First is on the gate-all-around. It appears that the vertical epi, and kind of like controlling the lateral resistance is one of the more critical steps in gate-all-around. For that, what kind of throughputs are we talking about? And can ASM International compete on this? Or is vertical epi likely 100% market share opportunity for AMAT? And then I have a follow-up.

Yes. Krish, I'll take the question, right? So I think the fundamental thing for, like you said, and gate-all-around is how to get precise thickness and composition control. And I think our focus is on how we can enable this. And how we can actually co-optimize how we develop our deposition along with a selective removal process. And so we have lots of experience on selective removal for silicon and I think the extension of the technology. So I think we have a leadership product in epi. We have strong leadership in selective removal. I think we can combine them to optimize to get the best performance for our customers.

Just any comments on the competition there? Or is it mostly your opportunity on vertical epi?

I think the way we look at it, Krish, is I mean, at every node, there's definitely competition. I think we try to make our products much better in terms of the device performance and yield benefit, and that's what made us a leader in epi. And I think at every inflection, we're always competing with our peers, right? So we don't take it lightly, and we think we try to innovate and differentiate at every node. But I think the main point I want to bring across, the differentiation is just not on a unit product level. It's a question of can you combine the unit -- all the unit products and also with metrology like buried defects, what we can do with eBeam technique, can we understand how to optimize the deposition and the selective removal to get the best performance. So it's how do you co-optimize everything to make it work. But we don't take lightly the competition, and I think we compete on making our product better and that's what's making us lead so far.

Got it. And then just a quick follow-up and a clarification. The Endura Copper Barrier Seed IMS system, I was under the assumption that your regular Endura barrier seed has been there for a while that all the top 3 CapEx that have been using it. So is this more geared towards the non-top 3 customers? Or in other words, is IMS really more for the non-top 3 or even the top 3 CapEx spenders using IMS? And then a clarification, Raman, you said eBeam revenue around $900 million. Just want to make sure that is from 2020 to '24 time frame.

Yes. So let me take the first question first, Krish. With respect to the copper barrier seed, like you said, I think you know this very, very well that, that product has been there. The IMS is now -- there are a number of different capabilities we're adding on like selective ALD and in situ removal of certain things. So you can think of the next generation of the copper barrier seed, and it's not targeted towards -- it's targeted towards all customers, not towards the trailing edge or anybody. It's targeted at the leading edge and to all customers. So it's just the extension of technology and actually extending from just having 3 steps to actually having 7 steps and multiple different capabilities to drive the performance, right? So that's what the part of it. With respect to the revenue, again, the -- what we are looking at is between the '20 to '24 growth. We have strong momentum in the product we have. And we have very good penetration, especially in the logic side of the market, logic-foundry side of the market.

And Krish, I can add to that and is -- yes, we're going to have a -- we will do a master class in October, and we'll talk about our process control business and also our AIx platform, which Raman is actually one of our architects of. With respect to our eBeam business, it will be very large over a multiyear period. But this year alone, we're targeting e-beam technologies to provide $900 million in revenue for the company. So it's going to be a very, very large year for that technology. There are multiple applications that we have. We have our PROVision, which we use for massive metrology. We also have our review tools that are used, for example, in combination with our opticals. And then we have SEM as a product. So we have a number of e-beam products. But as a group, it's going to be a very, very large year and a record year for that business. Okay. Thank you, Krish. And then the next question is going to be a write-in question, and this comes from Mike Demler who is an analyst with the Linley Group. And Mike is interested in the gate-all-around technology and patterning. And the question is, will gate-all-around require EUV for the front end of line as discussed in the IBM 2-nanometer process paper? So I don't know if either of you guys would like to take a crack at that one.

Sure. I mean gate-all-around by itself doesn't require EUV by itself any more than like FinFET. So there's no -- it's not really in the critical part of the dimension control, as I mentioned earlier. The channel thickness is controlled by epi and selective removal, and that's very key. In terms of -- overall, when gate-all-around comes then and nodes progress, we also mentioned that the -- you'll see DTCO becoming more and more important and things like materials and new structures coming in.

Great. And then we have a question that is from an analyst named [ Dan Fletcher ] on the East Coast. And he's interested in the DTCO topic. And he's wondering, when the industry puts in place some of these new DTO (sic) [ DTCO ] co-optimization techniques, what is the sense or the importance of vendor cooperation to make all of that happen?

So I think -- I can take this question, Mike. We work very closely with our customers. There are many different DTCO approaches used by customers. And so like I mentioned before, DTCO typically are trying to build something in the third dimension to save space real estate, so that -- that needs a close collaboration on understanding their layouts, their challenges, which are unique and very customer specific. So there's extremely close collaboration, working really early on understanding the product statements to optimize the solutions needed for them. So that way, I think without the close collaboration, I think the industry cannot make progress.

Okay. Great. And then there was a write-in question from [ John Wynn ] and it's about basically the logic road map. Any comments -- you talked about FinFETs going to gate-all-around. Is there any discussion of anything beyond gate-all-around like into the future? If you really put your crystal ball out there, what do you see?

Sure. Mike, I'll take that. So if you look at from the transistor part of it, so gate-all-around will come in, and then there will be extensions of gate-all-around, just like FinFET was there for a few generations. So gate-all-around would be there, there could be enhancements to gate-all-around like something called forksheet, where you put material between an [ NP ] stacks of gate-all-around, and it allows you to scale further and it also gives a large power and performance improvement in some of our customers and other researchers that talked about it recently. So something like that could come in enabled by materials and structures. And then moving on, you've things like 2D channels [indiscernible] materials getting higher mobility, better performance. And also things like complementary FETs where you're stacking NFET and PFET on a 3D kind of way. So all of these are potentially we have in the future. So I think the road map is still pretty strong. There's a lot of enhancements and innovations in enabling power performance area and cost. Again, through very cool tricks with materials and new structures. And this is -- the trend is still similarly in the back-end interconnects. We talked about power rail, buried power rail or backside power rail. So I think innovations like that, all of these will allow the industry to continue on the road map. It's just going to be a little bit different than the old shrink type of road map, which is to be much earlier.

Okay. Thank you. So going back to the audio queue. We have a question on the line from Patrick Ho, who's with Stifel. All right. Okay. Not hearing Patrick, I'm going to move on to see if [ AJ Joshi ] is on the line.

As scaling is a continued challenge, a near-surface activation is becoming a bigger and bigger issue, and how to control it and how to measure it is becoming a bigger and bigger problem. I'm talking about like 2, 5, 10 nanometers in the surface of the semiconductor material. How do Applied Materials challenges -- metrology offering sort of face this fundamental electrical material challenge?

We are controlling the interface in many ways. You saw a couple of examples in this presentation where we are doing this integrated material system. One was in the back end. There was with the Endura Copper Barrier Seed, where we are actually giving some surface treatment, and then we do interface engineering followed by ALD step and then some metrology to measure. The other was -- example was in the controlling of the gate stack, having an integrated gate stack. So clearly, there's a lot of innovation in terms of how we prepare the surface and how we control that interface engineering. And then when we deposit the film after that, we use some innovative metrology to measure very precise thickness and the control of the material.

I have one thing to add. So we have a lot of internal capabilities to look at the surface properties or the characteristics. But we also have a very close partnership with a number of leading players, and we work with them to find the right solution to develop what the capabilities are. So internal and external, we find the best solutions to go after solving what is required.

Okay. Do we help you with your question, [ AJ ] -- was that...

Yes.

Okay. Great. All right. Thank you very much. Great. Okay, so the next question is a write-in question, and it's from Dan Hutchinson, who's with VLSI Research, and he's interested in the ion implantation. We didn't talk about it a lot today. But as we think about the road map going forward, are there new ion implant steps? And what -- how would you characterize those?

So ion implantation could be used in different things. For example, if there's a backside channel control problem, that's one area. For example, ion implant would be used. So it's essentially like everything else, the opportunity to actually get shipped instead of the traditional opportunities, you have some newer opportunities or different type of opportunities which come in.

Dan, I can add just one more comment to it, right? If we look at ion implantation, we think of 2 things: one is traditional ion implantation for doping; the second thing is just using ions for surface modification or precision retails engineering. So there is ways I think the ion implantation -- the techniques are getting used for more different applications. So -- and I think that's where the opportunities are growing in terms of number of steps.

Great. And then I'm going to try Patrick Ho's line one more time. Patrick, can you hear us at this time?

Can you hear me, Mike?

Yes.

Sorry about that. I understand the company better than technology. Maybe as a follow-up from an earlier question. Obviously, customers are very focused on the technology requirements. I see how your new integrated solution focuses on that. There's more process steps, and you talked about DTCO. But one thing your customers are also focused more and more on is the cost of ownership because of these increasing capital-intensity trends, the increase in cost of manufacturing. Maybe at a very big picture or high level, how much cost of ownership benefits do your integrated material solutions provide for customers?

Yes. Patrick, thanks for the question. Definitely, cost is -- and when you look at PPACt, C is an important piece of it. So it's a multiple -- multipronged approach for cost optimization. So there's normally a trade-off with respect to what performance and what you gain. And also, there is a tradeoff. If you look at the cost for the overall device, it's not per step. So the customers, we work with them very closely. And I think in terms of optimizing the overall cost for every -- not at every device. So -- and again, the cost depends on whether the application is really critical or it's semi-critical or it's noncritical. So I think there is -- whereas, the overall cost is optimized. And again, of course, it's traded off with what the benefits you're going to get. With respect to each of the solutions, we spent quite a bit of time in terms of optimizing the productivity and the output of the systems in terms of making it manufacturable. It's not only cost-wise, but it has to be manufacturable and reliable, right? So that's where I think a lot of our effort has been. That's been a lot of leadership on putting these multiple processes together and make them work day in and day out and be reliable. So I think there's multiple things happening, but the cost is just not a one-step solution. It a cost that's an overall aggregate solution. The last thing I want to add also is, by doing some of these integrated steps, you actually take some of the cost away because if you don't integrate them, you actually have other steps in the middle. So by actually integrating them, you do remove some of the costs. So it's not just on cost [indiscernible], you're actually are able to save cost to like -- there are other clean steps and prep steps that go on in the middle, which are actually you're able to take it off. And if you look at the next level of cost, the cycle time, if you're doing 7 steps and 7 different tools, there's a certain cycle time. If you do all 7 steps in the same tool, you could actually get a different cycle of time. So there is a turnaround time benefit. There is a number of steps reduction benefit. There's overall cost optimization. So there's a lot of industry learning how the customers work on optimizing and trading off the PPAC. So it's not a single step solution.

Okay. Thank you, Patrick. And then we have a couple of write-in questions that are business-oriented. So I wanted to make sure we get those on the table. So we have a question from [ Peter Law ]. And the question is, you talked about gate-all-around representing $1 billion of revenue for Applied Materials. And his take is that, that actually sounds low. So can we explain a little bit further the $1 billion?

Yes. I think, [ Peter ], I can answer the question. It's incremental opportunity. So typically, if our market share in the logic-foundry is roughly around 20%, if you look at $50 billion spend, that's about a $10 billion. And if you look at this, it's $1 billion on top. So it's about a 15% or 10% incremental opportunity we have. I think that's the way to look at the thing. So I just wanted to clarify, it's an incremental opportunity. It's not a total opportunity.

Super helpful. And then we have another business question from [ Nisha Subramanian ]. And the question is, if there's a way for us to characterize what our revenue opportunity is in epitaxy, perhaps these days, and then with the inflections that are going on and epitaxy growing, do we see that as a growth market? So is there any way you could put some numbers around that?

Okay. I can answer the question, [ Nisha ]. With respect to epi, epi is growing. So the number of epi steps are increasing from -- and also as we start going to -- from N5 to N3 or N2, the process complexity even within the epi and how you shape and form the real source drain is also changing. So the market area, if you look at -- this year, it's north of $1 billion for the epi market. And if you start looking at what happens when you start looking at gate-all-around, you're adding additional steps. You're adding channel epi and you're adding the superlattice epi. So that market tends to grow. So a number of steps are increasing. And also how the epi is done and what's needed to get the right dopant concentration and how do you optimize the process makes the process slower and also increase the overall market for us.

Okay. Great. And then we have more of a technology question here from [ Vijay Jian ]. The question is onboard metrology, so actually putting metrology in a system, what -- why are we doing this? And what are the tradeoffs between perhaps the higher costs of integrating that into systems and then the functionality that you get? So what are sort of the pros and cons of doing that?

It's a great question. Thanks, [ Vijay ], for asking. So a lot of these times when we're doing integrated processing, 2 challenges happen. A number of these layers are deposited in vacuum, and you can't measure these layers by taking them out. So the only way to measure them is in vacuum. And one of the examples we showed today, the interconnect, the layers are actually deposited and removed in vacuum, so which means they don't even exist to go and measure. So to control the processes, you need to go measure. So it's really critical. These measurements actually add value. They provide controllability. And we started to look at atomic-level precision on these films. It's important to be able to measure in vacuum, high precision, understanding what their films are. So because the films are becoming ultrathin and their exposure to air becomes a challenge, onboard metrology becomes a key enabler for the products to work in manufacturing.

Great. And then the back part of the question is, where are we in this evolution of using metrology inside systems? Is this something that is just a niche? Or is this something that's going to be growing? And if it's going to -- where are we sort of in the evolution of that?

Yes. So we think -- I mean, if you look at the trends, what's happening in technology, the films are getting thinner and thinner. Interface are becoming critical. As we start combining a lot of processes together in the same platform, we need to be able to measure and control them. So the trend is towards to have more and more capability. And as we look at more applications where the complexity is increasing, we see this trend going forward to be one of the key enablers for us.

Great. Okay. Super. So we have a new question on the caller line, and it's from Joe Quatrochi, who's with Wells Fargo.

I just had a quick follow-up on the EUV and gate-all-around. With the focus on more kind of innovative materials co-optimization, are we to read at -- you're saying that maybe the trajectory of EUV exposures maybe changes as we get the introduction of gate-all-around?

Yes. Joe, I think the way we think about the problem is, right, EUV is already here to stay and it's being used for patterning. So the industry, the patterning, the critical dimensions will continue. What we see as the enabler for gate-all-around will move more towards materials, right? So that's the way to think about the thing. It's not one goes off or the other. It's what has already happened. The industry continues to innovate and keep using what the capabilities are. Then you start moving towards what the next set of challenges are. So it's not 1 shifts from the other. It's already here. It's being used, it's being adopted. So it now shifts to a different time.

Okay. And Joe, did that fully answer your question?

Yes. It's perfect.

Okay. Great. All right, super. And our last question is a write-in question, and it comes from an analyst named Ben Richardson from Farallon. And he picked up on the Endura product launch today, which discussed ALD. But usually when people think about ALD and Applied Materials, they think about Olympia, which is a stand-alone tool. So how should we think about the Endura platform in ALD versus Olympia? If you could kind of explain how we have ALD in these 2 different places? And maybe talk a little bit about the importance or size to the extent that we can.

I think Endura is a platform used for metallization and it's more an integrated-type application. So we develop different capabilities to actually drive the solution. So a lot of the ALD capabilities they are using in Endura is towards integrated processes. Olympia is a platform we have more for a stand-alone application. So that's the way we think about it. There are stand-alone processes which need more semi-batch type applications, and we use the Olympia platform. And then where you really need high-precision grail control of processes, where you need single-wafer ALD, we kind of go towards the Endura platform to use it. So again, it's based on the segmentation of applications, what the value is and what works is how the products are being developed.

Great. And then our last question on the technical side is going to be about gate-all-around. And one of our analysts named [ Charles Chi ] is interested in being able to stack these channels and whether it might be possible at some point to stack NMOS gate-all-around on top of PMOS gate-all-around that kind of an architecture, is that feasible?

Right. So I think the industry is already moving to gate-all-around. And as I mentioned, and this has been kind of presented at some of the technical conferences, the first move would be go to something like a forksheet, where it is more of these things are put side-by-side, but compressed together, pertaining with some materials innovation which improves the isolation, right? And then later on, the industry incurred -- a few generations later moved to something called a complementary FETs where you could actually stack them one on top of other to get further density improvements. And again, there also the challenge would be how do you isolate it? How do you connect it? What are the interconnect challenges, contact challenges? A lot of materials and structural challenges to enable this kind of scaling and DTCO in the future.

Right, super. So what I'd like to do is to thank Mike Chudzik, Mehul Naik, Regina Freed, Chidi Chidambaram for all of their contributions to today's classes earlier. And with that, I would like to also thank Raman and Uday for your answers. That concludes today's Logic Master Class. Our next events are going to be our earnings call in August, followed by our Specialty Semiconductor and Advanced Packaging Master Class on September 8. And then we'll do process control along with our AIx platform strategy in October. So thank you to everybody for joining us, and we hope to see you again very soon.