Applied Materials, Inc. (AMAT) Earnings Call Transcript & Summary

Good morning. It's great to see you guys. And I think like Sundar said, I just love being here at Applied. It's really a great place to innovate. And today you're going to hear a lot from our panel about what innovation collaboration is all about. So they gave us a compelling story about what innovation is about. And what Sundar did has really set the stage for heterogeneous integration. And the equipment that we're doing at Applied, making at Applied, and how we're out there really enabling the industry. So this is a paradigm that will require collaboration, and we're going to dive deep when the panel comes up here. So before the introductions, I'd like to pay homage to Gordon Moore, who in 1965 predicted that heterogeneous integration would eventually be necessary to drive scaling. And now you see you have a great picture of what's going on. I'd like to start by inviting the panel up to the stage. From AMD, we have Mark Fuselier, Senior VP of Technology, Product Engineering. In addition to overseeing Product Engineering, Mark has responsibility for both silicon, package technology development at AMD and foundry relations. From Intel, we have Babak Sabi, key Senior Vice President of Assembly & Test Technology Development. And since 2009, he's been responsible for the company's packaging assembly, test process technology development. From Qualcomm, we have Chidi Chidambaram. He is VP of Engineering; and also a Qualcomm fellow, Chidi leads process technology engineering and foundry relations. He is also an IEEE fellow. From BE Semiconductor, also known as Besi, we have Richard Blickman, the CEO. So he founded Besi in 1993 and has been focused on delivering equipment to this industry for the past 30 years. He is also a fellow and actually Hall of Fame member of VLSI. Last but not least, from EV Group, we have Paul Lindner. He's the Executive Technology Director. Paul joined the company in 1988 and is a member of the senior leadership team, where he oversees R&D, process technology, quality and product development. Welcome panel, and thank you again for this great event we're going to be talking about today.

So let's start with Mark. So we have a question for you beginning with the early adoption of heterogeneous design and integration with chiplet-based products going back to 2017 with the Zen 2 EPYC server processor called Naples. Can you talk about why AMD has embraced this approach and what role it has placed -- played in enabling the road map?

Yes. Thank you, Vincent. And really a pleasure to be here and share the stage with the thought leaders on heterogenous integration. A very important topic for our industry. What I'll say is, for us, it's been a journey, and it's something that really spans over the last decade when we saw some of the challenges with scaling. And it started out really as looking at cost and how we could save by really disaggregating the SoC into pieces and then bringing it back together in a package. And that was really Zen in the data center, as you mentioned. But then as we started to get familiar with chiplet, we realize there's much more opportunity there. And so the second generation for us is really bringing memory much closer to logic. That was first done with HBM in the graphics space. But then more recently, as we introduced with 3D hybrid bond, bringing SRAM much closer to the CPU and -- through 3D stacking. And so that was really just a moment of change for us, an inflection point for us. But really, the third generation that we see is even more exciting. And that's where we can enable true heterogeneous integration. Really optimizing our chiplets for either CPU or GPU compute, bringing memory on board as well. It really becomes an architect's dream of being able to optimize for each workload in the compute space.

Thank you, Mark. So Qualcomm is one of the biggest consumers of both wafer fab and packaging service, driven primarily by high-performance mobile chipsets. Mark, as you described, how AMD is leveraging heterogeneous integration for client and data center. Chidi, can you talk about how this approach is being adopted in the mobile space?

Sure. First of all, I want to thank Gary and Applied Materials for spotlighting the hybrid integration as a key innovation that the industry needs to come together on. And as I'll describe the answer to Vincent's question, at Qualcomm, I've been there for 15 years, and every year we've released a cell phone. Cell phones, as you know, are super high-volume products that are very competitive at a consumer level in terms of cost and yield. And for us to continue to have a phone every 15 years, for the next 15 years, we need innovation beyond Moore's law, right? So on the graph here on the x-axis, I'm showing scaling as one of the components. And you can see the dots are getting sparser, right? 5 years ago, I knew that get all around would be the technology of 2022. But 5 years from now, I'm not sure what we're going to do. So this uncertainty is going to lead to sparseness in the nodes in the future. So we need to go to the vertical axis that I'm showing where I see integration and the throughput being a key vector as opposed to scaling. So as you move from scaling to throughput, we are kind of walking in the 2-dimensional space between the horizontal to the vertical. And that's really where I think innovation has to happen for us to continue to deliver the user experience that people have to come to expect from us. On the right, there's a bunch of charts on how we can get this integrated. So we are thinking a lot about it. We don't have a product yet because it doesn't meet our cost requirements. Hopefully, this event will help get the cost to the point where we're going to see cell phones doing this in the near future.

Chidi, just a follow-up. 6G and AI. How does heterogeneous integration enable that technology?

Yes. If you look at a system as a whole, right, you have a lot of RF and you have our management and you have memory. And when you look at how to get from 5G to 6G, you need a lot of the insertion losses and the power amplifier performances to come very close to the rest of the system chips. And heterogeneous, the integration is the key to bring all this together, right? So today, 5G already at a system level, the implementation is kind of going a little bit slow. But once these 5G and 6Gs are implemented, along with the AI, you're going to have a phenomenal acceptance in the kind of user experience that you can develop. Like if you look at a roadside intersection, once you have a fully implemented 6G and bring the latency down from the existing 7, 8 microseconds to 1 to 2 microseconds, you can have the intersection fully managed by the roadside unit and people don't even have to stop their car at the intersection. So those kind of features are possible, but it needs a lot of infrastructure implementation and adoption and delivering on the promise of all the latency requirements and commitments on the number of connections on our roadside unit. So lots of opportunities, but infrastructure and things have to happen.

Thank you, Chidi. So Intel is in a unique position with a business model that spans chip design, internal manufacturing and a growing external foundry of business. Babak, if you look at the approach from the manufacturing perspective, can you talk about some of the key technologies that are needed to continue progress in heterogeneous integration?

Thanks, Vincent, and thank you to Applied Management team, and also the colleagues here are with me on this panel. So Vincent asked me to look into the future where we're going to go. I mean what we'll see in the future is that we're going to bring in a lot of course together or call this, of course, Mark mentioned we have to bring memory there. And we want to bring all of this thing at the absolute lowest latency and the highest bandwidth. So we haven't -- from those of you who are engineers is that this interconnect problem. So packaging is all about interconnects. And you can think about interconnects as you stack chips on top of each other, which we would like to use hybrid bonding. It gives you really, really -- Sundar showed it earlier a graph that, that showed you how you can reduce picojoule per bit. So this is what I call the vertical interconnection. Then you want to connect the chips together, that's the lateral interconnect. And you want to make that as dense as possible, in order to be able to do that, then you're going to need some new innovation there beyond what we have in wafer-level assembly because we are talking with -- in the AI world. We're talking about huge complexes. People are talking about wafer-level integration of a whole product. So this is where I think the glass substrate is going to become extremely important, allowing us to put these huge complexes together, and you can completely eliminate the intervals at there and just go directly from your chips and connect them together. I know we all love copper. I know -- mentioned that Applied loves copper but eventually copper is going to run out of gas for high-speed communication. And we're going to have to move into what I call optical area. This is coming by the end of this decade, we're going to start seeing optical, and we're going to sit in many different formats here. Some of the things that we have been working on, and Vincent definitely wanted me to bring a sample with me to show this. So I did. You see the tangling fibers here on this chip. This is a real problem for those of us who work in manufacturing to deal with. So what we've done in Intel, we have developed a connector that you could put at the edge there, and you can just connect to it with like a USB-C connector there. So you don't have to deal with those fibers. We have demonstrated that already. And if you look a little bit further into future, what you're going to see is that you're going to replace your electrical mesh with an optical mesh where you do die-to-die communication using optics. That's going to bring a huge, a huge performance and power reduction into future. That's what I see in the future.

Thank you, Babak. I think I asked you to bring some glass panels. Next time. So we heard from Mark, and from Chidi, and from Babak, from the design side to manufacturing products. We're going to turn to the equipment folks here. So hybrid bonding is clearly a critical capability to enable the next generation of innovation in HI. On today's panel we have 2 equipment companies. We have Besi and we have EVG. Let's start with a question for Besi. Richard, while we have seen hybrid bonding rolled out in a few applications, many in the industry are wondering when will it be adopted on a larger scale? Can you talk about your view and the adoption curve and which applications will be driving this?

Well, we are -- how should I say, one of the bottlenecks in making all this happen. And before I answer your question, I want to thank also Gary, in particular, who has the view on how this should happen altogether in a partnership model. And I think that partnership and cooperation is the only way that we can really bring this technology to high-volume manufacturing. What is the issue? The issue is, of course, ever smaller design geometry. So the placement accuracy is becoming ever more critical. But then even more critical is the handshake between assembly, interconnect and the front end. So that step, we're in very early stages, in bringing the design of the end interconnect on chip level and how to connect that either chip on wafer or chip-on-tip. And you see in this graph, some cases we have projected for the coming years, the adoption rate of this hybrid bottoming. You heard also from one of the speakers that we are also in a very early stage of that adoption. But it works. In the last 2 years, we have demonstrated that there are designs, which are in high-volume markets today. So that is simply a proof of concept in high volume. But as with all these technologies simply compare when flip chip came to mainstream, and that was about 23 years ago. It took many years before that really took a major part of that market and simply ever smaller design geometries, challenge the existing technologies and we know one thing with hybrid bonding, it's a wonderful process. It's much easier than doing that with a reflow process at the same time. So that bodes very well for hybrid bonding. On the other hand, it has to be more accurate. Particles is one of the biggest enemies. So how to design equipment at the same time in ever smaller geometries. And then the next step easily said, let's put them all together in a chiplet architecture. Simply imagine how you place all these different dies in the accuracies required, which is now in the nanometer space. We are very proud that we can deliver machines for production with 200-nanometer accuracy. Glass on glass, even below that. And we have shipped now the first system with 100 nanometers. And in this back-end world, we were proud when we reached 3 microns and now even 1 micron, but then you have to go into the nano space. So there are many new challenges, which simply have an impact on how this will find its way into the mainstream. But as you've heard, the advantages are so numerous that it's not a question if it will happen, but it's more a question of timing. So that's in a broader sense, Vincent, answer to your wonderful question.

Thank you, Richard, and we value your partnership. So we've seen wafer-to-wafer hybrid bonding used in CMOS image sets for several years, and it also appears to be gaining momentum in 3D NAND. Paul, can you give us some insights into the applications and markets that are driving the adoption of wafer-to-wafer bonding?

Yes. First of all, thanks to the applied management team to enable this collaboration within the industry partners. That collaboration is required to -- especially wafer bonding is so dependent on the preparation of wafers, the CMP steps and some of the process that supplied is performing. So at EVG, we really view wafer bonding as a scaling booster. It's a possibility to transfer active layers from one wafer to another to gain access to the backside of wafers. And we were part of the adoption of wafer bonding from the back end to the front end in any device. And even with SOI wafers, those are bonded wafers. So cleanliness challenge, other challenges have been mastered on the wafer level bonding space. And the image sensor was the first device adopting the fusion bond initially for the so-called backside illuminated image sensor, which essentially gives access to the backside of the photodiodes. So they are not obstructed by the wiring and gives a greater sensitivity of the sensor. And then later on, the hybrid bond has been adopted to integrate memory or logic. So going forward, we also see in the market already 3D NAND flash, adopting wafer bonding, the hybrid bonding process, particularly. And we expect if by size is small, if the dies are similar and redundancy can be designed into the dies that wafer bonding can be adopted for more memory applications going forward.

Thank you, Paul, and we also value your partnership. So we're going to turn to the next set of questions with the panelists, a little open-ended. So we spoke about the markets and applications. I want to get your views on the technical challenges as well. So let's start on this question with both Babak and Mark. Since we're on the topic of hybrid bonding, let me ask the panel, what is new and unique about hybrid bonding compared to other advanced packaging technologies? What technical and manufacturing challenges do we need to overcome to accelerate adoption and bring the capability to high volume? Mark, perhaps you can address it from the design side, and Babak from the manufacturing and development side.

Yes, sure, Vincent. The amazing thing about hybrid bond is really the density that it enables. And so on the design side, it really drives a lot of choices that you have to make in terms of how you leverage that density. And it becomes an optimization point for the architecture, not just at the chip level, but at a system level. And so you really have to, as an architect, figure out how you're going to leverage that density to manage some of the challenges you have, whether that be logic-to-logic, interconnect, logic-to-memory. And so that really, from a tool set perspective, there's a lot of innovation that needs to happen to really develop the tool set to drive that interconnect. We have a lot of those tools in the fab space today. But on the packaging side, there's a lot that needs to be done to really allow a more seamless process in terms of how we make decisions and using hybrid bond interconnect.

Thank you, Mark.

From manufacturing side, I mean, this is sort of interesting. It looks like the fab board is coming to assembly since some of the packaging guide. Other fab people think that assembly is going to them. It doesn't matter how you think about it. This collaboration between the 2 is almost essential. I mean we see it between the [ CNA map ] with the hybrid bond tool that they're developing. And this is the kind of collaboration that it's really needed to make a technology like hybrid bonding, which really crosses the fab and assembly boundaries very, very closely. There are lots of challenges. The density of the interconnects are massive. So we need extreme particle control to be able to make that happen. The CMP process has to be pristine. So you could make these millions of bonds happen across the whole wafer. So there is a lot of challenges ahead here. An area that I'd like everybody to look at is under metrology tools. We've got to be able to find the problems, so we can fix them. And that's why we need really good, fast affordable, let me emphasize on that, metrology tools to be able to find the problems so we can go fix them. So these are some of the challenges that we're going to see here.

Thank you, Mark and Babak. Chidi, it's clear that hybrid bonding blurs aligns between traditional front-end wafer processing and back-end assembly and test, which calls for more co-optimization. What needs to be done differently across the ecosystem to enable this new level of integration and collaboration? What is the role of the equipment companies, chip manufacturers and the chip designers?

Yes. So this question is really about system-level integration, right? So if you take a large company, like Qualcomm, when you talk about a system within the company itself, the guys that's working on a hard macro, let's say, a CPU and another person working on a radio frequency, don't know each other's areas that well, right? And here, we are talking about co-optimizing all these things coming together. So really the tools and the language that people talk to across these different fields has to enable that possibility. And that's a big challenge if you think about it. Our interconnect today is -- when we do a hybrid integration at 3D level, what you're talking about is really creating a back-end type of integration. To do that, you need all the physics to come in to solve the problem. You need to have the electrical behavior of the multiple chips that are integrated to be solved. At the same time, you move 1 block from the top to the bottom, it's going to change your thermal behavior, it's going to change your mechanical behavior, and you need to simultaneously co-optimize all these things. And that type of tool capability is something we really have to invest to develop. Today, they all exist in bits and pieces. You can solve some specific problems and do it in a sequential way. But we need a complete co-optimizable solution pretty soon.

Thank you, Chidi. So Babak, Paul and Chidi as well, so we heard Richard and Paul talk about some of the differences between wafer-to-wafer and ideal way for hybrid bonding. Are the manufacturing challenges similar across the 2 approaches? Are there unique problems that need to be solved for each? So maybe we can start with Babak on your views about that.

Yes. The challenges are somewhat different, but the underlying physics of the bond is the same. In some cases, there are some aspects of wafer-to-wafer bonding since we can use a lot of wafer-related tools, mixed life a lot easier. However, you have to deal with the extreme edges of the wafer. So there are other kind of challenges there. And I believe that the 2 technologies will coexist for many, many years to come because I think they're complementary. It's not one at the expense of the other one. And I can see, as an example, an application of wanting to put decoupling capacitor on the backside of your processors. You will use the wafer-to-wafer connection to add these capacitors that -- it's probably the most efficient way of doing it rather than doing it one diet a time kind of thing. So I think there are lots of good applications coming up.

Great. Thanks, Babak. Paul, you seem to be nodding about that. Can you give us your insights as well?

Yes, I agree. It's complementary technologies and in some process flows, even the combination of both. If you think about layers of chiplets that are stacked and that can be synced collectively, it also offers a path towards thinner and thinner packages. So the scaling in the CX is that does not -- is not restricted by the die thickness that can be handled individually. So definitely the coolest device going forward this one that uses die bonding and wafer bonding.