ASML Holding N.V. (ASML) Earnings Call Transcript & Summary

Welcome, everyone, to ASML's 2024 Investor Day. I am Skip Miller, Vice President of Investor Relations at ASML. Thank you, everyone that made the journey over here to our headquarters in Veldhoven, and good morning, good afternoon, good evening for all those joined via webcast. It's been about 6 months since we made the leadership transition. The handover went well. The team is happy today to welcome you all and give you an update and discuss our long-term strategy and the market opportunity we see ahead of us. Before we go into the details on the agenda of the day, I'd like to start with a few logistics. First, if you look at the -- from a safety perspective, the exits you go up here, here, and you can see we can go outside on the different locations, clear the aisles, please make sure you don't have stuff in the way should there need to be an exit. Secondly, please put all your phone on silent or airplane mode. The restrooms are located if you go outside here or here up on the top right, my right, your left. Presentations today will be posted on our website shortly after the event. And the in-person Q&A will have both a combination of questions, obviously, from the audience, but also online. And so we will take both of those after the presentations are complete. For those that are online, if you look at the -- you should see on a screen like you see here, which is basically you type in your question and submit, we'll receive those on our end and then we will try to take as many as possible during the Q&A session later today. For the agenda, first off, we'll start off with our President and CEO, Christophe Fouquet. He'll talk about the industry and the technology road map as well as ESG. Next, Amit Harchandani. He'll talk -- Senior Vice President, sorry, and Head of Corporate Marketing. Some of you may know him. He will talk about the end markets and how this translates into wafer demand and also some on litho spending. Next, we'll go to Peter Vanoppen, Executive Vice President and Head of Business line EUV 0.55 NA or also known as High-NA. He'll give us an update on the EUV products as well as business opportunities. Next, we'll go to Herman Boom, who is the Executive Vice President and Head of Business line deep UV. He'll provide an update on the deep UV products as well as the business opportunities. We'll then go to a short break after Herman. We ask you to all please to be back at the schedule where you can see, we'll start our next presentation with Marco at 3:30 p.m. We will go on the webcast here, so we'll try to keep it, as I said, very close to schedule. So please don't -- be efficient of coming in and out after the break. After the break, we'll go to Marco Pieters, Executive Vice President and Head of what we call our business line applications. He will give you an update on the holistic lithography solutions and the business opportunity there. And finally, Roger, our President and CFO of -- sorry, Executive Vice President and CFO. He will give you an update on all this, bring all this together with our business model and our capital allocation strategy. Finally, we'll wrap it all up with closing remarks from both Christophe and Roger summarizing the day. We'll then go into a Q&A, where we'll have all of our presenters come up here. We're, again, taking questions both from the audience as well as from the webcast. We'll try to intersperse both of those. We'll end the program formally at 5:30. And then for those that are still here in person, we'll give you an update on what's planned between 5:30 and 8:00 p.m. tonight, which will finish with drinks and dinner and the opportunity to network with a lot of the ASML's management team. Before we begin, I'd need to remind everyone that comments made by management during this event will include forward-looking statements within the meaning of the federal securities laws. These forward-looking statements involve risks and uncertainties. For a discussion of the risk factors, I'd encourage you to review the safe harbor statement contained in today's press release and presentations which were posted on our website at asml.com. Before we begin and before Christophe comes up, I'd like to do a quick video with a little bit of AI fun embedded in here, bring up the energy level and it's generated by AI. A lot of fun here, but we'll kick it all off, and we'll come back and introduce Christophe. Thank you. [Presentation]

So now I'd like to bring up Christophe Fouquet, our President and CEO. Christophe?

Thank you very much, Skip. Thank you. Hello, everyone. So as you can see, AI has got very, very exciting but it's still not good enough. So we still have to show up in person here to talk to you today, but we are very happy to do so. And I'd like to thank all of you for joining us here or virtually. It's really a pleasure to have you here. And we are, to be honest, very, very excited to have the opportunity to talk with you for the next few hours about the future, the future of the market, the future of technology, the future of ASML. And the ASML teams have been working very hard in the last few weeks to bring you our latest view. And from where we stand, the future of each one of those things is extremely bright and extremely strong. And we're going to try to share that with you. So we're going to talk about a few things today. The first thing we're going to talk about the market. We could make it short where we're talking about a $1 trillion market in 2022. We're going to talk about the $1 trillion market today. So you could say, well, it's all of the same. Well, not exactly because AI has come around and what you will see when I and Amit present is that if the size of the market is the same, the mix of the market is going to be quite different with a much stronger presence of advanced logic and DRAM. And we believe that this is a very good shift for ASML. We will talk a lot about technology, sorry, but welcome to ASML. But we will talk a lot about technology because this industry needs innovation. For AI to deliver on its promise, we need major, major innovation. We need major step on cost. We need major step on energy consumption. And we believe that our portfolio is going to basically help our customers to deliver on those needs. We'll talk about EUV extendability, the progress of High-NA. We'll talk about how holistic lithography can once again help us help our customers basically to tackle those new challenges. On top of technology, we will also talk about many, many things we are doing to improve our product with our customers. We're going to talk about quality. We're going to talk about flexibility. We are going to talk about time to market, all those things that are still very, very important, basically, to get what our customers need. We will, of course, also reconfirm our view for 2030. So a few weeks ago, we had a bit of, I would say, a more, I would say, conservative view for 2025. In many ways, this is related to the change of the market we're going to talk about, this big transformation that AI is driving, but when it looks -- when it comes to 2030, we are still very, very bullish. I think you have seen that this morning in the press release, and Roger give you again the fundamental that explains why we believe that 2030 is still a very, very positive year for us. So this is a lot of topics. I'm going to start with global market trends, the road map of the industry and ASML and a few words on ESG. If we look at the big picture, the semiconductor industry remains very, very strong. We talked about that in 2022. What is new is that AI is going to boost this industry even further. And we see that happening today. There's major investment being done in AI and the rest of the industry is getting ready, basically, to also release the different application to insert AI basically everywhere. As I said before, the industry will require major innovation to address the need to improve cost and energy consumption on AI. And this will require to further boost the industry road map. Logic, DRAM will see major transformation in order to be able basically to deliver on those needs. And this will result in a product risk, which is more towards DRAM, more towards advanced logic, which is once again very beneficial for our customers and for ASML. Our customer, they will remain at the core of ASML strategy. And we believe that lithography will remain at the heart of their innovation. If you need more advanced process, I will explain the lithography today is still the best way to drive cost down and to drive energy consumption down. So lithography remains important. I know some of you had doubts about the weight of lithography moving forward, we'll explain to you today that this weight not only will remain strong, but will continue to grow. And the focus on logic, advanced logic, on DRAM is going to be a very good opportunity for us. When it comes to product, we will talk about the extendability of EUV. We can scale EUV for many, many, many years. We have been spending years to get EUV to work. You know that. You remember that, as some of you're smiling. Now the good news is we have it. The technology is getting more mature and we will be able basically to use this technology for many, many, many years. And this will offer our customer a way to really drive costs down, energy consumption down. Holistic Lithography is still key. The scanner today is still the only tool in a fab that can be used to correct process. So not only we produce chips by providing lithography, but we use our scanner to improve all the rest of the process. And this will be very, very important as customers shift also towards 3D integration in front end in order to increase transistor density further. And finally, on deep UV, Herman is going to explain that this is one of the workhorse of the industry. We continue to improve on all products, in productivity, in quality, and this will also allow us basically to address a very large set of needs from our customers. On top of that, as you may have noticed, our installed base is growing. We are talking now about thousands of systems, which means that the opportunity for service, the opportunity for upgrades is growing as well. And that part of the business is more and more a customer. And as a result, it's going to be a part of what we are going to do. I think Roger will explain that very nicely in number later on. Finally, ESG. This has been an important topic. We have been working very hard with our partners in the last few years so that this industry with all its partners, all it peers could basically lead the way, I would say, on ESG. We have made huge progress. We continue to make huge progress. We're working very closely with our customer, with our suppliers in order to make sure that we achieve the commitments we have made to the entire world a few years ago. So this is a bit the key talking point. I told you that the customer is at the core of our strategy. You are all aware of how successful SK hynix have been this year, last year, most probably will be next year because they were one of the first DRAM customer moving into high bandwidth memory, one of the first one to basically sense this AI opportunity. And we are very happy that [ Dr. Cha ], who is the CTO of SK hynix, so one of the masterminds behind the success of SK hynix has agreed to make a short video for you. There will be 2 parts. In this part, he will talk about partnership, what the relationship with ASML means. And later on, I will bring him back to talk a bit more about technology.

[Foreign Language]

So one of the best reward can get in ASML is when our customers tell us that we have helped them to be successful and that they are counting on us basically to maybe be successful further looking at the next generation of technology. So this, for us, I would say, is as good as it can get. And we're very happy again that [ Dr. Cha ] was willing to share all of that with you. Let me go back to the market now. So this is a slide, in fact, we showed you in 2022. And we showed you this slide to explain you, as you know already, that if we look forward, any major innovation we will see will be based on semiconductor. This was a story in 2022. That's still true, and semiconductor is going to be used everywhere. But on top of that, AI over time will be added everywhere. And today, most probably, as we talked in the past about semiconductor everywhere, we will be talking about semiconductor and AI everywhere. And this is, of course, the biggest change we have seen in the market in the last 2 years. This will have a huge opportunity on the total GDP. Amit is going to talk about that. But this is also going to basically require the entire market to be connected. About 4% of the semi business will be around AI in 2030. The rest will still be about mainstream semiconductor. The semiconductor basically that will generate the data sensor, for example, in order to feed AI. So AI is built basically on the existing ecosystem and what we will see moving forward is basically a combination of both AI and mainstream semiconductor really driving this market. And as you know, our portfolio has been, for many, many years, addressing both. If we look at the number, this is about what we see. There's a lot of debate, I know about the size of the market in 2030. But for discussion today, we take $1 trillion, which is still about the mid-range of many experts. You could decide that there is an upside. We won't even fight you on that. But then you can scale whatever we are going to tell you to whatever market number you have in your mind. But for all discussions we look at today, we look about $1 trillion. And like I said before, you will see that if the number doesn't change, the mix itself is going to change quite a bit. Now the other very important thing about this market, it's also a slide you have seen before, is that it remains a very, very profitable market, EUR 865 billion EBIT, the [indiscernible] EBIT in 2023. And 2023 was a bit of a downturn year. So this is a lot of profitability and a lot of money that can be reinvested for innovation and we continue to see very strong investment from the entire ecosystem to do more, to innovate. About 1/3 of EBIT before R&D is being reinvested to innovate. I think we don't know any other industry that does that. And this means, if you look at 2024, more than $500 billion of R&D will be spent to create the next innovation. And this has been true for many, many years, this is -- when we look at this graph, we believe that, well, we don't know exactly what will come in 5 years from now and 10 years from now but this is a guarantee that something else is in the preparation. Now let me go to our customer, Moore's law, many, many discussions about Moore's law. Everyone likes to take its own version of Moore's law. So this is my favorite one. That's showing basically that the number of transistor continue to double per package. So we don't talk about per chips. We talk per package now every 2 years. This is still very much true. This has not slowed down. In fact, what's happening is that, of course, this number of transistor is going to provide computing power. What happened in parallel to that with Moore's Law is that customer, our customers have been basically also driving the energy down, right? So they've been driving transistor density up 2x every 2 years, energy down 60% every 2 years. This was a good way basically to, for example, drive the road map on mobile. So this is still true. Well, if I look at AI, in fact, this is, in fact, accelerating. What you see happening with AI is that the demand now for computing power is increasing a lot faster. And the slots you're looking at is not a 2x every 2 years. It's a 16x every 2 years. So it's 8x faster than Moore's law. This is what people who are working on supercomputers, who are going to on training model really wants to get. And the problem with that is that energy cannot keep up. Energy as a result is not decreasing anymore per generation. It's increasing also a factor of 5 every 2 years. And those 2 things, of course, are showing the challenge of AI. There was a reason why Moore's law was important. It was important because it was putting cost in control and it was putting energy consumption in control. So that control is a bit off. Now I'll take an example to illustrate that. So let's focus first on the number of -- on the computing power. So that you can get. This is a kind of a supercomputer you have been seeing in the last few months. So if you want to get more power to compute, you just put more chips together. And for a few company in the ecosystem, this is great news because they are going to sell a lot of CPUs and a lot of GPUs. So getting the power to compute is possible. The first challenge is here, yes, you need a lot of CPUs, more than 20,000, a lot of GPUs, more than 60,000 a lot of memory. And the cost of these things today is $0.5 trillion, which is okay, if you are investing to develop your model and most of the company can do that. You have seen it, thanks to the ecosystem EBIT. But this is, of course, a bit of a problem on the long term to be able to transfer AI to all devices. So that's problem number one. And problem number two is energy consumption. A supercomputer like that is going to require 60 megawatts. And that computer, you see it is only allowing customers to train basically a number of parameters, and this number of parameters is going up very quickly. So the graph you see on the right is a graph I took from Lisa Su. She presented that at ITF back in May. And she said, "Well, if we keep going basically on training more and more parameters at some point of time, we will need a nuclear power plant in order to feed those supercomputer." So that's a bit of a challenge. What does it mean? Well, it means, again, we can get the power, computing power, just put more chips together, great news for the industry, at least in the short term. Cost will be an issue. Power consumption would be an issue. How did we solve that in the past? Well, we go back to Moore's Law. And this is the logic road map. This is a slide from [ my Mac ] that have been, I would say, shown many, many time. Still the same. What it says is if we look at advanced logics, there is a path. There is a path basically to create architecture that will be more performance and with less appetite for energy. So that's possible. A few years ago, customer who were working on advanced logic, were not even sure they will need a 2-nanometer node. They used to tell us, why do we need it? What are we going to do with 2-nanometer? Who can afford it? What are the applications that are going to run on that? That's only 3, 4 years ago. And there was then a risk that this whole road map will slow down because if you don't have the need for it, there's no need to drive it. If you hear the story today around the AI with our foundries risk customer, AI customers are extremely eager to get 2-nanometer chips. And they will be equally extremely eager in the future to get 14 Angstrom chips. Why is that? Because that's the only way to really address cost and power consumption. So what I'm trying to say is that AI will again, demand an acceleration of the road map. That's something we like in ASML, of course, because this is creating opportunity for also more performance tool in lithography. So that's the story for logic. What's happening with memory, with DRAM is also very, very interesting. So you're all aware of high-bandwidth memory. Why did people suddenly get very eager to buy a lot of high-bandwidth memory? It's simple. It's because today, memory, DRAM is the bottleneck of AI because the structure of DRAM is such that only 30%, 40% of the bits are going to be really used basically for computing. Therefore, a need to change the architecture. HBM is the first step. What we believe will happen moving forward is processing in memory. What does it mean? It means that memory will see more and more logic coming together with the DRA. And that logic is going to be used to improve performance, to improve speed and to reduce power consumption. So we also expect a major shift on the DRAM road map. I think Amit will come back to that. This is mostly the market that will be the most affected in a positive way by AI. So that means practically that when we look at bit growth, which has always been a driver for ASML, when it comes to logic, when it comes to DRAM, very aggressive growth moving forward. And there, again, you see with the [ protocol ], there's a lot of debate depending on your belief of AI. Our belief is that when it comes to logic, especially advanced logic, we will see an acceleration, same when it comes to DRAM. Now this brings me to us. So if we go one more step in the food chain, I talked a bit about the customer. Now we have to talk about wafer processing. And as you know, wafer processing is a combination of many, many processes. You need lithography, of course. You need edge, you need deposition. You need all kind of process. This has been true yesterday. This is still true today. And for our customer to drive cost and emission -- total emission down, they will also have to optimize this process. So they want to make sure that any chips they produce is going to be at the lowest cost and the lowest possible emission. And then [ coming with ] holistic lithography, if you look at the best way to reduce cost, to reduce emission, there's 3 things. First, you need to make sure that the yield is the highest possible, right? Every transistor you produce, you want the transistor to work. That's a good way to do that. Second, you need to simplify the process flow as much as possible. [ Dr. Cha ] was talking about our EUVs being used for HBM, using EUV on HBM allow a DRAM customer to skip more than 100 process steps, which is a lot. When a total number of process steps for DRAM is about 700 to 750. So it's a big deal. You gain in cost, of course, you gain in emission and you even gain on cycle time. And the last one is to make sure that for every step you're going to take, you try to reduce cost and you try to reduce emission. So that's simple. And that's what basically all our customers are asking us to do. Now if you look at ASML, this is what we have been doing for many, many years. We had KrF, then we had ArF, then we had immersion, then we had lower NA EUV and high-NA EUV and 1 day, most probably hyper NA. Why do we do all of that? We do all of that to provide our customer with more good transistor at a lower cost. This is also as simple as that. That's the value of ASML providing the ability to create a lot more transistor at higher speed, lower cost. And we have been quite successful over time, going from 1 generation of tool to the other. If I look basically at the overall curve, you see that this has been quite a significant trend. Now you could think this is easy, right? But when it comes to lithography, we have many, many different things we can do to achieve that. Before I go there, if I look at this value. So I told you the key for us is to provide more good transistor at the lowest possible litho cost. If we look at EUV alone, and we're going to talk about that with Peter later on. There's many things we can do to achieve that. First one is high NA. High NA will provide 150% more transistor per exposure. 50% -- the 150%. So it's almost 3x basically the number of transistor. Second, for every EUV technology, low NA or high NA, we will be able through productivity improvement, through efficiency improvement to lower the cost of the exposure of EUV by 30% by 2030. And here, I said again, when I say we're going to lower the cost of exposure on EUV by 30%, it doesn't mean that we are going to give 30% more discount to our customer, right? It doesn't mean that we are going to draw our gross margin down. It doesn't mean we are going to drive our contribution margin down. Roger is like, no, no, no. Now what it means really is that we are going to use the R&D team we have in place to innovate, to innovate on cost, to innovate on all the parameters that allow us to do that. And I will come back to that later on. The good news is we can do that. So that's something you want to do is one thing, but being able to do it is very important, and the EUV technology today gives us this opportunity. And finally, when it comes to environmental cost emission, EUV will also be able to cut the emission by 50% by 2030. So here, you can look at it 2 ways. You could look at it from the ESG angle, which is a good way to look at it. But you can also look at it from the cost angle because emission is cost. And it's a matter of time where this industry will have to really pay real dollar in order to deal with that. So this is what EUV can do. And if I broaden a bit this value equation to our entire portfolio, and the team will come back to that. There are many, many, many different axis we can drive in ASML in order to get more transistor at lower cost. I talked about yield. This is going to be Marco presentation with holistic lithography, resolution, low NA, high NA, hyper NA, accuracy, which sometimes we call overlay or eP express material at ASML, productivity, of course, very, very important. And when it comes to cost, where are you seeing the system cost. That's something that we work extremely hard on to make sure that every machine is cheaper. Lifetime, our system, I think Herman is going to talk about it, especially with deep UV. We intend every system to last with our customer for more than 20 years. That's also true for EUV, by the way. right? Also, we started to ship those to only 5 years. We are already working to make sure that they will last in the last 20 years, it's good for our customer, and it's very good for our service and upgrade business. Operational cost and environmental costs. So we're going to work basically on all those axis in order to drive the value to our customer. Now let me go back for a second to our customer, and we will introduce a bit now what is needing moving forward?

[Foreign Language]

So as [ Dr. Cha ] said, there's quite some work moving forward, and I'll come back to that, especially it comes to DRAM. But if I look first at the big picture, the industry. So this is the road map, pitch dimension for logic. What you see here? Yes, shrink has slowed down. I think this has been the case for many, many years, but shrink is still happening, meaning that neither logic customer or DRAM customers have given up, sorry, on shrinking. They will shrink as we have nothing to stop them from doing that. And what it means, if we look at our customer road map, the best way to shrink using a simple process is to use more EUV layers. And when it comes to advanced logic, when it comes to DRAM, we still see a significant increase, node and node year after year of EUV in both advanced logic and DRAM. So here, we look at the 2025, 2030 horizon. So we will have a pretty good understanding of what customers are going to do. And if we translate that in spend, and both Amit and Roger will come back to that, you look at 10%, 20% for logic and even more 15% to 25% for DRAM. One of the reasons for that is what [ Dr. Cha ] was explaining. He told you in the video, well, with EUV, I can still reduce the amount of multi-patterning layer. Why is that? So when it comes to multi-patterning, there's a lot of different patterning schemes. And we picked 3 on this slide. So these are the blue line here. And what you see here is the cost of patterning over time. The blue line is multi-patterning. The purple line is EUV. EUV, we know how to take the cost down. It's a lot harder with multi-patterning because immersion tool, Herman will show you, are a bit limited when it comes to productivity because of the water between the lens and the wafer. If we move too fast, we break meniscus, and we get defect. So we are limited physically in how fast we can go with immersion. And all the other process tools edge, deposition also struggle to get better productivity, better cost. So we see basically a bit of upward trend for multi-patterning. Cost of EUV is going down. That's one the reason why in 2019, EUV was adopted to replace a lot of multi-patterning. But as we continue to go down, we see more opportunity, especially with the DRAM to convert more layer from multi-patterning to single exposed. So this will be happening in the next few years. And if you go a bit more into the detail of those use cases, at equal cost single-exposed multi-patterning, single exposed makes more sense because it's simpler, it's faster, et cetera, et cetera. And what you see here is that for every of those use cases, we will be able to shift a large part of the patterning cost from non-litho to litho. So this is for us a way to build up more EUV layers, but I will say, to build up also a much higher litho intensity. So this is something we will continue to see. This is the reason why basically we built EUV in the first place. And then come high NA, why do we have high NA? We have high NA because what's happened with deep UV immersion in the past is about to happen again with low NA EUV, meaning that at some point of time, you need to do multi-patterning on low NA, more complex, more expensive, et cetera, et cetera. Therefore, high NA opportunity is happening now. And this is why Peter would show that. We have many, many customers evaluating the technology today in the lab, meaning they come here even before they get a tool because they are impatient to find out how much high NA can help. And we have a few good first example of why high NA could help. This is logic. Free mask could become one with about 35% cost reduction. This is quite a bit. This is a situation we will see around what we call 14A or A14 node. What's also important that you may not know is that high NA single exposed give back a lot more flexibility to the designer. If you use multi-patterning, designer can only use vertical and horizontal line to create their pattern. If you use single exposed high NA, you can use whatever you want. So you have like a thin brush that allow you to design whatever you want. And this is something your customer are going also to start to look at because they see that EUV high NA is working. So this is, of course, the next trend. And over time, some of those low NA layers. So whenever we're talking about low NA, or 0.33 NA equivalent exposure. So we still look at the exposure for low NA, but some of those exposure will move to high NA and we will see the number of high NA layer going up. Around 2030, we believe we'll be somewhere between [ 4 and 6 ] in average at advanced logic customer, [ 2 to 3 ] on DRAM customer. And of course, as we move forward, those numbers would continue to grow because this is a bit story repeating itself as we saw it with low NA. Now the other very important thing about high NA, the other very good news is that we have now a new optic technology. We could say who cares, right? We have already optic technology. But the new optic we have developed with high NA can be, in the future, also used for Low NA and can be also in the future used, sorry, for hyper NA. And that technology will allow us to reduce the number of mirrors on our low NA tool. Every mirror cost us productivity. If we take out 1 mirror, we get back 40% light. If we take another one, we get another 40% light. So this new optic allow us to envision a road map for EUV, which will boost productivity for many, many years. And we have plan if we look all the way to the end of the next decade, mostly to take EUV technology towards 500 wafer per hour, again, because we can. And this is thanks to the high NA optic we have developed. So maybe you missed that part when we walked on high NA, but the intention was to get both the high NA tool, but also an entire road map basically that we can use moving forward. So this one is one important part of the road map. The other important part is the source. So we have struggled many, many years to get to 200 watts. Today, our tools use about 500 watts. We have demonstrated 700 watts, and we know how to go beyond kilowatt. We have a good idea on how to do that. There's a short video here. So we always like to brag a bit about our EUV technology in ASML, but I wanted to share that just to show you again the uniqueness of the technology. So what you see here is a [ team of ] droplets -- is a droplet -- [indiscernible] droplet, sorry. So you remember, we use 60,000 of those droplet every scan, right? So this movie itself is a fraction of a second, right? It's 1 second divided by 60,000. And what you see happening here is you see the droplet that is being hit not once, not twice, but it's being hit 3 times by a laser. So the first 2 time is to make it as large and gaseous as possible. The third time basically is to get the power out. This is years of work. And this is why when it comes to EUV, we feel pretty good also that it will be quite some work for anyone to be able to repeat this technology. So has 1 engineer in the room. Well, that's very, very important. And I think this is a bit of a visual of why we are also so bullish on the EUV road map. Now if I translate that into the road map, simplify it a bit. So this is what you have today. Low NA, high NA to platform, 2 different optics, 1 source. Moving forward, we will be able to increase the system commonality from 50% today, which is already good, by the way, to more than 90% and the reason for that is that we'd be using pretty much a platform that is very similar for all tools. We'll use the exact same source and the idea that the only thing that we have to change is the optic. So that will be used for Low-NA that will be used for high NA and if we need it 1 day also for hyper NA. And if we need it, 1 day is also very important because I will show you later on, most really the time for hyper NA will come. We're still debating when 2032, '33, '35. It depends a lot on our customer. But when it comes, if we had to develop a platform from scratch, this will be too expensive. If we have the platform and we just have to put a new optic, then we have the flexibility to do it any time at a very reasonable cost. So this is also enabling that step. So hyper NA to maybe finish on that part of the story. So this is the timing. So I told you shrink slowdown, most probably hyper NA will be useful around the introduction of CFET with advanced logic because CFET will basically increase the interconnect density dramatically. We don't know exactly when we need it. To be honest, we are very relaxed about that because we're preparing the platform. We continue to work with our customer and when they need it and when the business case makes sense, we will move. So what we have it, if you want, in the back pocket. We're ready for it and that's the way we'd like to provide also the flexibility to our customer. So this is the 2D part. Now one thing we see happening also when it comes to transistor density, is more and more 3D integration. So if you can put less transistor per unit area 2D, you're going to try to stack them. We see that happening everywhere. And if we look at 3D NAND, if we look at DRAM, if we look at logic, one thing we have seen happening over time to enable that is wafer bonding. And we believe that wafer bonding will be everywhere. But there also, and I will explain to you later, taking example of DRAM caused has to make sense because remember, it's not only about getting more density, it's about getting it at the lowest possible cost. But wafer bonding is going to happen everywhere. And we believe that this is a place where we can help. We believe, again, it's a significant opportunity for ASML. Marco will go a bit more into the detail of that because this is becoming important for us but the key is when you do bonding, you take 2 wafer, for example in this case, RA, CMOS, and you bring them together. The problem is when you bring them together, you create a major, major deformation on the resulting wafer, which is a bit the picture you see there with all the color. This shows if you want the deformation of the wafer. And this deformation is, of course, not good for the chips. So it has to be taken away. You cannot take it away when you bond because it happened when you bond. So the only thing you can do is either prepare the wafer before or expose the wafer after bonding in such a way that you remove the fingerprint. And that's something that holistic lithography can do. Why? Because we measure the wafer, we describe the deformation. And because, as we have explained to you in the past, our system is the only tool in the fab that can provide major, major correction. We show you this slide, the first time in 2014, 10 years ago. Back then, we had about 20, 40 parameters we could play per exposure. Today, we have 100,000 parameters. Meaning that every time we expose a dye on a wafer, we can change 100 parameters in order to do it the right way. And this is, again, very powerful when it comes to deal with also bonding pre, post-bonding processes. So holistic lithography and Marco will talk about in the details, is very, very critical for those applications. Now I want to finish my technology part by talking a bit about DRAM. I wanted to talk about DRAM because when it comes to DRAM, everyone talk to you like they knew exactly what's going to happen with DRAM. A lot of things will happen with DRAM. No one knows exactly what, right? The only thing we know is that the 6F2 structure that have been used for many years, most probably cannot be extended forever. That everyone agree. Then there's already a debate on when the next structure, which could be vertical transistor, also called 4F2 would happen. And depending on the customer, they are more or less aggressive to implement it. It will also depend on how quickly they can validate it. So what we see right now is a bit of a mix at our customer between 6F2. I think you heard [ Dr. Cha ] saying he wants to extend that as far as he can and vertical transistor. But I think there's also a consensus that most of the vertical transition will happen as well. And over time, we will look at 3D integration because if you cannot again put enough transistor on 1 wafer, you will start to stack them. But there also a lot of discussion about how this could be down. And if you look at how it could be done, I think there is most probably 2 main paths. The first one at the bottom is creating 3D array, which is sometimes called 3D DRAM, but you could also create more density by just stacking 2D array as we do them today 4F2 or 6F2 over time. This is also something we see happening. So stacking array wafer to get more density is something, for example, NAND customers are going to use moving forward. So these are basically most probably the 2 options. And how will this be decided? Well, it's going to be decided based on the Y axis that you see on this graph, and this Y axis is of course, cost because DRAM customers have been driving density at lower cost. They have never been driving density at higher cost. And this is the curve we see with 2D array, most probably extending all the way to 2031, '32. That's also a consensus right now. Then there is discussion about potentially introducing a 3D array. There's been some data proving that this is possible. There's been a data point with 5 layers. But so far, the cost is pretty high. And 5 layers is not what you need in 2032 to get the density, what you will need in 2032 to get the density is about 125 layers. And if there is no cost improvement on this technology between now and 2032, the cost of the 3D array would be a real challenge. So this is a bit the debate that is happening in the industry. Can we reduce the cost of the 3D array enough, to close enough to the cost of 2D array. And the answer to that depends a lot, but this is a very, very big challenge. I was talking about 30% cost improvement on EUV, right? And I was very proud of that. Here you need to improve by a factor of 100, right? It's similar. So people also talk about new materials because that could be a way to make it simpler right? But that's also material that do not exist today. In fact, material that people have been having -- going after for a long time. So the question becomes, of course, what's happened and what you see here is that most probably, there would be a battle between the 3D array concept and a 2D array like concept where we stack. Cost wise, most probably today, the bottom is an advantage, but I think the debate around that is going to last for quite some time. And we will be, of course, making sure that we work on both. The advantage of the bottom also is that this will be using the same tools as you have today, the same fabs. So you need to build a new fab, you don't need to ask completely new equipment. And as long as the cost of the 2D array can go down, we can stay on the curve here. That's a very important debate. You will see us coming back to you talking about it. But I wanted to show you again that this is not a one path solution. I think there's many, many ideas on how to do that. So this was a bit my piece on technology. Well, I have a few slides on ESG. This is a summary of the commitment we have made very simple here. We say Scope 1, Scope 2 will be done through greenhouse gas neutrality by 2025. 2025 is next year. We are on track. We will be doing that, check. When it comes to Scope 3, I think that's a lot more difficult. So we split it in 3 parts, business, travel, commuting. We also want to do that in 2025. We are on track. We will do it, check. Supply chain. This is a tough one. But because we have, of course, a strong relationship with our supplier, we are working with them so that together, we can achieve the target for 2030. Huge progress being done there. We report on that in very detail in our annual report. You will see that again this year, and we have good hope we will meet that. And finally, the hardest part, which is product use because that's also include our customer. To be honest, that's the part where we have seen a lot of progress in the last few years because all customers, everyone in the industry is really moving. So we are a lot more optimistic now on 2040, it was looking a bit difficult when we set the target. Today, we believe this would be achieved. We will play our part. EUV. So I told you EUV will basically allow us to reduce power consumption. Within 15 years period at customers, so 15 years after we ship the first tool, we will have reduced the energy consumption per wafer exposure by 80%, right? Because we work on productivity, because we work on energy efficiency, et cetera, et cetera. That's quite spectacular. So yes, EUV is, of course, initially quite energy consuming, but the progress we have done on the technology will allow us to really reduce that by 80% by the beginning of -- by the as said at the start of the next decade. And finally, a bit of a joyful slide about our community engagement. This is something we have stepped up quite a bit in ASML in the last few years because we feel this is also becoming our responsibility. We are very engaged with the infrastructure of the community around to support our growth with education, with innovation around us. The bottom picture on the left is our, I think, world famous light festival in Eindhoven. If you stay here tonight, you can go see it. It's happening as we speak. It's very nice, and we have been sponsoring, that's one of the events we sponsor a lot of activity, which we are very proud of. With that, I'd like to thank you. I hope that I didn't give you too much details. I'm sure I did, in fact, but this is a bit a way for us to continue to explain you why we are doing what we do and why it is important. Thank you very much. And I'd like to call one of your friends, who has been switching to the dark side. So please, Amit.

Thank you, Christophe. Well, hello, everyone, to those of you in the room as well as on the webcast. Amit Harchandani. I joined ASML last year to head the corporate marketing function. But this is not my first Capital Markets Day. In fact, it's my sixth. And the first 5, the previous 5 were actually spent sitting alongside many of you over the past decade. So this time, it feels a bit different. In terms of my key messages, let me dive right into this. I'm going to talk about the market. So the first message I would like to share with you is that the long-term outlook for our industry is promising, given the role of semiconductors as mission-critical enablers of multiple megatrends in the society. In particular, and I'll go into this in a little bit of detail, the emergence of AI is a significant opportunity. And as a consequence, we do expect global semiconductor sales to grow 9% CAGR over the period 2025 to 2030 and cross the $1 trillion mark in 2030. What does this mean in terms of wafer demand? We believe this translates into an overall wafer demand growth of 780,000 wafer starts per month per year over the period 2025 to 2030. The rise of AI, of course, as a leading driver, to Christophe's point earlier, thus translate into greater Advanced Logic, greater DRAM, and therefore, you could argue, is positive from a lithography standpoint. Last but not the least, we continue to expect a tailwind from what we refer to now as strategic considerations when it comes to capacity, and we still expect that to contribute up to 5% to 8% extra capacity around the 2030-time horizon. And last but not the least, we've talked end markets, we've talked to wafers. What does this mean for lithography spending? Clearly, Christophe touched upon this earlier, litho still is the best game in town when it comes to driving down cost and driving density and performance. And as a consequence, we still expect the litho layers to go up low NA as well as high NA across both Advanced Logic and DRAM. As a consequence, over the period 2025 to 2030, we expect the Advanced Logic EUV litho spending to grow at a CAGR of 10% to 20%. For DRAM, it's even stronger with a CAGR of 15% to 25%. And I'll walk you through some of the moving parts over the next 20 to 25 minutes. But before I do so, I just wanted to share with you and give you a bit more insight on how do we go about actually coming up with our long-term opportunity. Some of you may remember this slide, it has been shown at previous Capital Markets Days. And one would be inclined to believe that you've got the low inputs and the high inputs and all of them end up coming together into formulating the low and the high scenarios. To be honest, even I thought that way 10 years ago. Found out it's a bit more complex than that. And what makes it more complex is actually there is a plethora of inputs, which go into understanding what's happening in the market out there. On top of that, you bring in all the elements associated with technology. Christophe talked about 4F2, and 6F2 and you got high performance and low power. It's a big blend out there. And it varies by customer, it varies across nodes. You put it all together, you end up with more than 2,000 scenarios. Did not know that before I took the job. But when you put in all those scenarios, and you finally come up with the 3 distilled down versions that Roger is going to talk about as a part of his financial outlook. So suffice to say, just adding up all the lows doesn't give you the low scenario, adding up all the highs doesn't give you the high. It's a bit more than that. So that's a bit about how the model works. Let's now go and talk a little bit about the end markets. So you've seen this slide. Christophe talked about it. And the reason I want to start with this slide is, yes, we talked AI, and we will talk AI, but that doesn't mean the other stuff is not happening out there. It's still happening out there. The megatrends we talked about 2 years ago are still very much intact. It's just that as all of us who have spent some time looking at technology know you tend to -- you have to take it in the long run, things can go a bit left or right in the short term. Eventually, they play out probably even faster than some of us anticipate in the long run. So the climate change and resource scarcity, connected world, social and economic shifts, all of that is very much intact. But of course, the new kid on the block is AI, and we are particularly encouraged by the rapid progress that we make in artificial intelligence. Christophe earlier touched upon the topic of productivity and what AI could mean for the wider society. We definitely think it's going to be the next big driver of productivity and innovation. There are various studies out there. I'm pretty sure all of you have looked at it from someone calling out $19 trillion by 2030 to someone else saying $17 trillion to $26 trillion. So you have all those who are positive on AI and so are we, but we are also very mindful that there are certain inhibitors along the way, whether it's legislation, whether it's power, whether it's ability to drive compute at a lower cost, Christophe touched upon it in his presentation as well. So AI is definitely a significant opportunity, but we need to be a bit more balanced as we look forward to it. But where we have confidence is on the chart on the right, as in case of previous computing waves, whether it was the PCs in the 1980s and '90s, the rise of the Internet, followed by smartphone, we do believe the computing wave of AI will definitely have a multiplier effect on the importance of semiconductors more broadly and ensure that semiconductors continue to become a bigger part of the broader macroeconomic picture, in this case the GDP. So then the question is, how do we think this plays out? And what I'm going to say next will not come or should not come as a surprise to you, which is that indeed, we believe in the initial wave, it would be the enablers, call it the picks and shovels, which in this case, we would call out is the servers and data centers in the storage end market, which would be the key initial beneficiary of AI. If you look at the chart on the left-hand side, we talk about units, and in particular, AI training and AI inference units, and you can see the unit CAGR is relatively muted. But if you translate that to the right towards the associated semiconductor content, you will see the CAGR there is much more significant. In fact, if I could also give you another data point, if you look at AI servers and if you look at raw content growth, so call it transistor growth or bit growth, you're almost looking at 40% to 50% for inference, 50% to 60% for training on a compounded annual basis. So it's quite significant what the content opportunity means in our view for the servers and market. And as a consequence, we expect by 2030, the total sales associated with this market would be more than $350 billion. So that's what's happening in the server's end market. But then that needs to be then pulled into what's happening elsewhere. And if you look at the picture there, what would immediately strike you is the total number is very much in the ballpark of what we told you 2 years ago, which means if servers is up, the other segments are down. And that is indeed the picture as we see it today. 2 years ago, we do believe there was greater anticipation of growth in smartphones, in PCs, but the broader macroeconomic backdrop has not turned out to be that supportive, particularly as it relates to growth of PCs. On the automotive side as well, some of the policy developments over the past 12 months have led us to believe that the growth is still going to come through with a slightly more muted trajectory. And last but not the least, again, to all of you who look at this space so closely are very well aware of the downturn or the down cycle that we have gone through over the past 2 years. But still, on the whole, if you put it together, and if you particularly incorporate for the effect of the shift towards AI, because please remember the enterprises, the consumers, who will be looking to spend on AI will make choices elsewhere, you put it all together, you still have a very healthy backdrop for the semiconductor industry. So what does this mean for wafer demand? Again, let's start with the picture that all of you are familiar with, which is what we shared with you at Capital Markets Day 2022. Just to be very clear, the headline number we talked about back then was 2020 to 2030. However, given we are now in November 2024, we felt it's logical to talk about it in the context of 2025 to 2030. Again, some of you may remember, we did give a 2025 number and a 2030 number 2 years ago. And this was the mix we talked about with mature logic growth of 380 per month per year, Advanced Logic at 220, DRAM at 60, NAND at 100. So if the end market mix has changed, logically that should also have an impact on the wafer demand associated with the end market. And if you look at the picture there, yes, there is a change. First and foremost, I would like to highlight that what -- where we anticipate to land in 2025 is lower in total versus what we anticipated 2 years ago. And the 2 big drivers there are the NAND business, which has gone through a difficult period, which meant that the bit growth was lower, which meant that the need to add wafers was lower. And secondly, the mainstream market, which is associated with late cyclical end markets, where, again, the demand backdrop remains muted, and all of you have heard some of the leading players in that market talk about the prospects there. So that means your starting point for 2025 is lower versus 2 years ago. But that does not mean we do not anticipate growth in 2025. We do anticipate growth, and we talked about it as a part of our Q3 briefing a couple of weeks ago. More importantly, the growth rates, we believe, are still likely to be very much in the ballpark of what we told you 2 years ago, but the big change there is DRAM and NAND. And DRAM goes from 60 to 160. NAND, on the other hand, we believe, is likely to still be muted given the bit demand backdrop and translate into an addition of 40 kilo-wafer starts per month per year. So that's the like-for-like picture as we see it today. But there is another column I want to introduce. And the reason I want to do that is because some of you, and many others have told us, do you really think 28-nanometer is advanced? And we said, yes, we get the message. And then we said, so what do we do? This advanced stuff keeps changing every 2 years. I can't stand up here every 2 years and give you a new definition. I've been in your shoes, I hate reclassifications. So we said, you know what, let's go with a bit of an ASML style here. So the Advanced Logic, as you see, the new definition is less than equal to 7-nanometer, which dovetails nicely with, let's say, the chips, which need EUV. So if logic needs EUV, it's advanced. And secondly, we said, if something keeps growing like this, you can't call it mature. I mean, seriously, mature was when we thought DUV would decline, which is a decade ago, things have changed. So we came up with mainstream instead. So mainstream and advanced is the way we are going to talk about this going forward, but just to make it crystal clear and transparent, the totals all add up, it is just a shift in the way we would like to classify the logic segment going forward. And of course, DRAM and NAND stay the way they are. The total still is 780,000 per month per year. So that's the view on wafer demand. I want to dive a little bit more into DRAM because we talked about AI going up, driving service up, which means it drives the DRAM growth up, as you saw earlier. And what's driving this? Well, on the left-hand side, all of you are familiar, with the rising HBM content, Christophe touched upon it earlier, so did Dr. Cha in the video. And you can see what that means in terms of the AI-driven server DRAM demand out to 2030. And what you can very clearly see is the standard server, DRAM, is not really growing that much. The real growth engine is DDR and also HBM over the next 5 years out to 2030 to a level where we anticipate AI-driven demand from servers alone will go up to 1 million wafer starts per month per year. And you may remember on the previous slide, I talked about the total demand to be around 2.5, so call it 40% of the total number. And just before we close the topic of wafer demand. I actually want to tie it back to the transistors number that Christophe alluded to earlier. So Christophe talked about total logic transistor growth of 26%. What I've shown you here is the Advanced Logic component of that to make it very clear. And the Advanced Logic grows even faster. And if you look at this number, 32%, and compare it to the wafer numbers I showed you earlier, you can see that density is still very much alive and happening. And we are helping drive that density. Yes, Moore's law is slowing down, but the pitches continue to come down, the density comes through, which is why we are still able to pack more transistors per wafer, and that's what this CAGR tells you. Same is the case on the DRAM side, again, if you look at the bit growth CAGR and if you compare it to the wafer CAGR, you will see density coming through. And last but not the least, the same holds true on the NAND side, but admittedly, these bit growth numbers on NAND are much more muted than some of us have seen 5 or 6 years ago. So that's the end markets to wafers to transistors. Now before we get further, we have to also talk about the other elements, which go into the capacity discussion. So we have talked about demand so far. There is a bit more than just end demand, which drives capacity. There are what we refer to as strategic considerations. The first is the desire or the continued drive for tech sovereignty. We talked about it 2 years ago. In fact, that continues to only broaden, and you see a couple of new flags in there, and countries, regions continue to strive to support this industry because they recognize the importance of semiconductors. So we definitely see a broadening range, a deepening range of incentives. The second element, which we did not explicitly call out 2 years ago, but definitely is something that continues to come up in discussions and indeed is driving what's happening out there, is the need for supply security. I was at a conference last week, and this is the latest data from SEMI, the Industry Association, which talks about 108 fabs, which are likely to come online, but more importantly, in all parts of the world. In fact, SEMI argues more announcements are needed to get closer to $1 trillion. But it's not just -- yes, Asia continues to dominate, but it's coming up in all parts of the world. And last but not the least, of course, there is the element of competition within our customer base. 2 years ago, we talked about this in the context of foundry, but if you heard what SK Hynix talked about and if you heard what Christophe said, it's a bit broader than that. It's broadly in logic and memory. We talked about our top 3 customers 2 years ago. The picture again, has become a bit broader. At the same time, we also have to acknowledge that particularly as it relates to foundry competition, given what we see out there in our customer base, we have to take a more nuanced view of how things are likely to shape up between now and 2030. So if you put it all together, it's still very much a tailwind for us, which means when you then think about this in the context of how capacity is built in the industry, we still anticipate these considerations will contribute towards capacity build-out. We told you 2 years ago that we anticipate getting to 10% by 2030. We are tempering it slightly. We think it's likely to be 5% to 8%. You could attribute to us being conservative there, but we believe that is the picture we see in front of us, which is still a very healthy level of strategic considerations, whether it's tax sovereignty, supply security or indeed intensified competition. So that's wafer capacity. Lastly, let's talk a little bit about lithography spending. And I want to spend some time on this slide now. So Christophe referred to this earlier, but let's take a moment to digest this. If you look at 2025 on the left-hand side, starting with Advanced Logic, what you see is a very healthy level of adoption of our low NA technology, anywhere from 19 to 21 exposures. If you think in terms of the road map, again, Christophe showed you the Imec roadmap about the various nodes coming up in front of us. There is -- it's a broadening array. Because if you go back 2 years ago, the big driver or even 5 years ago, it was smartphones, PC portables, tablets, low power, whereas with servers, it's high performance. That triggers certain changes in the way you go about thinking about the Advanced Logic demand. But when you put it all together, remember, those scenarios I talked about at the start, you end up with a range for the total exposures of about 25% to 30%. And within that, we expect the average high NA adoption to be around 4% to 6%. It varies by customer. It varies by what they are looking to achieve as an end application. And it's a combination of low NA and high NA exposures. That's why the number on top is the total number. To be precise and not to confuse you, the 4% to 6% is included, and that's why it says total EUV exposures, but that translates into a very healthy spending CAGR of 10% to 20% for us over the coming 5 years. If you move on to the DRAM side, as you can see, next year, we expect about 5 EUV exposures on average, low NA, and that is, again, blending in all that we see in front of us, 4F2, 6F2. And different customers have different ways they would like to go about building their designs. By 2030, it's expected to as much as double, 7 to 10, including 2 to 3 high NA exposures. And again, Dr. Cha referred to it as a part of his video. And that translates into an even stronger CAGR of 15% to 25%. And we thought this was a much better way to get the message across to you because the key is the number of EUV layers. The key is what that means in terms of the sales numbers that Roger is going to talk about in his presentation later. So with that, I come to the end of my presentation. And just to recap the key messages for all of you. The long-term outlook remains promising. We still expect to cross $1 trillion by 2030. Yes, we expect this to translate into a healthy level of wafer demand with a greater skew to Advanced Logic and particularly DRAM versus what we thought 2 years ago, which is positive from a litho spending standpoint. And of course, in terms of capacity, there remains some tailwinds, tax sovereignty, supply security, and of course, competition. And last but not the least, that translates into a healthy double-digit outlook for EUV spending in the years to come. With that, ladies and gentlemen, thank you. And I will now call upon my colleague, Peter to take you through the next presentation. Thank you.

Good afternoon, everyone. My name is Peter Vanoppen, and I have the pleasure to take you into the world of EUV. EUV has become mature, and that maturity allows us to innovate based on this platform that we have created. That innovation has led us into introducing new products this year. One of the examples is the NXE:3800E, which is a significant overlay and productivity improvement. But it doesn't stop there. This platform allows us to continued innovation, continued innovation that will bring additional overlay performance and additional productivity performance. In June of this year, we ceremoniously opened the High NA lab. I can tell you that since then, this has been a staggering success. All of our customers have been here. They have exposed wafers. And they've told us that they see the capability of the technology to lower the cost compared to low NA on the critical layers by 20% to 35%. The first high NA systems are out there at our customers. And they actually mark a significant milestone in the adoption of high NA in the semiconductor industry. The future is all about getting the cost for good printed transistors down, and we can do this by scaling the cost of EUV. This we summarize in a roadmap, and the roadmap spans a decade, the next 10 years. And what I will show you is that we will have several levers to bring down the cost on the EUV. We have also, of course, an installing -- an increasing installed base of EUV. And the opportunity of that installed base will be fueled by value-based services as well as upgrades and performance, but also upgrades that will enable us to extend the lifetime of EUV. Let's put all of this in a historical perspective. Remember that EUV has introduced a significant step in resolution. If you compare the resolution where we are today compared to 40 years ago, it's 2 orders of magnitude of improvement. And it doesn't end there. We have high NA now being there, which is another significant step in resolution. And potentially, with the introduction of Hyper NA, we will make another significant step in resolution. So our strategy, our goal here with lithography is to continue to drive this resolution down. EUV is mature. We have achieved 93.5% of availability, and you see how this availability has increased over the past years. This is a significant improvement, but it will not stop there. We will continue to improve the availability, and we are targeting in the next years to go to 95%. Availability is one part of the equation. The other part of the equation is productivity. We started out EUV in volume manufacturing at around 140 wafers per hour. This year, we brought out a product that can do 220 wafers per hour, a significant improvement. With that, actually, we have generated the capability to expose more than 3,000 wafers per day, which is a significant step if you look at where we were a couple of years ago. This is enabled by a product that we call the NXE:3800E, introduced this year. It has 38% of productivity improvement above its predecessor and 13% of overlay improvement, enabling the 2-nanometer node. This is an innovative product, and innovation is created by going to higher source power, 500 watts. And if you go to higher source power, you have to make sure that the system can, of course, go fast, and go fast means have higher accelerations in the wafer stage and in the reticle stage. We are -- these 2 -- well, I talked about productivity. The other aspect of it is overlay. On the left side of this graph, you see what we call Dedicated Chuck Overlay, about 0.6 nanometer versus a spec of 0.8. And on the right side of the sheet, you see the historical performance in Matched Machine Overlay. And today, we are achieving sub-nanometer levels on Matched Machine Overlay. We are introducing this system at all of our EUV customers, all of our DRAM customer, logic customer and foundry customers in the next year. It doesn't end there. We're already working on the next generation. The next generation will be introduced early '27. And this tool will enable another step in productivity and another step in overlay, targeting 1.5-nanometer node. Same type of innovation, but then again more, we go to 600 watts of EUV power. And we go to another step in accelerations, wafer stage and reticle stage, enabling the tool to keep up with the source power that we generate. And it doesn't end there for this platform. We will continue innovation on the platform to introduce more productivity and better overlay going forward. It doesn't end there for EUV. We will expand our portfolio. And this portfolio will be expanded in a way that we like to use that portfolio to create flexibility for our customers to have a lower cost of good printed transistors. And doing that, we will focus on yield. We will focus on resolution. We will improve the accuracy. We will improve the productivity and all that while optimizing the cost. High NA window of opportunity, it is now. If you look at this logic roadmap, we talked about single exposure, we talked about double exposure, single exposed capability of high NA we can use today. And we -- I can extend that opportunity into the 0.7 nanometer node and probably even beyond that. I'd like to introduce a bit more in detail High NA to you. High NA fundamentally improves the process complexity. I told you already, it improves resolution. It will bring additional accuracy capability. And because of the single patterning capability, it will bring productivity. Let me talk about more detail and summarize the technical values and the customer benefits. 0.33 NA versus 0.55 NA. It gives you the opportunity to shrink the device density by a factor of 2.8. It will enable a contrast improvement of 40%, which has a big impact on those and which has a big impact on local CD uniformity, the integrity of the pattern. This will lead to benefits for our customers, and these benefits for our customers are foremost the patterning cost reduction. The patterning cost reduction is fueled by 3 main things: first is enabling single exposure. Second is dose reduction. Third is the ability to go 2-dimensional designs. Process simplification leads to defect reduction. Defect reduction has a positive impact on yield. Single exposure has an impact on cycle times, less mask steps. Less mask steps leads to a better optimal use of the fab space. So these are the benefits that our customers will see when they start using High NA. High NA is here. As I already said in the introduction, we ceremoniously opened the High NA lab in June, but June was the end and the beginning of a journey. It was the end of the development cycle. The development cycle for High NA took us a decade. We started designing the tool back in 2014. And soon after the design, we started manufacturing the first modules. Of course, when you manufacture them, you have to integrate them, you have to make sure that they work. You have to qualify them. And after that, in the period of '23-'24, we did what we called system integration. That is a very important step when you put all the functionality together and you make sure that you get to this resolution, this accuracy, this speed that you need to make this technology work and led to the first good exposed wafer in the High NA lab. This joint, IMEC, ASML, High NA EUV lab is an important milestone for High NA. All of our customers have started exposing wafers, and they do that to make sure they start learning on this technology, learning in terms of processes, learning in terms of masks. And with that, they hope to reduce the time from the first process development to when they can start using this technology in the high-volume manufacturing. You see on the left side of this graph that they -- by the end of this year of customers together, both DRAM and foundry customers, will have exposed about 2,000 wafers on the High NA lab. These are 2,000 highly valuable critical wafers that help them understand the capabilities of the High NA tool. The first feedback we get from our customers is actually extremely positive. They're telling us that they very well see the contrast improvements, the imaging capability of the tool, even to the extent that they're saying it's a bit better than what we expected. And this is also illustrated by some of the statements made by our valued customer, Mark Phillips from Intel, who presented at Barclays Conference last September, and he's saying, High NA is there and the tools are healthy. The ecosystem is ready to use High NA. The expected benefits of High NA are evident, and the timing of High NA is right. It's right in a sense that it's on time to avoid complex mask splits of lower -- for Low NA. Back to the fundamentals. High NA is a higher NA, better resolution, better contrast. Better contrast leads to lower dose, lower dose leads to higher productivity, higher productivity leads to better cost. The other aspect is better contrast leads to lower defects. Lower defect density leads to better yield. Better yield leads to better cost. Other fundamental aspect of High NA, and Christophe alluded already to it, is the capability to go to 2-dimensional designs. As in the animation and drawings, you can see if you do interconnects with Low NA, you have limited to one-dimensional structure. And to connect all of these transistors, you will have to do this in multiple layers. You can see this here. In the middle picture, on High NA, you can actually connect these transistors in one go. And with that, you reduce -- you can reduce the cell size, the logic cell size. And you probably can also reduce the number of metal interconnect layers that you require, again, leading to a cost benefit. Theory is one thing, but data speaks for itself. The upper hole is exposures we did in the High NA lab. This is a relevant pattern, contact hole pattern for DRAM. And it shows pitch 40 all the way down to pitch 28 on the upper hole. The lower hole, you see the corresponding Low NA exposures, one-on-one comparing the 2 to each other. A few things become apparent, High NA drives resolution down to pitch 28, and probably even beyond that is possible. And the other aspect is, and you can see this in the number, dose and local CD uniformity, there is a significant reduction in dose and a significant improvement in local CD uniformity with High NA. And what I did is I recalculated the dose that you would need on Low NA. If you would print these Low NA pictures at the same local CD uniformity as High NA, you see that the capability that you can generate with the optics, you would, otherwise, need with excessive dose. An excessive dose, of course, is creating a problem in cost. And, therefore, I also calculated what the cost advantage of High NA is compared to Low NA at the same local CD uniformity, which approaches 50%. Let's now look at a few logic use cases. This is a logic use case, pitch 19. If you want to print this with Low NA, you would need 3 mask splits. If you do this with High NA, you can do this in one go, leading to a cost-benefit of 35%, fueled by the productivity change, of course, but also fueled by the process simplification. Another relevant pattern, what -- this is what we call Random Vias, and this has a critical dimension of about 30 nanometer. And this is a case where you see 2 mask splits being replaced by 1 mask on High NA, leading to a cost benefit of 20%. Then, if you look at Random Vias at a pitch where you can compare directly Low and High NA, the evidence is, again, their better capability in terms of local CD uniformity, pattern integrity as well as dose and productivity. Let me extend that to again to DRAM. This is a DRAM critical layer, pitch 30 or 15-nanometer contact holes, hexagonal pattern. This is something where we would need 3 masks; 2 EUV masks and 1 DUV mask, which we can replace with 1 exposure of High NA, generating 35% of cost benefit for this particular layer. One-on-one comparison, similar conclusion, local CD uniformity improved significantly; dose, significantly lower, leading to a higher productivity. Now with -- one thing I have to explain about High NA is that because of the optic you are limited to half field exposures. If you look at half field exposures for DRAM, where we typically have small die, this will need -- will lead to the fact that to generate a full field, you will have to do 2 masks, 2x the same mask to generate a full field. If you look at the logic case, where some of the die are larger than the half field, you have to do something which we call stitching, meaning that you have to have a mask A and stitch that mask A to a mask B. We wanted to investigate how well we can do stitching. And from these ASML pictures, you can see that actually it's almost not able to see where the stitch line is. That's why I put a line on top of it. So this means that the fundamental capability to do this is there. This is an engineering problem. We can just develop processes to do stitching on the High NA tool. I talked about Low NA. I talked about High NA. But let's now talk about the future of EUV. The future of EUV is affordable scaling. And for the affordable scaling, in the next decade, we're going to do a couple of things. We're going to continue the innovation on our current Low NA and on our current High NA platform. That innovation will be fueled by the source power, productivity increase and will be fueled by overlay improvements, and this will span into the next decade. But we will also make a transition. We will make a transition to a high productivity common platform. And that will enable us to drive the cost per exposure down to -- with 30% towards the early -- towards early of the next decade. How does this work? This works by an innovation, which we call a modular frame architecture. That modular frame architecture is enabling us to fit optics, which are very different in size and in nature, a Low NA and High NA optic, onto the same tool. With that, of course, we can generate a lot of commonality on these 2 product lines. And we can benefit from the innovation on this platform, which we will need. We will need to make the reticle stages and the wafer stages faster and faster. We will have to do this just once, and both product lines will benefit from this. The other consequence of this is that -- of this architecture is that we can fit the Hyper NA optic on it. And Christophe already alluded to it. By fitting this higher Hyper NA optic on this high productivity common platform, we significantly reduce the lead time to get Hyper NA optic out to the market. When we talk about scalability, there's -- it is all about productivity. So when you have a platform that can cope with the productivity challenge, you need, of course, the horsepower, or in this case, the source power to generate all of the photons that are required to generate the productivity. Today, we have products that can generate 500 watts or 600 watts of EUV source power. We have demonstrated technology to go to 740 watts, and we have the ideas to scale this to 1 kilowatt. Effectively using photons means that you need to make sure that the transmission of your optics is right. We already talked about the innovations in High NA optics. And we are now deploying that innovation in Low NA and a new POB, a new projection optics for Low NA, which we call the high transmission projection optics. That high transmission projection optics will have a factor of more than 2 better transmissions. So that means that a lot more photons that we generate in the source will end up in the wafer and will lead to the productivity. With High NA, we do it slightly different. This is -- there we are improving the illuminator. And we are innovating in an illuminator that we call the flexible illuminator. With a flexible illuminator, the total projection optic system will have a transmission increase of 1.4x. And one of the other benefits that are generated by this flexible illuminator is the ability to even further scale the contrast and resolution compared to the tool, the High NA tool as we have it today. This leads to a productivity roadmap. And this productivity roadmap is leading us to productivities going all the way up to larger than 450 wafers per hour for single exposed Low NA. Now let's compare that to single and exposed High NA, which is depicted in black. And this goes up towards 300 wafers per hour. Now if you want to talk -- think about cost effectiveness of High NA versus Low NA, then you have to compare High NA single exposed to Low NA double exposed. And Low NA double exposed is the lower light bluish line, and then, you see that in terms of effective productivity, High NA is outperforming the Low NA tools for this effective productivity, leading to the cost advantage for these critical layers where we can deploy High NA. I talked about Low NA, innovations, maturity. I talked about the readiness of High NA and how our customers are starting to use it. I talked about the scaling of EUV. And I want to finalize about the installed base. The installed base of EUV is growing, and this creates an opportunity for us and our customers and that opportunity is fueled by us improving continuously the availability of the tool by us improving the cost of -- the cost per exposure by us making sure that we can extend the lifetime of the tool towards 20 years. And by making sure that the tools that our customers have in the installed base are going to be able to cope with the upcoming nodes, and therefore, we will deploy performance and productivity upgrades. With that, I'd like to summarize. EUV is mature. We have innovations ongoing in Low NA. The High NA tool is ready. We have an affordable and scalable EUV roadmap for the next decade. And we are deploying service models and upgrade that will fuel the opportunity and service. And with that, I would like to thank you to listening to this presentation. And with that, I'd like to introduce Herman.

Thank you, Peter. So good day, everybody. I'm Herman Boom. I'm in charge of the business line deep UV. And today, I'm going to talk to you about the deep UV portfolio, the deep UV business. And as Christophe already said, it's a lot about innovation. Also in deep UV, it's still about innovation. It's about innovation of performance, it's about innovation on productivity and it's also innovation on cost. But before I go there, let me go to a few key points with you. If you look at deep UV, deep UV is and will remain the workhorse of the industry. And in that context, there's a very important role to play for immersion. We keep on supporting our customers with a high-end immersion line and a mid-critical immersion line, targeted at overlay and productivity improvements. If you look at the dry portfolio, then we have our XT and NXT systems platform that keep on providing full flexibility to our customers in terms of performance, but also in terms of cost effectiveness by building on commonality and operational efficiencies. Very noteworthy is that in the dry portfolio, we're also extending our i-line portfolio within wide-field scanner, the XT:260. Now I will be talking about it because it's an important one also in context of advanced packaging applications. And we are optimizing our installed base. We keep on providing a diverse portfolio of service offerings, upgrade offerings. And by doing so, actually enabling our customers to keep our systems running to keep their installed base running for more than 20 years, and we'll be talking about that as well. Now we heard Peter and Christophe talk about EUV. And EUV by now is the standard for almost all critical logic and memory layers, but there's a huge amount of layers. The vast majority of your layers is still printed by deep UV and using deep UV technology. And that's also reflected in the number of wafer exposures that we see. If we project that from today into 2030, you see that we are almost doubling the number of wafer exposures. And that is supported by different applications and different market segments. On the left-hand side, you see here the advanced market segments, reclassified, as Amit already said, using all EUV. But you also see there that deep UV is present in these advanced segments supporting, you could say, the EUV applications. All of that being done at 300-millimeter. On the right-hand side, you see the mainstream segments. You see a much more diversified application space. You also see that this is the deep UV space where we not only have a 300-millimeter wafers, we also have 200. We have 150 even. And we have many more different applications that we're supporting with our product portfolio. And it's also that with all those different applications, they also lead to some of the wafer growth that we see. And if you look at the different wavelength segments in that portfolio, you actually see the steady growth. But if you project it outwards, towards 2030, you see that part of the growth is simply given by sheer volume, the fact that we need more wafers being printed, but that's also a part which is driven by more layers, a bigger little spend, if you like, in those applications. And if you look at that record -- look at in how we actually delivered the different value there, and we go back to the equation that Christophe showed, right, where at the top side, we see the different value drivers. And at the bottom side, we see the different cost drivers if you like. Now I'm going to talk you through what we do with the deep UV portfolio by first addressing how we create value, how we recreate resolution, accuracy, but also productivity. And I'm going to do that by taking you through the portfolio of deep UV. And if you look at the portfolio of deep UV today, then they basically have 4 wavelengths or have 3 wavelengths, starting with i-line, we have KrF, there's ArF. And there's ArF again in the form of immersion. And then we have 2 platforms. We have the NXT platform, and we have the XT platform. And I would like to walk you through the different wavelengths and the different things that we're doing in terms of innovation on those wavelengths, improving cost effectiveness for our customers. Now let's go in and start with immersion. If you look at immersion, then the ASML immersion portfolio is the backbone of today's industry. On the left-hand side, you see the total number of installed systems, as well over 1,000 systems that are out there in the total world capacity. And the vast majority of that has been installed by ASML. And we've come to those numbers by growing our installed base since the mid-2000s already, right? And that growth has been supported by innovation on productivity as well as overlay. If you look at the last 5 years, then 92% of the added wafer capacity has been installed by ASML. And if you look at that more closely, then actually, you see that as a difference in the different requirements that our customers have. We have the high end, where next to productivity, accuracy, overlay performance remains very critical and that we see mostly applied in, for example, the memory space. We also have a big chunk, which we call the mid critical, our NXT:1900 series, which is mostly targeted at productivity and still at very impressive performance levels. And then we came -- I already told you that we came here by continuous innovation, which you see by the different models that we released in different years. You see that at the bottom of the page. And it doesn't stop there. We keep on investing in emerging technology to further address performance to bring the overlay down even further, but also to improve cost of ownership by improving productivity. And on the top chart here, you actually see our high-end immersion. You see the different models that we have been introducing. And you see that also the match machine overlay has been going down, overlay from 1.5 to 1.0 nanometer in the 2150 that we will be releasing later this year. The productivity hovers around 300 wafers per hour mark. Now if you move towards the 1980, then you actually see an overlay of about 2.5 nanometers, which is sufficient from a lot of the markets. What we see is more geared towards productivity. We're having levels there of 330 wafers per hour. And we're also developing our next immersion system, which will be north of and have a larger productivity than the 330 wafer hours that we have today. Now if you look at high-end immersion, and I already showed that we started with that like a big 5 years ago, then we see that we have a solid adoption of those systems by customers. We have an installed -- a very solid installed base. And by now, we also have shown that when we install those systems within 2 or 3 weeks after they have been installed in these high-volume manufacturing fabs, these -- our systems ramp up to the maximum productivity to around 5,000 wafers per hour. At the same time, over the years, with the different models, we have been improving the overlay all the way from 2 nanometers down to 1.5 to 1.3, and we'll be making another step to 1.0 nanometer later this year. So it doesn't stop there. Later this year -- as we speak, actually, we are in the midst of the qualification of our next high-end immersion system, the NXT:2150. It's supporting even tighter overlay requirements, but it also supports improved cost matching between EUV and deep UV. There's a whole slew of different technological innovations on board ranging from heating controls, temperature controls, new metrology, new sensors, but also very important new optical correction elements. And these optical correction elements are also very important, I'll talk about it in the next slide, to actually apply additional corrections. So on this table, I have the 2100. It's still tiered at 295 wafers per hour, and we're improving productivity somewhat towards 310 wafers per hour whilst improving the overlay performance. Now, I talked about these optical correction elements, and they are important, particularly in the context of bonding and correction of bonding that we needed. So Christophe already showed that if we bond those 2 wafers, actually, we get mechanical deformations in those wafers, which lead to overlay errors. We can measure those overlay errors using metrology, and then, we feed that data into the scanner. We feed that data into the scanner so that we can use it to calculate the corrections that we have to apply to the pattern through the image. And by doing so, we also need the correction knobs to be able to tune that patterned image. And by applying more of those knobs, we can actually get it to a larger correctability. That correctability has led to data, like shown also earlier today, that post-bonding, you would have a 15-nanometer overlay error. After applying these corrections, you have a potential to go down to 2.5-nanometer. So we believe that bringing these additional correction knobs provides a lot of value and a lot of correction capability in those -- in that space. Now let's go to the next part of the portfolio and talk about the dry portfolio, very specifically about KrF. And in this part of the portfolio, we do not only have the NXT platform. We also have the XT platform. And if you look at those 2, then actually those 2 platforms both serve high-volume wafer fabs, but it's a slightly different flavor. You look at the XT fabs, what we call the high product mix fabs, they actually look for versatility. They look for flexibility. They like to configure their system with all kinds of different options, 200-millimeter, 300-millimeter in such a way, it perfectly suits their needs. On the right-hand side, you see the NXT. The NXT is a high productivity platform. It actually suits best in what we call low product mix fabs. Low product mix fabs, meaning old 300-millimeter, not running an enormous amount of different products, just making sure that you get the best out of this big productivity that this platform provides. And it's not only happening -- that's not only true today, we also see towards the future. If you look at the new announced fabs, we still see a lot of interest and a lot of application of both platforms in all these different fabs all across the globe. Now if you look a little bit closer into KrF, and you look into our latest NXT:870 KrF system, then we've seen that system have a solid adoption, a very solid and rapid adoption with a lot of productivity, proven productivity and reliability. And the reason we could do that is because we built it on our NXT platform, an NXT platform that we already know from immersion and also from ArF before. Now we have seen a very solid adoption, and we've seen actually record numbers in terms of productivity on 13-week moving averages, while spiking at 7,000 wafers per day. And -- well, and that's only possible because the system is very reliable, actually providing availability is north of 95% continuously. And it's not where we're stopping. So this system is running at 330 wafers per hour. Actually, as we speak, we have been qualifying our 870B, which is planned to actually have a productivity of 400 wafers per hour. This system, we are qualifying as we speak, and I'm very happy actually to be able to tell you that we had the first sign-off of this system earlier this week. This brings me to the next part of the portfolio, i-line. And on i-line, we've been extending our portfolio -- we plan to extend our portfolio next year with the XT:260. And XT:260 is a bit of a special system in the context of how we normally develop our systems because it's a very high productivity i-line scanner. And the reason we are able to do that is because this system has a larger exposure field. And a larger exposure field does 2 things for us. The first thing it does, well, if you have a larger exposure field, you simply need less exposures to fill up a full wafer. So it cranks up the productivity significantly. So we're talking about 350 wafers per hour, which is the world's -- is the industry's highest productivity on an i-line system in this segment. But the other thing which does for us, it has this larger exposure field. And particularly in advanced packaging, where interposers are printed, the typical interposer size today is about 2x of what an exposure field of a regular scanner will be. So that would require stitching. With the 260, you can actually print this in one go. And even towards the future, when interposers start going, you can actually still print this in one go, maintain your productivity, whereas a normal 4x stepper or scanner would fall down -- would actually reduce in productivity because it would end up swapping masks all the time, and that's being shown in the graph on this slide. Now I've been talking a lot about -- now about our portfolio. I'd also like to give you an update on what we're doing in terms of addressing cost, keeping things affordable, but also staying competitive. So I'm going to give you a peek into what we do with commonality, configurability, also in installed base management. And to be able to do that, I'd like to start with commonality. And commonality is a very important part of our strategy. Commonality means we use the same modules, same materials, same frames throughout different platforms and throughout different products that we are offering in our portfolio. And we have different levels of commonality. We have commonality using common technology within the wavelength, for example, using the same optics, same optical modules, light sources, sensors and the like. But we also have common technology that we use across deep UV wavelengths. Think about wafer stage, reticle handlers, reticle stages. And many of the different options that we provide on our systems can be ported from one product to another. And then very important, we have common technology between deep UV and EUV. Think about alignment sensors, level sensors, metrology, which -- where customers also like to see that things work similar between what they already know from deep UV and what they have on EUV, but also wafer handler, for example. But it is not just limited to the different modules and parts that we have inside the system. We're also looking at commonality outside the system. So part of our system is actually in the subfab. And if you look at that subfab, actually, there was differences in the different cabinets and different systems that we have there to support our products that are doing the work up there in the clean room. But by making sure that we use similar cabinets, the same components there, we can actually gain quite some efficiency. So here, I showed one of the subfabs indicated by the different colors at the bottom. We start producing a system. At the same time, we bring some of these same components in at the customer fab site. We start qualifying the system. We move out the system towards the customer. Now we bring in an XT system, a different product. We start using a different subset of what we have in the subfab, but the white ones and the black ones are all the same. They are all the same by design. And by doing so, they actually get -- move this further down to customer again. And by doing so, we actually leverage the same part, we need less inventory, but also we need a shorter cycles of learning in terms of how we do installations, and we gain time and installation by being able to do things in parallel. So if you look at commonality and commonality benefits, then they are across the whole value chain, right? So it starts in engineering where I only have to develop things once, the supply chain, where I will have lower inventory, lower parts cost, reduced cycle time in the factory because there's less learning needed. At customer side, faster installation, faster ramp-up, but also very important upgradability because they have those things, all those modules, which are interchangeable. We can have the opportunity to upgrade our systems data quite easily. And during service -- during the life of the system, low OpEx, very important also, we can repair and reuse much more -- many more of our parts because they are the same. And it leads also to higher availability. Now if you look at what we do for cost effectiveness, this is not only limited to product design, but also engineering quite a bit on operational efficiency. And one of the examples I'd like to show you is one where we are moving transport from our systems, from airplanes to the boat, which require quite a cross-functional coordination. It brings actually down the carbon footprint of transportation a bit down at about 95% by taking it from a plane into a boat. And I'd like to show you what we did based on a video, and I'd like to start the video right now. Thank you. [Presentation]

Yes. And talking about shipping systems, this was just one. But ASML has been shipping systems actually for a long time. And so I'd like to talk to you also about our installed base. And if you look at the number of systems that we have out there by now, it's over 6,000, right? And we already talked about and said that we like to sustain our installed base and actually extend the lifetime of our installed base, increasing the longevity. And in order to do that, we have a whole portfolio. We have systems out there, which are already 30 years old. So we have a platform, which we started shipping in the mid-1990s. Then around the 2000, we started shipping our AT platform, which is still out there, followed by XT platform. And in 2009, we shipped our first NXT system. So throughout the life cycle of those systems, we're offering different service options. We started warranty, regular service, then customers also have the option to go what we call a value-up service, which means that we do service beyond the normal specifications that we have, suiting individual needs our customers would have. We can also do field upgrades, with that increasing the intrinsic capabilities of the system, for example, productivity, but it could also be overlay performance. Then we move into an extended service that is very important to also apply refresh. So there's some wear and tear on those systems after 15 to 20 years. We offer refresh packages. We see quite some traction with our customers to keep their installed base live, vibrant and on performance. Also trade-in on buybacks. If customers think, hey, from a fleet optimization point of view, I like to actually trade in the tool, go for something different. This is also something we will entertain. And then, of course, beyond 20 years, again, refresh has become important. And also there, we offer a different service and upgrade options. And if you look at that, what that does for the opportunity out there, then this whole installed base provides an opportunity with -- based on this expanding service and a great portfolio. And in here, you see the different revenue expectations that we have based on the portfolio that we have in place, which splits in regular life services, extended life services, field upgrade revenue and also trade-in and refurb revenue. I'd like to give you one example of what we do, for example, for immersion. This is a slide where from left to right, you see actually the productivity going up. And from top to bottom, you see actually the overlay performance improving. You see the different systems that we have shipped over the years plotted in this graph. And what's now important to understand is that we can bring basically every system from every performance down to -- well, we can upgrade it in terms of productivity. We can upgrade in terms of overlay. And you also see this little green bars, we can also provide wafer-per-day upgrades. Wafer-per-day upgrades are things like where we provide services, but also upgrades, where we integrate in the customer process our systems together with the rest of the equipment in such a way that we actually get more wafers out today. Now you see this here happening from all the way from the 1950, 1960 all the way to the 1980. The same applies for the high-end immersion, where we can also upgrade from a system that you once bought to the latest and greatest that you're interested in. Now with that, I'd like to conclude, and I'll not go into all these details. I think I'm in between you and the break. So I'd like to thank you very much, and I'd like to call Skip on the stage.

All right. We're about halfway through the program. 2 hours, I know is a lot of material, so we want to get you recharged for another round of 2 hours of material. So what you want to do is if you can come out and go down either side door here at the bottom, we have some drinks and snacks outside. But we are going to ask you to be back hard at 3:30 p.m. And so for the webcast, we'll start again at 3:30. You should see a countdown clock on your end. We'll see you shortly here. Please be back in your seats at 3:30. Thanks. [Break]

All right. Thanks, everyone, for making it back on time and keeping us on schedule and welcome back for everyone joining via the webcast. Let's continue the program, and I'd like to bring out Marco to give us an update on holistic lithography.

Thank you, Skip. Thank you. Good afternoon. I'm Marco Pieters, responsible for business line applications. And this afternoon, I'd like to give you an update on our holistic lithography solutions and the opportunities. Before I start with a couple of key messages, I'd first like to explain what holistic lithography is about. And actually, we're focusing on improving accuracy and bettering yields for our customers and we do it in the following way, which is depicted by the triangle on the left. Peter Herman already discussed about the scanners, and they also show that these scanners have an advanced control capability, manipulators optical element, et cetera. And with holistic lithography, we actually complement that with -- on the lower hand computation on litho and metrology that gives us basically models that we use to already predict the behavior of the scanner upfront when we're preparing masks. And on the right-hand side of the triangle, we complement it with metrology and inspection, both optical and e-beam. And we use those systems as you will see, to basically get a lot of measurements on wafers, customer wafers in order to steer that advanced correction capability on the scanners. Now if we talk about accuracy, what is this? This is basically driving improvements in overlay and edge placement errors via its computational litho, physical models, but lately also AI, metrology inspection and that scanner optimization. And we've talked a number of times about edge placement errors. But basically, what it is, it's the tolerance that we have between the design that customers basically have on the mask and what actually happens on the wafer. And that difference, that's an edge placement that we need to, of course, keep within certain tolerances. The second part that we focus on with holistic lithography is better yields. And there, we are driving cost-effective metrology and inspection, both for 2D and 3D devices, as you saw also in the [ IMAT ] roadmap shown earlier by Christophe because that's key for early yield ramp as holistic litho control. And on that part, I'll also show our significant progress on our multi-beam e-beam inspection system and the opportunity for driving that system into high-volume manufacturing. And there, the first application that we will see is the so-called Voltage Contrast inspection, but more later on. And after that, we think there's more opportunity by measuring smaller or trying to find smaller 2D defects and 3D structures that require actually very defect inspection. Next to that, we also will enable front-end 3D integration wafer bonding with metrology and control solutions to basically meet our customers' requirements on overlay because we see there is a challenge of the wafer bonding and the deformation that is happening on those wafers. Overall, if we look to the total holistic lithography business, we expect that to grow with a CAGR of about over 15% in the next year from 2025 to 2030 that goes together with strong gross margins. Now if we look back to the value equation that was shown before, holistic lithography basically focuses on patterning yield and accuracy. And this is where our product portfolio is active. So we can be a bit more specific, but I will do that first by looking at the logic roadmap shown by Christophe already from [ IMAT ] and this roadmap has a couple of components. The first component, it shows that 2D shrink will continue. And edge placement error, it's basically's also linked to that shrink, we'll actually see that, that shrink is driving tighter and tighter control and edge placement errors. Secondly, we've also seen that 3D structure is also a part of that roadmap. And especially with the introduction of, for instance, the backside power network, we also see that the backside metal pitch is reducing over time. And that in itself has also given us tighter and tighter requirements on post bonding overlay requirements. So how do we now want to tackle those challenges? As I said, we're focusing on patterning yield and accuracy, and we do that by 4 groups. The first group that we're focusing on is Scanner and Process Control Software. The drivers there are there -- we're transitioning to EPE pitch shrink, but also wafer bonding. And there, the trends is that also it's not just EPE, it is EPE on top of overlay and CD. If you are to high-volume manufacturing, it used to be only DPV, Peter said already, EUV is mature, EUV is there. But moving forward, also high NA will be part of that. So also, that means our solutions need to go all the way from DPV to high NA. And in terms of the correction capability, we showed the graph earlier today. I will go back into more detail later on, but there we go from, let's say, low order corrections, a limited number to correct to a very high order and a lot of correction capability. If you look at computational lithography, there, the drivers are all about the accuracy of litho and edge models, and it goes together also with compute cost. So what are we doing there? As I said, we started off with physical models. Those have been complemented by deep learning and AI techniques. In terms of mask patterns, it traditionally was all rectangular. Now we go to more freeform patterns. And in terms of compute cost, but traditionally, we're only looking at CPUs. We have been also adding there the use of GPUs and hybrid platforms to basically drive down the cost of compute. Then going to Metrology, both optical and e-beam and metrology is all about accuracy, precision, local stochastic effects and, of course, at a right cost. Some of the trends that we see in optical overlay. We always have been measuring on targets, but now we also see opportunities start measuring on device. And of course, with the tightening requirements on overlay, we go to more and more sampling. On the e-beam side, there we go from a small field of view to a large field of view, and that actually enables so-called massive metrology, where we can get massive amount of CD data from wafers that allows us actually to optimize not only CD, but also edge placement errors. And finally, on inspection, where it's all about resolution throughput, being able to measure both electrical but also buried defects. And there was a trend where traditionally, it was optical. We have to move to single e-beam systems. And you will see today, I'll also show what we have been doing on multi-beam systems, including the application of voltage contrast. And these 4 segments, we also can look at the TAM associated with that. And we see actually by 2030, we actually envision there a doubling of the TAM compared to where we were in 2023. Chris has showed the slide before. The litho tool is the only tool in the fab that is basically capable of correcting other process and also process fingerprints. And why is that? Well, actually, every wafer that goes in the litho tool gets first measured on the metrology stage. So we have a good idea of how that wafer looks like. But secondly, every field of every wafer is exposed field by field. That means we can actually optimize the settings of that scanner for that particular field. And you see in the picture, we have a number of elements actuators, manipulators that we can actually customize for that field. And over time, you see actually here that correction capability how to increase over time. And today, if we look at all the degrees of freedom that we have that we can actually optimize per field in a lot, that gives us about 100,000 degrees of freedom. Now how do we use that? Well, what you see here in the dot on the line, you see the trend of basically the scanner capability in terms of overlay. We simply use the scanner as it is, and you get this type of overlay. Of course, here, you already see a significant improvement in overlay over time. But if we then start using these -- manipulate that correction capability to really optimize for product wafers, we actually see that by doing it in a holistic way, we can actually further improve the overlay capability that customers get on product. And of course, you see with more and more process effects coming in, the importance of holistic litho only becomes more. And this is an example where we focus on overlay, but we can actually extend that by optimizing towards edge placement error. And I think that's another opportunity to explore because we do see that, that metric of edge placement error has a significant better correlation to yield. So this is something that we will be exploring and I'll show you in example later on. If we talk about computational litho, as I said, it's all about the accuracy of the models that we have. So before a model goes into production, we do a so-called optical proximity correction, and traditionally, let's say, 10 years ago when the world was only using DPV, we did it with physical models fed by a limited number of metrology gauges, limited number of parameters and we got a certain accuracy at a certain cost. With the introduction of EUV, there was, of course, a need for a higher level of accuracy. And we did that by the following way. We have extended those physical models with AI techniques, deep learning techniques, we're fed by more and more metrology. And by doing that, you can see the white curve, the accuracy actually went down significantly. But more important, well, we have got the accuracy down. But if you look at the cost, we're still at an affordable level. So if you look at the enormous increase in the amount of model parameters, the amount of metrology needed, overall costs were still kept affordable. As I mentioned, we've used that scanner capability to optimize overlay, but this is a project we have been doing with one of our customers, SK hynix, where we actually did an optimization that we called EPE-aware. So what we have been doing, if we follow a wafer through the line in a very simplistic view going from left to right, -- of course, first of all, we make sure that the master pattern at first wafer is optimized with the computational litho. We exposed the first layer or layer end for that matter. And after exposure, we could actually measure with e-beam, high-density e-beam, global CD, but also line edge roughness. So that gives us basically imaging information. Then we exposed the second layer on top of the first one, and then we can measure the overlay between the 2 layers. We do that with our optical system. And thirdly, then we can again characterize that second layer also with e-beam metrology giving us the global CD, but also the local CD and placement errors. And if we then combine these different data sources, we basically can reconstruct the edge placement, as you see on the right-hand side of the screen. And that is an input to basically feed back to the scanner again from those edge placement errors, we can actually see how the next lot should be tuned in terms of overlay parameters, focus parameters; those parameters. And this is something that we will be exploring more moving forward. As I said, this all depends on having metrology. And if we look to our optical overlay system, so-called YieldStar, we actually see that over time, where in the purple line, you see actually the increase in the amount of data points that customers need to sample in order to meet overlay requirements. Of course, we have been following that trend. But more important is with that platform, we actually were able to reduce the cost of a single measurement by about 30% to 45% it in 4 years. So you see, while the amount of sampling goes up, we were able to keep the total cost under control. And moving forward, we see an opportunity there for even more sampling. To the shrink, as I said, with lower pitches, lower edge placement and tolerances, we need to measure more. And I think we mentioned it a few times today. We also see that with wafer bonding, we need more and more data points to basically capture what we see on wafers in some cases, even over more than 2,000 points per wafer. Now talking about our YieldStar platform, earlier this year, we actually celebrated the fact that we have now an installed base of 1,000 systems. And actually, this shows the need for having high-end metrology that can be used to basically optimize the scanners. And looking at inspection, e-beam inspection. As I said before, if we look at the landscape of inspection and if we look at the landscape as a function of defect size, if we look at defect sizes over 10 nanometers, traditionally, it's all physical inspection done by optical solutions. Going below 10 nanometers, the resolution of optics is no longer sufficient, and there is the opportunity for e-beam. But with e-beam has more capability than just physical inspection. With e-beam, we can also do so-called voltage contrast inspection and see-through so we can actually also measure buried and electrical defects. Now if we look at some of the latest trends, we do see, of course, that progress has been made in optical inspection. But we also see that new nodes really require higher resolution to capture defects well below 10 nanometers. And you see it in the middle of the slide, it's also confirmed by a quote of one of our customers who basically say "the defects that I see in that light blue oval that cannot be detected by any optical inspection tool regardless of the inspection time." And the other thing what we see is that because of the more complex 3D structures that fuel the need for voltage contrast inspection, it started with NANDs, but it will soon now also move to DRAM and Logic. And I'll talk about more on the voltage contrast inspection. With voltage contrast inspection, what it does on the top left, it actually detects defects between layers that cause electric open or short. So with the e-beam system we can actually find those defects, as if heavily used already in 3D NAND. And we also see actually that this type of inspection also correlates very, very well with edge placement error. So it's a very good proxy for yields. And on the right of the slide, you actually see here our presence in that market in the last couple of years. So this, we have been doing with single-beam systems. Of course, a logical step would be to basically multiply the amount of beams, what we call multi-beam. We have been doing that, and the product that we have now in the market is called the eScan1100, and that system has 25 beams. And the first thing that you could see, of course, and that's the bar chart on the graph here is that, that systems capability basically gives us a factor of 10x more throughput compared to a single beam system. So you see every bar here represents the layer that's being measured at one of our customers, either a logic customer or a DRAM customer or layer. Next to where we are today about 10x, we also have plans to further improve the system. So early next year, we will be releasing a throughput upgrade to those systems. And you can see in dark blue the projection that we have for the next step that we can make in productivity. So how do our customers use that productivity? It's not that they basically start measuring shorter. No. what they do is they typically spend the same time on measurements. But then in a given timeframe, they can cover 10x more of the wafer. Now why is that important? If you cover 10x more of the wafer, you are able to find defect fingerprints and earlier you detect defect fingerprints, the faster you can correct them and the faster you go through your cycles of learning. And we try to envision this year in the coverage between a single beam system where you've seen this particular case has 0.12% coverage, where on the eScan 1100, the multibeam system, we already have 1% to 2% coverage. But today, that system is out there. By the end of the year, we have over 10 systems installed at over 5 customers, and they're all being evaluated and qualified to use this in HVM. Another data point. And this is collaboration together with Samsung. It actually confirms here also that by using this eScan 1100, they actually had a 7x larger wafer coverage at 60% shorter cycle time. So in this particular case, they even optimized the wafer covers that they need versus the cycle time that they thought was needed for that. And also here, you can see with this wafer coverage, you can imagine you can -- you're able to detect fingerprints significantly faster. So this is the system that we have today. But of course, there's always a roadmap attached to it. And here, you see our roadmap on our e-beam systems. In the bottom, you see our single beam systems. eScan 460 that we have now at our customers, eP5 XLE and we will continue to upgrade these systems and make them more efficient, more faster over time with throughput upgrades. And they're focusing on voltage contrast, physical defects, buried defects. And also there, we do see an opportunity to come with new single-beam systems mainly for those applications that require very high landing energy. The bigger part of the slide is about multi-beam. As I said, the system that we just discussed, the eScan 1100, I call the Generation 1 here already has basically a factor 10x in terms of throughput compared to single beam systems. And as I said, we will continue to also offer throughput upgrades for those systems. But in parallel, we're already working on a so-called generation 2, eScan 2200s. And there, you'll see it on the next slide, we're going to increase the amount of beams from 25 to over 2,700 and that gives us another significant step in productivity. So you will see here, we will go over 100x compared to the single beam systems. And beyond that, we actually think we can go for a different type of setup based on what we're going to do in the next step, and we call that Generation 3. And that Generation 3 actually will give us the throughput where we can actually have 100% wafer coverage area per hour. So we'll be able to measure full wafer within an hour of using, of course, again, significantly more beams. So here, we see the opportunity for multi-beam inspection. As said, we started off with 1,100 at customers being qualified, but in parallel, working already on the system that has close to 3,000 beams. As I said, we're working on it plus technology demonstration is ongoing. And I would like to show a bit of what we have done so far. And apologize for the technical details here. But what you do see here on the top, this focal plane variation, we actually have over 2,700 beams on the scintillator screen, actually working. And we have been validating the true focus behavior of those beams and on the right, you see we actually have been able to validate the resolution that we need. Technology demonstration is ongoing, and we're working towards customer early access next year. When we come to the topic of 3D integration. I think Chris has showed this slide before. We see that in all segments of the market, people will start to use wafer bonding. And of course, wafer bonding comes with certain challenges. And we think that with holistic lithography, we can actually tackle those challenges. Now to give the example that has been shown before, I will go into a bit more detail. If we look at the memory application, where we started to use, let's say, 1 wafer with CMOS, 1 with the memory array that we want to bond. Now these 2 wafers, they had their own life. They had their own processing, their own patterning, but now before bonding, we have to make sure that those wafers actually match in terms of overlay the grid should match. So that's the first part. We have to make sure that while those wafer being processed, we know that they will be matched later on. Then we're going to bond them. So we flip one, put them on top of each other. And as mentioned before, there will be significant stress on that wafer. And that stress will be there. The only key thing is now, how do we make sure that the next layer's pattern on top of that actually are aware of that and we get good overlay. Now the first thing to do is to start measuring that wafer, trying to characterize that stress. And there, typically, we need couple of thousands of measurements per wafer because we look here at a very high frequent overlay of distortion nanometers over 50 nanometers, nanometer-wise over 50 -- so we first characterize that wafer. And then with that knowledge, we can actually make sure that the next layer that we will pattern on top of that actually has an overlay again of below 5-nanometer by using all the actuators in the system. And then, of course, once we have that, we can continue with that afterwards. So it's key that we measure at the right time and translate that into corrections for our scanner making sure that the post bonding overlay meets customer requirements. But it's not only about measurements and doing corrections. It's also about how do we optimize the overall flow. And this is some work we have done together with EVG and leti, where we actually started off first with a standard bonding recipe that gives, and if you look at the top part of the slide, a deformation of about 35 nanometers. And after litho, we were able to bring this back down to an overlay of below 4 nanometers. And we looked at the process and we said, well, what if now we can co-optimize that bonding recipe in the bond of being more aware of what litho can correct later on downstream. And that's what you see in the bottom. So there, we actually get a larger wafer deformation out. And people say, well, that's not good. Well, it's good if you can follow it. And that's what you see on the right-hand side. So with that larger deformation present, but actually more correctable, we actually were able to drive down the overlay to about 2.5 nanometers. So it's not about metrology, not only about metrology, not about control, but also about making sure we understand the full flow, and we optimize over the total stream. So with that, there's a challenge on wafer bonding, but we think that will holistically so we can actually capture it. And that consists of a couple of things, having the right metrology even before bonding the right control points before bonding, but also, again, the right metrology after bonding the control and also be able to optimize the whole stream. And with that, I come back to the summary of my presentation. As I said, with holistic lithography, we're focusing on improving accuracy and pattern yields for our customers. We do it with computational litho, support it with AI, metrology inspection and standard optimization -- and we do see challenges there in terms of front-end integration with wafer bonding. I think we have solutions for that. And as I said before, we've also seen significant progress on the multi-beam, where we are qualifying systems to be used for voltage contract inspection in HVM later on. With that, I'd like to thank you for your attention. And I'd like to get Roger to the stage.

Good afternoon, everyone, and good morning, and good evening, wherever in the world you are in the stream. It's great to be here. Great to talk to you. And during the break, I heard drinking from the firehose quite a bit. So I know there's a lot of information that have been shared with you. And I hope that's a positive because there is a lot of information to be shared. What I would like to do is to try and bring it all a little bit together for you in terms of what this means for the company, what it means for the company in terms of euros because that's, at the end of the day, what is an important metric also for the success, I guess, of the company. So what I would like do is talk to you a little bit about how -- what we've done and the investments that we've made in the past couple of years, how it's actually led to success for the company, both for the customers, but also in a financial sense. And then I would like to talk about how we're looking at the future. I think I'm going to leverage quite a bit of some of the things that particularly Christophe and Amit have been sharing with you in terms of the way the markets develop. But also I'm going to talk to you and bring back the different technology scenarios that you got from the presentation of Christophe, from Amit, but also from the different presentations from the BL leaders, so trying to bring it all together. In terms of the 2,000-plus scenarios that Amit was talking about, so I hope you didn't make plans for this evening because we're going to go through the 2,000-plus plans, just scenarios just to get a feel for what the size of the opportunity potentially there could be. We're going to bring it together -- fear not, we're going to bring it together in 3 scenarios and actually, the 3 scenarios that Amit showed; a high growth, a moderate growth and a low growth scenario, both from a market and from a technology perspective and then tell you how does that pan out in terms of financials. And we're giving it away here a little bit already on the slide and also in the press release this morning, that we're looking at the EUR 44 billion to EUR 60 billion annual revenue by 2030 with a gross margin of gross margin of 56% to 60%. Numbers that sound familiar. I'll come back to that later on. And then finally, we're going to talk about capital allocation and financing. So those are the things that I would like to cover with you in the next 30 minutes. So first off, let's talk a little bit about how we have created value for the company and for the shareholders in the past couple of years. And I think what this slide clearly shows is that we have been creating value by really investing in technology by really investing in innovation together with our customers, together with our suppliers, together with the entire ecosystem. And if you look at this, you see that there has been a significant spike also in recent years in terms of investments. So clearly, there has been a spike in R&D, right? So on this slide, you see that R&D has gone up in the past couple of years, EUR 3.3 billion in 2022, EUR 4 billion in 2023 going to EUR 4.3 billion in 2024. So you really see that the roadmap, the R&D road map that the company has embarked on is very broad. You would very much recognize that, I guess, in the individual presentations. You also see that in the recent year, we're really digesting a lot of the people that have been added in the past couple of years in the R&D department. And in that way, are definitely driving further efficiency within R&D. You also see there's quite a bit of CapEx that has been added in recent years. So you see the CapEx in 2023 at EUR 2.2 billion, a major step up from the year before and also a significant number still in this year. And that, to a very large extent, has to do with the fact that we're building capacity as we told you in the Investor Day in 2022 we are building the infrastructure to accommodate significant growth that a company might be faced with, and those investments are happening in these years. You also see that we've been making some focused investments in the past couple of years in M&A, particularly in those areas where we believe this was critical to -- from a strategic perspective, either because it was critical to get a certain opportunity in the supply chain, get that recognized or because there was a strategic opportunity like HMI, we're just looking at the story on e-beam and multi-beam because we thought it was critical for the further development of Moore's Law of the roadmap. So that's why we do that's -- those are the instances where we do M&A. And of course, there was a major acquisition of the 25% -- 24.9% interest in size given its critical nature for the business. So those are some of the investments that we've made, and I think it's fair to recognize that those investments have paid off, right? If you look at the financial performance of the company in the past couple of years, I think it's fair to say that it's been very, very strong. We're looking at a CAGR since 2014. So let's say, over a 10-year period, we're looking at a CAGR in the earnings per share of 22%, in essence, driven by 3 things: first off, obviously driven by growth of the company, right? So if we look at the level in 2023, we're in fact, looking at 4.5x the revenue that we had in the starting year of 2014. So very significant growth obviously is 1 key driver of the EPS. Secondly, we're looking at gross margin improvements. So you're looking here at the gross margin this year last year of approximately 51% coming from 44% at the beginning of this period. You see there is a little -- the gross margin going down a little bit from 2021 in the years thereafter. To a very large extent, that can be explained by a lot of costs that have been incurred on high NA. So I think high NA makes up for more than the delta that you see there between the 53% and the 51% in 2024, high NA dilutes the gross margin by more than just that delta. So I think that's an important element to recognize in that time frame. And if you bring it all together, together with the fact that we've been doing quite some share buybacks in this period, we executed approximately EUR 20 billion of share buybacks. That gets you to indeed an earnings per share improvement of 20%, 22%. And I think it's fair to say that, that is also something that has been recognized quite clearly by shareholders. So if you look at the shareholder return since the beginning of the previous decade since -- since 2010, you're looking at a total shareholder return of 23% in comparison to 22% for the stocks and 17% for the NASDAQ. You also recognize, and I think that is something that we all vividly see that -- it went down quite a bit in the past couple of weeks, interesting topic for conversation, I'm sure over the dinner. It's also interesting to see that if you look at our CMD -- if you look at the previous CMD, the previous CMD that we had in 2022, you saw the same movement many things that you could interpret there, but just something to call out. For whatever reason, the love between the shareholders and ASML slightly before the CMD is somehow being tested. Let's fast forward to the future and let's look at the continuing -- let's look at continuing growth. I think Amit gave us how we do the model. So broadly speaking, we start with the end markets. We look at the demand for transistors coming from those end markets. We translate that into wafer demand for all the different nodes and all the different technologies that are associated with that, we translate those wafers into what is the most optimum way for the customer to produce those wafers, so which technologies are they going to deploy from a litho perspective in order to create those wafers. And then we add -- and that gives you the tools that person, that the customers need, and we add to that or assessment of the installed base business. That's in essence the way we do it. As you heard, 2,000 scenarios, that Amit and I and many others needed to go through page by page. No, no. Of course, you're looking at those, you're trying to assess probabilities and that way, we get to the 3 different scenarios that I just talked about. So this is an important slide. And I think Amit summarized it well for us. Indeed, you do notice that service data centers and storage are a very significant driver of the growth. As a matter of fact, if you look at the growth between '25 and 2030, you see there's approximately 200 growth in that category alone. So that represents more or less half of the growth in this period. So this is very significant to call out. I think Amit went on to the reasons why the growth on some of the other categories might have been a little bit more muted. But I do think it's good to recognize that there is growth both in the traditional segments as well as in the category of servers, data centers and storage, which, of course, is not only driven by AI, but I think it is fair to say that AI is a significant driver of the growth in that category. Also important to recognize is that if you look at the total capacity that is needed by 2030 to create the wafers that are necessary to cater to the end demand. We also look at strategic considerations. And Amit went through it, but just to recap for you, last time -- last year or in 2022, this was a pretty significant number. You might recall that we added to the base scenario that we had at that point in time of 760,000 wafer starts per month. We added another 150,000 coming from those strategic considerations. Now we're at 85,000 and I think Amit shared the considerations with us. But an important element of that is yes, we do see that this proliferation of fabs across the globe is actually happening. I think the supply security that Amit was talking about is a consideration that is important for the customers of our customers. And actually, it's important for countries and for government. So that's why you see CHIPS Act continuing. That's why you see this proliferation of fabs across the globe actually happening. But I think it's also fair to recognize that if we look at the foundry competition that was one of the elements in the strategic considerations. I think it's fair to say that foundry competition and the size of the foundry competition and what it could do to the extra capacity that could be installed is developing, but it's not manifesting itself at this stage with the vigor that might -- people might have considered about 2 years ago. So those are some of the considerations why we took down the strategic number from the 150,000 that had 2 years ago to 85,000 this time. Very important, and you saw this slide in several presentations, but recapping it again because it is quite essential. We do see that both in Logic and in DRAM, we see over this timeframe of 2025 to 2030, we see an increase in EUV exposures. And what you see here, again, to recap, and it has been mentioned in previous presentations, but this '25 to '30 number that you're looking at here for Logic is what we call 0.33 equivalents, right? So it is in that sense, agnostic to whether it is being done on high NA or it's being done on low NA, 0.55 or 0.33. But there is a translation of effect to the extent that it's done on high NA, it counts for 2 exposures in this calculation. So '25 to '30 in comparison to the, on average, 20 that we're looking at for 2025. So uptick there. And potentially 4 to 6 high NA layers, as has been mentioned before on the Logic side. If you look at the DRAM side, I think it's also clear that we're looking at an uptick there. We're looking at 7 to 10 EUV exposures there of which potentially 2 to 3 could be high NA. And all of that translates into an EUV litho spending CAGR in this time frame between 2025 and 2030, as you see here of between 10% and 20%. So differentiation between low and high case and a EUV litho spending, a CAGR between 25% and 30% or 15% to 25% when it comes to DRAM. So these are important parameters that we have been using in our calculation of the financial model. Talking about the financial model. So these are the model assumptions that we've been using for this model, and I think it's good to go into these in a bit more -- in a bit more detail. First off, market share assumptions are similar, I think, to the market share assumptions that we shared with you 2 years ago. So on EUV, 100%; on ArF immersion, on ArF, we're looking at 90%; and in the Dry business, we're looking at 65%. Those are the assumptions that we've used in this model. What we put here into the assumptions is Advanced Logic, DRAM, those are the real steam engines and NAND, but obviously, the lion's share of our business is really being driven by the Advanced Logic and DRAM. So that's why I'm really going to focus on those 2 in particular. I think Amit already shared with you the -- on the market side, he shared with you a mid case of 32%. And indeed, as you see here, we're looking at a low transistor CAGR of 28% on advanced logic and a high transaction CAGR in this timeframe of 36%. So this an important starting point in the -- in our calculation. Then from a technology perspective, the variables that we used there are, on the 1 hand, we're looking at what is the composition of this end market demand. And of course, the composition of the end market demand gives you, therefore, a blend of high performance, so high-perform compute, and low-power designs used for smartphones and what have you. We're looking at high NA starting in 2026 in terms of high-volume manufacturing. And we're looking at 25 to 30 EUV exposures of which 4 to 6 high NA. That's what we assumed. And again, when I talk about exposures here, -- once again, I talk about 0.33 equivalents. That's the way we look at that. And then if you run through that than what the analysis tells you is that you're looking at an EUV litho spending CAGR between '25 and '30, as I mentioned, of between 10% and 20%. Some people might recall that in the past, we had slightly different models. So in the past, we were looking at node cadences and we were looking at spending delta node over node. We moved away from that because, quite frankly, the definition of what constitutes a node has become quite arbitrary, right? With all the sub-nodes that are in there, it has become a bit arbitrary, what exactly do you call a node. So that's why we moved away from that and replaced it with the data that we show on this slide for logic. If we go to DRAM, we're looking at a bit CAGR between 18% and 26%. So that has gone up, right? You might recall in 2022, we talked about 15% to 25% bit CAGR. And obviously, that is as a result of some of the things that we've been just showing because it was pretty clear, I think, from Amit's presentation, that there has been quite some increase in the demand for DRAM. So that's an important element in that regard. I think Christophe showed you some interesting data points and insights into the technology side of DRAM. So in our model, we've used blends of 4F square and 6F squares designs. And also here, we assume that there is a start of EUV high NA in production starting somewhere in the '26, '27 timeframe in HVM. And as we showed before, here, we're looking at 7 to 10 EUV exposures, of which 2 to 3 could be from high NA. And that leads to an EUV litho spending CAGR, which is actually north of what we saw for logic between 15% and 25%. And finally, the NAND statistics, as Amit showed you, NAND has actually come down quite a bit in comparison to what we were looking at last time. So also a lower bit growth here. Last time we were looking at 25% to 35% as the low and the high scenario. So a decrease for NAND also in our models. But also, as you know, NAND is not a very big variable in our business. So that gives you some of the background in terms of the CAGRs that we're looking at for the system sales business, particularly on EUV as you just -- as you were just able to see. If we look at the installed base business, the installed base business in the first half of this decade, we were looking so far at a 14% CAGR of the installed base business, really driven by 2 things, in essence. So first off, obviously, the installed base is growing, and that comes with a commensurate growth in the service. Also within service, you see more and more value-based services kicking in and then quite some upgrade business. And I think it was pretty clear to see from all the presentations of the different BLs, how important this is to the BLs, how important it is to ASML, how important it is to the customers. Because extending the lifetime of the tools for us is very, very important. So making sure that customers can continue to leverage the tools with all the upgrades that we're providing and all the services that we're putting in there to us is a very important thing to be able to offer to the customers. So that's the driver behind the 14% CAGR that you saw in the -- until today in this decade. From -- for the remainder of this decade, we assume a 13% CAGR. That has not changed in comparison to 2 years ago, so a 13% CAGR to add the top line get you to EUR 13 billion by 2030 as the high market scenario for the installed base revenue by 2030. If we model all of that in terms of revenue, for EUV sales for non-EUV sales and for the installed base business. Here, you see the 3 different scenarios, right? So here you see high scenario, so the scenario with the -- and the probability distribution, the one with the high outcome there. You have the moderate scenario in the middle and then you have the low scenario. And what you see here is that we stopped talking about units. I know you're all very much used to units. We moved away from units. And the reason we moved away from units is because a unit in 2030 is such a radically different unit from the unit that you have in 2025 that we actually thought that, that was confusing. So that's why we said we're just going to -- we're just putting in revenue numbers here rather than talking about unit numbers because that is far more informative to talk about revenue rather than units, which, as we said, differs quite a bit in terms of what they bring. So these are the scenarios. So maybe quickly looking at what are the different drivers of it? Because you might look at this and say, "Hey, wait a minute, these numbers seem a little bit familiar to us, right? Because the 44 to 60, we've seen that before. So I'm sure that some of you thought, well, the CFO has just been asking ChatGPT, what's the revenue for ASML in 2030. And ChatGPT came back with the answer of EUR 44 billion to EUR 60 billion, and that's what I put in. That's not what we did. That's not what we did. So we did it the way Amit explained. And I think what you see here is that although the revenue didn't change from an overall perspective in terms of numbers, it's still in the bracket from EUR 44 billion to EUR 60 billion, it is very clear that there are quite some moving parts in the revenue that shifted it from one to the other. So if we focus on logic, net-net, logic is actually down in comparison to where we were last year. So logic is a little lower than what we had in our models in 2022. What's the background there comparison to '22. So first off, the advanced nodes, as you saw in Amit's presentation, the advanced nodes are higher, so that would be a positive. But it's also fair to say that it's offset by shift in node timing. So there has been a delay in node timing at least to some customers. And that offsets the plus that we had in the advanced node wafer demand that Amit showed in his presentation. So that's kind of a neutral in the first bullet. The second one, as we discussed, the 85 is substantially lower than the 150 that we talked about before. And of course, the 85 and the 150 is a blend, right? So it's not just all logic and it's not all advanced, but there's definitely an advanced element in there. So that is a negative in the total logic comparison. And then finally, as Amit demonstrated, also the mainstream node wafer demand has been taken down a bit. It's still big, right? It's still a substantial number in terms of wafers, less so in euros as far as we are concerned, but it's still a big number of wafers because also with AI, you need all the sensors, et cetera, to empower it, but it is lower in comparison to what we had before. So net-net, if you take all those elements together, we have logic a bit lower in comparison to the Capital Markets Day 2022. Memory has gone up. And memory has gone up for, I think, all the things that you've seen during the different presentations. So first off, the memory wafer demand was higher, primarily driven by HPC and by AI, the high-bandwidth memory. I think the slides that Amit showed there I think were pretty clear. And the fact that in that scenario, we're looking at an increase of 60,000 to 160,000 wafer starts per annum in terms of addition. I think, is an important element in the drive for that increased demand. And secondly, as Christophe showed very clearly in his presentation, there is also a shift from multi to single patterning in both from immersion multi-patterning to 0.33 single patterning and from 0.33 multi-patterning to 0.55 single patterning. So that clearly is in there. And that combination of things is a positive in terms of the number of layers that we see in DRAM. And then finally, the NAND wafer demand is lower, but in the grand scheme of things that does only very little in the total memory demand. So that's why we have memory up in comparison to '22 and logic a bit down and combined, you sort of get to the same range with EUR 44 billion to EUR 60 billion. It's good to look into the details and look at your leisure. You do see that if you start with the moderate scenario that the upside is actually a little bit more on the EUV -- on the EUV side, and that is because we see a lot of upside, primarily also in the AI space. So that's where you see the upside. And the downside, I think, is a little bit more distributed over the different technologies. My favorite topic, the gross margin. The gross margin development that we have here. So the gross margin, if we take the midpoint of the gross margin in 2025, and I told you a significant element in the negative development in the past couple of years and the gross margin has been all the cost that has been taken into the P&L to get high NA up and running. So we have a start at the midpoint of 52% as a starting point. And you see that the lion's share of the improvement to get you to the midpoint of the gross margin of 58% is actually an EUV. Now what is that? It's a combination. First off, obviously, in low NA, where we continue to see you saw the roadmap. We continue to quite a bit improve the throughput; higher throughput, as you know, comes with higher ASP and ultimately comes with good improvement in the gross margin. So that's an important one. Second, volume, more volume in -- more volume in 0.33. And because at this stage, 0.33, with the gross margin improvement is really contributing to the corporate gross margin rather than being dilutive as it was in the past more volume in 0.33 actually helps in driving up the gross margin. So that's a positive. Those 2 are positive. On high NA, you will, of course, see a sustained increase in the gross margin. And we do believe that by the end of this decade, it's not entirely at the level of the corporate gross margin, but it's very, very close. That's the way we model it today. And as a result of that, with that improvement it's going to be not -- it's going to be significantly less dilutive to the gross margin than it has been in the past couple of years, even though the number of high NA systems is going up. So that's the EUV story. If you take that all combined, that gets you at the midpoint, 4%. Then we have a non-EUV. We have a 1% improvement in the gross margin. This volume to a large extent, a little bit offset by mix effects, a bit more dry in comparison to immersion, but net-net still a 1% improvement there. And as you know, we continue to improve our gross margin on the installed base business. And a very important element in there is the service business. We have been very successful, I think, in the past couple of years in driving up the gross margin on service and doing that on all parts of the business. We do believe that 1% further improvement at the corporate level coming from the installed base business is achievable. So that gets you to the 58% as a midpoint for the gross margin by 2030. So how does it all end up, then, in the financial model? The financial model is more or less in line with the financial model that we presented 2 years ago. We're going to call out 3 deltas. The 3 deltas in this model. Starts with SG&A. We have SG&A a little bit higher than we had it 2 years ago, EUR 1.7 billion to EUR 1.9 billion is what we have in here. A very important part of that element is what we -- is the community engagement that we performed. You saw the slide that Christophe had on that front. As you know, with all the growth that ASML is experiencing here in this part of the world, in this part of the country, there is a lot that needs to happen here. There is a lot of infrastructural development that needs to be done in this region. People close to the region know that. The housing, the infrastructure, the public infrastructure schools, et cetera, a lot needs to be done. The Dutch government has put forward a significant package to help the industry grow. So that has been very positive. But there is an element of cofinancing in there, part of that finds its way into the SG&A. So that's, I would say, the most significant driver up of SG&A. Second element you see in there is CapEx. So CapEx at EUR 2.5 billion, quite a bit higher than what we had 2 years ago. And that is related to the high productivity platform that we talked about. You don't get the revenue and the profit of that yet in 2030 because as we showed, the high productivity platform is actually only going to kick in, in the early years, if you like, of the next decade. But at this stage, we're definitely building because there is a lot of adaptation that needs to happen. And that finds its way into the prediction of the EUR 2.5 billion here by 2030. And then finally, a small one, the effective tax rate is a little bit up as a result of our current understanding of some of the tax laws across the group that are effective for us. A few words on flexibility because with the huge window that we still have from EUR 44 billion to EUR 60 billion, flexibility, obviously, is important. What you see here is that the flexibility is there to a certain extent on the headcount, right? You see it on the left-hand side and definitely also on the R&D side, the there is flexibility -- but the big flexibility that the company enjoys obviously is in our operating model, right, where if you look at the cost of goods of the tools that we ship, only 13% of that is labor, 87% of that is what comes from suppliers. So that's a very significant part. And obviously, that gives us an innate flexibility in our operating model, which I think is important. Finally, shareholder value creation. A couple of things, in essence, confirming the capital allocation, as you've heard us talk about that before, so what comes first is that we -- with the cash that we generate, we use that to make all the investments into the business that are critical. So the investments to execute our long-term roadmap. So this is CapEx, this is R&D. This is the support of in Zeiss in making some investments and loans to Zeiss in that regard. So that's critical that goes first. And then whatever is left is obviously returned to shareholders, sustainable dividends per share that will grow over time as you would have seen us execute on in the past couple of years paid on a quarterly basis. And whatever remains as being as excess cash is being distributed back by means of share buybacks. And on the financing side, you would have seen us in the past couple of years, increasingly maintaining a significant amount of liquidity to ensure continued business operations, whatever the circumstances are and maintain a capital structure that targets a solid investment grade credit rating that we currently have at A2 and A plus. Our approach to capital allocation in that way has not changed. And as you see here, focused investments, we've gone through that before and the cash returns that we've been able to do to shareholders accumulative over this period under a little under EUR 40 billion is what we've been able to distribute in terms of dividends and in terms of share buybacks. And dear friends, that concludes my presentation. Thank you very much for your attention. And now I would like to welcome Christophe back for some closing remarks.

Thank you very much, Roger, for -- we get something back. So first, I'd like to thank you for your patience and attention. I was looking at the page number, and we just passed 200 pages. So I think we all realize that this is a lot to take for you. But our intention with that is to inform you as much as we can. And I told you before, we did spend quite some time to prepare this day. We thought this was a very important day. We thought it was very important to share with you our view of the future. I think we have been enjoying a great relationship with you for many, many years. And I think we want to continue to really do our very best to share with you at any point of time, basically, where we believe the market stand, where technology stand, and of course, where we stand. So thanks for being patient. Thanks for going through all those explanation, and I hope that they will be useful for you moving forward. And we have many, many more months most probably together with our IR team to discuss and answer more questions. So that's the first thing. The second thing, since we gave you so much information, we thought it's a good area to summarize it a bit again. I will go through some of the key discussion we had. I will start a bit with a strategic view. Roger will come back 1 more time also on the numbers. The market, the semiconductor industry and the stand, we believe, is going to remain strong because semiconductor is going to be needed for any great invention moving forward. And also because AI is going, if anything, to add basically to that demand. So we see still a very, very resilient market. I think a lot of our peers, a lot of our partners in the industry are giving the same message. I sometimes say the market with AI is better than the market without AI. So I would say the market view we have in 2024 is most probably even better than the one we had in 2022. This being said, AI will take some time. So we're still not sure exactly how this will play out or it will be adopted. So I think we have to see how this evolves next year, the year after and how this happened basically. We also talked about the market size being the same as 2 years ago, EUR 1 trillion, no change. But I think one of the key takeaway I hope for you from this discussion is that the mix itself is very different and this has some impact on what our customers will do. And of course, how we are going to serve them. More advanced Logic, more DRAM, I should call it, advanced DRAM today has always been good for lithography and has always been good for ASML. And I think you have seen also through the video of Dr. Chad that we are already deeply engaged with our customer basically to work with them and address those next challenge. So that's the first thing. The second thing, we talked a lot about technology because innovations will be very, very important moving forward. It has always been -- we talked about Moore's Law in the past. I show you today that Moore's Law is getting a bit on steroid with AI, and we need basically to continue as an industry to provide more and more solution so that the cost, so the energy consumption of AI, basically stays where it should be so that this can really happen. So there will be a lot of innovation and in our case, we believe that lithography will remain at the heart of our customer innovation. And we talked a lot about advanced logic, DRAM. I could repeat. I think Herman showed you also that even on mainstream semiconductor, in fact, the number of Deep UV layer is also increasing. So even there, we spent a bit less time, but we still see that lithography is still a very, very good way to drive innovation, to drive cost down, to drive down energy efficiency. So we are going to continue to innovate on our portfolio. EUV, I like to say it because getting to 200 watts for ASML has been such a difficult mission. I mean we have been sweating for years. We have been talking to you for years without showing any progress on power. And today, we can proudly stand here and say, well, we know how to get the power up for many, many years. And not only we know how to get the power up, but we know how to reduce the need for power because we're going to move to optic, which is coming to life with High-NA, which allow us to reduce the number of mirror and therefore, get us back a lot of productivity. So we have in hands a technology that will allow us to extend EUV, I would say, at least for the next 15 years, reducing costs, reducing energy consumption. And we will pace of course, innovation. We will introduce Hyper-NA when the time comes. We will work on productivity. But all of that give us a way to really help our customer. Like I said, we can commit to our customers to reduce the cost of EUV exposure, not because we are going to give away from our profitability. I think you saw that with Roger, but because we can because we know how to do it. And that's a luxury, and that's something that is very important. So what's next after EUV is a question that we get a lot. The answer is simple. It's EUV, and it's EUV for the next 15 years. And this is the value of this technology, and this is why also the investment we have made on Low-NA and High-NA, I would say, has been such a very smart investment. Then there is holistic lithography. So I know it's always a bit of a complicated topic for all of you because this brings many, many different pieces together. You have a lot of different metrology. You have a lot of different models. We have a lot of different correction. But there, I will say, because of the accuracy our customers are going to look for, the demand for control of the process, which is going to be even higher after bonding because bonding is doing very bad thing to the wafer practically, and we have to go and repair that with process control. So the demand for control and therefore, the demand for metrology and therefore, the demand for very smart model that Marco start to call AI because AI is going to be part of that. AI is also an opportunity for ASML. This combination is still great for our customer. And the value holistic lithography has generated in the past is enormous. If we had to deliver the accuracy today, we have delivered with our holistic lithography -- without holistic lithography, just using the scanner. The cost of a scanner will be enormous, right? So holistic lithography has allowed us also to keep lithography affordable for our customer, and this will continue to be the case. And finally, Deep UV. So you also saw from Herman that this is a very important product, very, very important product. It's not all about EUV. EUV is doing the critical stuff, but then you have to do all the rest. And the rest is also expensive. So you also have to work on costs. You also have to improve those technology. And I think what Herman has shown you is that we are still very creative on the technology. We're improving performance, productivity. But we are also looking at any possible ways to reduce cost, with our supplier. You saw the example of the boat shipment. And the boat shipment is a bit an example for us on how far we are willing to change to address those new challenges. I can tell you that talking about shipping a tool by boat 5 years ago in ASML was seen as a crime, right? But we are also capable to change in the way we run operation because this is becoming more and more important for our customer, right? Finally, installed base. So the good thing with installed base is, of course, the number of tool goes up over time, and the ratio between the number of tool you ship every year and the number of tool you have on the ground is always going towards the number of tool you have on the ground. We have done quite some work with our customer to demonstrate the value of our service. There was a time where, in fact, on Deep UV tool service was coming for free in ASML. I think you've seen with Herman that this has changed quite a bit. And basically, we continue to do that because our customer can use those systems for 20 years. When they look at cost of lithography, they depreciate the tool over 5 years. Well, in fact, they could depreciate the value of the tool over 20, maybe 25 years, right? So this is also very important. And finally, ESG. So Roger said it, we are even willing to increase part of our SG&A to contribute positively to community. We believe this is part of our responsibility moving forward in ASML. That's for the big picture on the strategy. Roger will give you back one more time, the $44 billion to $60 billion range.

At the back of the rough, absolutely. Thanks, Christophe. Very much in line. So starting point again, end markets as a total number, not different, not dramatically different from what we had 2 years ago. Composition definitely different. And the composition also more to the advanced side, advanced DRAM and advanced logic. So that's a positive. We've become a bit more conservative, however, on the strategic side. So the 150 we brought back to 85. So that's prudence that we applied in light of the considerations that we gave before. Yes, the proliferation of fabs across the globe is happening, but also the progress that we see on the foundry competition whilst there is maybe not as exacerbated as some people might have expected 2 years ago. So that's why we've been more conservative in that part. Combination of those 2 means that on the market side, on the logic, we take it a little bit down. On memory, we take it a little bit up because of the spike in DRAM. On the technology front, I think what we've been able to demonstrate, I think, in this presentation is that we're making really good progress on all parts of our business. I think when it comes to logic, I think that is more or less in line with the expectations that we gave in 2022. I think for DRAM, I think our comfort levels have actually gone up quite a bit and the comfort level there that we have in terms of being able to get more and more layers on EUV, that confidence level has gone up based on the presentation that Christophe has shared with you. And the combination of those 2 is that we're looking at a larger memory business and a slightly lower logic business. So net-net, still the 44 to 60. But again, there with a different composition. And based on the potential that we see to improve the productivity and the value of our tools to the customer, the value that we bring in our installed base to the customer and our ability to control cost, I think that has also given us good comfort that even though we're starting in 2025, with a lower starting point as it comes to the gross margin that we're still able to improve and still believe that the window of 56% to 60%, with the 58% as a midpoint, that we have a clear path and clear plans towards that. I think that is it, Christophe. And I guess with that...

Time for Q&A.

Time for Q&A.

Yes. Thank you, guys. Okay. Let's jump into bring the presenters up here. We're going to bring the chairs up. I'll take that. And we'll get the chairs moved. Yes, please. And we'll also have -- for those on the webcast, we have a large number of questions coming in. So we'll be working through those as well. So give us a few seconds here. We'll get things set up. All right. So let's get started. Microphone is coming here.

Didier Scemama, Bank of America Securities. Thank you for all this information a lot to take in. A couple of questions. So you say you're bullish on AI, but I would argue you're bearish on AI. For 2 reasons: a, when you look at your CAGR for smartphone and for PC is actually quite low. So am I correct in assuming you're assuming effectively no replacement cycle driven by AI, number one. And on the data center opportunity, you're talking $350 million or billion, apologies. I think AMD have talked about $500 billion in '28. So I guess my question to begin with is if we were to be a bit more optimistic on Edge AI and on what AMD are saying, are we tracking closer to the $60 billion? That's my first question. The second question is a lot of focus today on cost productivity and just making EUV more affordable effectively and greater reason for customers to upgrade. I wonder, as the industry transition to chiplets, whether that benefit is somewhat negated? Or do you think actually EUV is enhanced or complemented by chiplets?

Roger, you go first?

I'll take the first and Christophe takes the second. So Didier, thanks for your question. I think when it comes to data centers, I think Christophe showed it in his presentation. The potential is huge, and you showed it in your presentation, the potential of AI is huge. But there are also obstacles that need to be overcome. So that's why we took a view that some might look at as prudent, which that's the view that we took into our base case. To the extent that the opportunity that all the roadblocks are being removed and you get to a higher number. As Christophe said, be my guest to put it into the model and off you go. When it comes to Edge AI. Again, there's a debate. I think we are of the view that it might take a bit longer before Edge AI really powers the opposer devices in such a way that it's going to be absolutely compelling for customers to replace their devices earlier. So -- again, you might argue, we've taken a bit of a prudent view there. Most industry analysts that we see believe this will definitely come, but they're hesitant to confirm that, that's already there by 2030. So that's why we've always taken a fairly prudent stance to the extent that this is going to manifest itself, then you're absolutely right, and you're going to see larger CAGRs there.

Yes. And on the second question, I think the short answer is no. So I don't see that there will be some potential value taken away because chipsets are being used. I think this is being used extensively today. It's a way to optimize already the cost. I think that explains also the mainstream part of the semiconductor, which remember, we still believe is a large part of our business. So the idea there is that if you can have a functionality using a lower node, either for logic or DRAM, I think you should do it. I think that trend will continue. AI or the need for high-performance logic, high-performance DRAM, I believe, on the other hand, will in fact, increase front-end integration. So today, you talk a lot about advanced packaging to create more density. I think we will see more integration in the process itself. So that's a dynamic we have to watch as well. We don't know exactly how it's going to play. But I think the trend is towards a lot more integration on the wafer itself. So you have those story about chiplet. You also have those story about full wafer chips that are already developed by some of the AI customers. I think TSMC has been talking about those products also publicly a few times.

It's Mehdi Hosseini, Susquehanna International. Two questions for Christophe and the team and one for Roger. Can you help me understand what's going to drive the increased system commonality between Low- and High-NA? You had a reference going from 50% to 98%. And just -- I don't want to get into engineering aspect, but what are the key parts of that increased commonality? And number two, it seems to me that holistic lithography is an enabler for selling more expensive EUV tools. Maybe you can just debate me on that. And, then for Roger, given the fact that you're more conservative near-term 2025, would the buyback be more of like a year from now? Because I think that's the big difference between today and Capital Markets Day in '22. If I'm not mistaken, I think back then, '23 proved to be a stronger year and your cash flows improved. And I think you had a stronger buyback. And is that the one key difference today versus the last Capital Markets Day?

Okay. So I will try also to be simple on your first 2 questions. So if you look at the commonality moving forward, what we envision between Low-NA and High-NA is to try to have the optic being the only difference. That's the idea. So everything else, except for the optic, would be about the same. The source, of course, the stages, but we even go down to the frame. So that's the leading principle. And that principle will be optimized, of course, based on the cost of the 2 platforms. But if you start from the idea that everything is the same except for the optic. And if you look at the bill of material of the tool today, you come to this number. It's far above 90%. So that's the simple answer. Now the question about holistic lithography, there's always the question about cost, which sometimes could mean the cost for the customer or the price of the tool, and I try to touch both. So like I said before, the reason why we do holistic lithography is to reduce the cost of an exposure for our customer. I took the example of overlay. With holistic lithography, the cost of overlay is a lot cheaper for our customer than it will be if we didn't have holistic lithography. So when you come to our customer, the cost of litho exposure using holistic lithography is going to go down versus not using it. Now for us, of course, the product Marco was talking about are coming on top of our scanner and generate value for ASML. But that's a bit the win-win situation we have been trying to create forever. That's also the win-win situation I've been trying to explain around the improvement on EUV cost of exposure. We will reduce the cost for our customer, and that will translate for us into more revenue and more profitability. This is the simple model. So if one day you don't get both, most probably one party will say this doesn't make sense. As long as we get both, everyone is happy.

As to your question on share buyback and liquidity, I think in 2022, it was clear that order intake was very, very strong at that stage. We were coming out of a period, I think, where we were very much supply constrained and being supply constrained meant that customers, even though the downturn was starting to manifest itself, still customers were very bullish in placing orders and as a result of that, providing us with cash. I think what we've seen last year, in particular, is that, that has kind of cooled off. I think the reason for it cooling off is, first of customers know that we have been building capacity. So to be supply constrained is not going to kick in as rapidly. And frankly, some of our customers have gone through some very tough days. And there, we also believe that it was appropriate for us to help them by giving them extended payment terms also for down payments and what have you. So that has happened. And I think that has led indeed to at least for the first quarters of this year to a lower cash inflow. We've also taken quite some inventory for High-NA, taken quite some inventory for further ramp in Low-NA. So as a result of that, I think indeed, the free cash flow hasn't been as strong as it has been in previous periods. I think realistically, even though we're not going to give any guidance on share buyback, we never did that and won't do it. But I think realistically, if the market comes back, that will also come with healthy order intake as a result of that healthy down payments and the healthy building down of the inventory levels as a result of which the free cash flow should become -- should get again to good levels, and that would allow us again to perform share buybacks. If that is the big difference with the Capital Markets Day in '22, I hope not, right? Because this is a bit of a short-term thing that as a result of the cycles that you have in the industry. And the way we try to help our customers and try to help our supply chain, that could lead to a situation where sometimes our cash flow is a little bit under pressure. But as I've also shown, we have a capital structure. We have a liquidity structure that allows us to play that role. So from that vantage point, I wouldn't see that as a major difference. I think the major difference, if I may express that on your behalf, the major difference is, a, the way we look at the market and the way AI has kind of redefined the market to a certain extent. And I think the very strong progress that we're giving on the development of our technology. I think those to me would be the key things that I would highlight from the meeting.

Sandeep Deshpande, JPMorgan. Two questions, if I may. Firstly, on your growth assumptions in the memory market, clearly, I mean, you're more bullish on the DRAM side. You do seem a little more bullish than what the DRAM makers are saying. Is there a reason from what they are ordering to you, which is why you are more bullish on bit growth than them particularly in DRAM? And then my second question is regarding the competition in the industry. I mean, there is this worry that overall competition is declining and that the number of customers that you will have in the long term will not be as many as you have or at least substantially -- and is that having an impact in your negotiation on pricing at all on the tools, particularly from the most healthy ones of your customers because they are so critical to your growth in future years?

I think, Sandeep, on your first question, and Amit, please weigh in. But obviously, I think what you're hearing from our customers, I think, is a little bit more short term. I think what we're looking at is the longer-term demand. And I think as Amit has been demonstrating the longer-term demand, given the dynamics in the end markets that we showed, the longer-term demand on the advanced DDR on high-bandwidth memory, those dynamics are very, very positive. So that's the reason why indeed, particularly on that front, you do see a very healthy development and the CAGR over that 5-year time frame, healthy as we've portrayed it. So is this completely synced up with customers? Well, the longer-term ideas and the technological dynamics are, right? Because obviously, we are in very close contact with our customers on the technology that they are deploying. But I think the delta that you might observe is really the time horizon. We're looking out all the way to 2030. And I think the commentary that you see is a little bit more short term as well.

And if I may just complement. We just saw it in the room right now. Didier suggested that we are being too conservative. And on the back of that conservatism, the result in DRAM demand to you looks more bullish compared to what our customers are saying. So that's exactly the dynamic we look in front of us. There's a range of possibilities. But to Roger's point, we are giving greater weightage to the end markets, but at the same time, we acknowledge the enablers, but also the inhibitors at this nascent stage. But putting it all together, indeed, we do think our view is fairly constructive on the long term. And yes, we did look at what our customers are saying, but we do believe it's good to be constructive on the long term. I'm saying be constructive, not go sky high bullish, not go pessimistic.

And maybe the second one then, Christophe, on the...

Yes. The second question is a bit of a more difficult one because, of course, there's a lot of things happening on the short term. So I think that triggered this question. I'll split the answer into 2. So if you look at memory, I think that clearly, there were some early winner on the high-bandwidth memory. This has to do with, I would say, the advancement those winners had in their R&D product versus other. I would be surprised if over time, I would say, the key DRAM customers are not all playing in this field because the demand is such to a mid point that most probably the market is going to need to see that happen. So that's for memory. So I think some maybe short-term turbulences, but on the long term, I think mostly we go back to the scheme we know. For logic, advanced logic, of course, you have one formidable company that for many, many years have been driving foundries, and they have been always ahead. I think this is true, by the way, for many, many years. If you look at the market share in foundry, this has always been skewed towards one of our customer. I think it's still true today. Lot of discussion, because we had a lot of question about how many players they may or may not be. I'll let you guess yourself. But if you look at still geopolitics, if you look at the overall demand, including over time, a higher demand for logic in DRAM. I think that's something also that will come. I think that this will -- it will take a lot more time to answer the question you're trying to answer. I still think that on the long term, we will see everyone fighting for this business. That's my at least assessment today.

Maybe just a couple from the online. I think the one that seems to be have the most routine, there are some questions about between 2025, we gave some update last quarter. We're now talking long term. Can we say anything about the midterm? I want all the blanks filled in.

Yes, sure. Yes, sure. We've given an update on 2025. We give an update 6 years ahead of 2030. I think that's good enough. And people can obviously look at '25, and look at where we want to land in 2030 and then ask themselves the question, is all of that going to happen in 2030, in all likelihood not, right? So but we said 2026, we look at '26 as a growth year. And I think people should just look at what we set for '25, look at 2030, recognize we look at '26 as a growth year, take it from there.

Yes. Another one was with all the discussion on the way that the road map is evolving with the 3D possibilities there. It looks like there's a lot going on within the holistic litho space that Marco identified. Is that something that we see as a space that we fill? Or is there something that we're looking to do any acquisitions or anything around that arena?

Well, in general, I think if you look at our plan, our plan does not include any acquisition, right? So our plan, there is no M&A in there. And we've talked about this before. The opportunity that we see without any acquisition is huge, right? If we look at the opportunity that we ahead of it, it is colossal. And that's why we don't have it in the plan. Does that mean that we're going to categorically say no to any acquisition? No, that's also not the case. And you've seen that before. If we see that there is something that need -- that we think is critical for us to adapt because it's critical on the road map of our customers, and we need to do it, then we jump in, right? And that's what we've done, for instance, with HMI. That's what we've done in constraints on our road map. But at this stage, we didn't plan for it. It's not in our plans, and we think that the opportunity that we have for the business that we're currently in is massive.

If I can add to that, I think I hope we demonstrated today, we have a lot to do in ASML. And I think we continue to be very, very focused on the execution of our strategy on EUV, on Deep UV. And on holistic lithography, if you recall what Marco, what I was presenting, I think Herman touched on it a bit, this is still very much about what we can do today. So we've been talking about scanner control, which we have. We've been talking about metrology, which we have. So this is built basically on some of the things that are already in house. So the focus is always on getting that major strategy going because this is really the biggest part forever of what we are going to do. And if you look at history, you're right, our acquisition has been always about maybe taking something that maybe would not have worked if it was in-house. And I think that logic will continue, right? So we stay very, very focused on our strategy execution. And if on the way, we feel that one element may block us in doing that, then we will consider that. That the same logic I think apply moving forward.

C.J. Muse with Cantor Fitzgerald. Two questions on High-NA. The first one you talked about, HVM in '26, '27. Curious if you could speak to layer counts and the breadth of customer adoption across both logic and DRAM? And then a longer-term question for High-NA in terms of possibly increasing the size of the reticle. Obviously, that would be enormously disruptive to the mask guys, and you would need to have TSMC behind it. But you have companies like NVIDIA who are reticle limit, and that could be a way to drive improvements, particularly in the AI space. So I would love to hear your thoughts on that.

Yes. So I'll try to answer maybe Peter, feel free to add. So on the question on high-volume manufacturing, I think it will be both. So I think the adoption in DRAM, logic, we see happening around the same time. As it happened before with Low-NA, most probably logic and DRAM customer will be looking at first using High-NA for 1 or 2 layers, so that they develop their understanding of the technology, they learn about it, they develop whatever they have to do in the factory and then they will basically scale up, which is pretty much the number we were showing for 2030. So we always look at what we call a 2 nodes adoption. The first node is just to almost kick the tire, if you want, and then you get really serious on the next one. So I think this will happen around the same time for logic and DRAM. It's always difficult to point to who will really go first, but it won't be a huge difference in terms of timing. And on your question on the mask, so I think you said it yourself. This is indeed a major disruption. I think we have explained to our customers. We can do it. We know how to do that. It's something we could do within a few years in ASML. A larger mask is not a bad idea for lithography because you can scan longer. So it was a bit the story of I-Line from Herman. So we like, in general, bigger mask. But we cannot do it with the entire ecosystem. And for the entire ecosystem to move, I think the voice of our customer is more important than ours. And I think we have already one customer very vocal on that. And I think you mentioned the one that at some point of time has to be convinced that this makes sense and then the industry could move. So there, I mean the value is such that I will say, as a customer get used to High-NA, they see the value, they like it. They have it in high-volume manufacturing. I think this will be a natural discussion. And that's why we are not shying away to have the discussion with our customer and the ecosystem.

And maybe since we're on that topic, Peter, there's a few questions here on the stitching and use of High-NA and why we're okay that customers are okay with the use of stitching. And maybe just a quick explanation on the how half field works in terms of the final productivity, meaning the specifications you put up there? I assume that includes half field, those type of questions.

Yes. So when you expose half fields compared to full fields, you have to expose more fields on a wafer to get to the same coverage. Of course, in the way we have designed the tool, we took account of that. And we have increased the acceleration potential of our stages to be faster, to move faster from field to field to compensate for the half field. Now indeed, as I explained, the -- once you have larger die than the half field, you have to stitch. The intrinsic control in the system in terms of overlay and imaging control and the way we can compensate for that also with our knowledge on how to do the mask and how to stitch masks, we already showed that this is an engineering problem. So -- and an engineering problem results in a development cycle that you can implement in high volume. So there is no significant concern around stitching.

Right. Andrew?

Andrew Gardiner from Citi. Just first, a follow-up from C.J.'s on High-NA insertion. If we're thinking of that in the '26, '27 time frame and sort of the customer interest there for 1 to 2 layers, you've got some in your backlog today. My math sort of mid-single-digit billions of backlog for '26 and beyond. I presume most of that is High-NA. Is that enough to see customers sort of draw down that backlog to get that insertion done? Or will we need to see additional orders for High-NA on those initial nodes? And if so, what are your lead times? When would you expect to see those orders come in?

Well, I think the number you mentioned is a big number, by the way. And I think that is also important for our customer to, I would say, to get the return on those major investment because, as you know, High-NA is a major investment. So those tools will definitely support the initial insertion, right? And that's why we got some of those orders before. Not fully. So it means that as time goes, we will see some addition. But the next, I will say, a major wave of orders should come for the bigger node because this is where you're going to look at a much higher volume of machine. That's also when we will be looking at ramping our production a bit more. And that higher number of machines, we have always given 2027 as a starting point. So that will be out of the 2 nodes insertion I was talking about, that will be the second one. I think the first node with some addition, could most probably be started with some of the tool we have in the backlog.

Okay. And also related to that, the sort of 4 to 6 layer count on advanced logic by 2030, if -- you don't have the slides up, but if I sort of remember, if we double that to get to a 0.33 equivalent, you're almost implying little change in terms of Low-NA layer count as we look out through the subsequent node transitions. Is that right? Is there cannibalization happening? So how are the customers developing their process around that?

So we talked about equivalent Low-NA EUV layers because as we move in the road map, some layers require EUV. And yes, some of those layers may move to High-NA. And by the way, they move usually as a factor of 1 to 2 because you go from double exposed to single exposed. So that's why we look first at the total picture. And then you get some cannibalization, of course. But because you keep moving to the right, you also get some additional Low-NA layer. So that's a bit more tricky, mostly it's a good question for a follow-up. But we first look at the total potential for Low-NA EUV equivalent. And then we try to decide how this will be allocated between one or the other tool. That's for the capacity. So that's something important for us. If you look at the revenue, I would say the allocation matter a bit less. That's also why we try to not confuse you too much with all those numbers because at the end of the day, the change is minimum.

But if you look at the math, Andrew, I think you're pretty close to it, right? So we said 25 to 30 tools. And we said 4 to 6 High-NA exposures -- sorry, exposures, 0.33 equivalent. So what that means is if you take the highest point of that, so if you take the 30, you take the 6 layers, that gets you to 18 Low-NA and 6 High-NA layers -- exposures. I mean that's what you would end up having in that model. Does that make sense?

It's Janardan Menon from Jefferies. Just to follow on Andrew's question on the capacity side. So you've so far talked about 90 Low-NA and about 20 High-NA. But what you're describing here seems to be a situation where you'll probably end up by 2030 with more than 20 Low-NA and probably well below 90 High-NA depending on how the additional wafer volume translates to that High-NA to the low NA. So is your 90, is that a fungible number? Can you change the capacity? Or does this mean that you have to add new capacity on the High-NA side if that were to be the situation? And then just as the other side of that revenue equation, you've sort of indicated in the past that every time you add wafer throughput on the Low-NA machine, the ASP sort of rises by -- in the region of about EUR 1 million. You've talked about as much of 450 wafers per hour on some of your Low-NA machines, I thought I saw on one of the slides. So does that broad thumb rule last all the way to that kind of wafer throughput? Is that what we're looking at? And should that be also the same on the High-NA machines where also you're indicating pretty high throughput in coming years? And is that how we square the revenue calculation? And just last quick one for Herman perhaps, which is on the rising layer count on Deep UV. I'm just wondering where does that come from? Like if -- is it because if you go to a 1.4 nanometer, yes, your EUV layer is probably flat or rising as the calculation showed, sorry. But is the Deep UV, does immersion layers rise at that point? Or is it coming from 28-nanometer, 20-nanometer, where is that coming from? And especially given the context of what you're saying that Low-NA is replacing double patterning on immersion, where does that rising -- I mean, Deep UV layer count come from?

Yes. I can start with the end of the question. So we -- what you see in the road map is a lot of changes in the architecture of the different devices, for logic, for DRAM, for NAND even. And every time you change the architecture, so we talk always about the number of EUV layer, but I'll give you an example that you well know, if logic move to gate all around, this requires some more lithography, but those lithography exposure will be done with Deep UV. They won't be done with EUV because they are not critical. I'll give you another example. If NAND customer decide to make more tier, that again require more lithography. So we have seen the lithography number of layer for NAND going up over time. And again, that's not EUV at all. In this case, that's most probably KrF. So every time you have a change in architecture, this require more process step, and those process steps that are not litho critical will be done with Deep UV. And that's why you still see the number of Deep-UV increasing. And that's true for NAND, logic and DRAM, to be honest. We spend usually less time on that. That's why we made the choice to show it to you today. That's still quite significant, and this has been happening also for many, many years. So when it comes to the question of the mix in EUV and what that means ultimately for capacity, as it comes to capacity, this is -- your question is one of the key reasons why indeed we're looking at common platform, right? Because at the end of the day, we want to give customers as much flexibility as they can in order to optimize the tool mix and also the EUV tool mix for themselves, right? So that's why the common platform, which also means that building those platforms can, in essence, happen in the same environment and the same type of cabins is so important to us. So that's what we're working towards. In terms of capacity, we have been working, as you know, in the past couple of years on creating sufficient capacity, both for Deep UV and also for Low-NA. So I think we have good flexibility there. To the extent that we need more capacity on High-NA, and that might be the case. We'll definitely have the opportunity to build the capacity there. But we will do it in such a way that, that capacity can then also be used to the common platform, right? So that's the decision that we need to take. We still have a bit of time there in order to see how customers are deciding on the exact composition. So we have time to do that. But I think we do have the flexibility in our model to accommodate that. Financially, you're quite right. In terms of revenue, it doesn't really matter a lot, right? So from a financial perspective, whether we take a High-NA tool or 2 Low-NA tools, doesn't have a huge implication for our financial model. In terms of the pricing on the high productivity tool, [indiscernible] to start negotiations with the customers on the tool that we're going to sell 8 years from now is probably not what we should do and definitely not in this meeting. And I think in the past couple of years, I think we have been able to get a share model with customers where we share the value of the tool, the incremental value of the tool with the customer in a fair way. And that has not led to a nice -- a very strong correlation between the throughput improvement, only one of the improvements because we give more value to the customer than just throughput improvement. But it's led to a very strong correlation between the throughput improvement and the ASP. We think that we can continue to deliver value. We think the value-sharing model will continue to happen. But exactly how that's going to pan out and whether the high productivity platform is going to give you the same linearity. That's a bit too early to comment on.

Francois-Xavier Bouvignies from UBS. I have a quick question on the layer count you described for logic. If I remember 2022, you said you expected 20 to 30 exposures for advanced logic. And now you are targeting the high end 25 to 30 for the end of the decade. Now the chart that you showed the most is the IME charts about the nodes and the improvement. And when you look at the pitch, metal pitch size, the 18-nanometer pitch size was supposed to be in '26 at A14 in '22. And now it's in '29, 2030 for A10. So you had the kind of a move on the metal pitch since 2022. So what is driving your confidence that you're going to get to higher end of the exposures when the road map of the pitch seems to go to the right. And also in the context of Christophe, you said that it's slowing down. And we know that your customers are doing a lot of improvement in terms of the layers as well, always to get more out of their exposures.

So, I'll first clarify the numbers, and then I think Christophe can take the specific road map question. So just to clarify the numbers. The 20 to 30 referred to the'25 and 2030 period. So the 20 to 30 was for the period of '25 to 2030. So that was not linked specifically the 20 to 30 to the year 2030. So you should not interpret the 25 to 30 by 2030 as an increase, right? The 20 to 30 was related to the 2025 to 2030 period. So just to clarify that. And by the way, and we also recognize when I gave the overview of the pluses and minuses, we also recognize there the slippage in timing in [indiscernible]. So that is consistent with the comment that you make.

Yes. And on the second part, so I think, first, we look at the 5 years horizon, which means that we have a pretty good understanding of where the road map of our customer goes in those 5 years. If we were to look 5 years beyond, it's a bit more complicated. So that's the first part. So I think the confidence we have on the number is also based on the fact that the level of discussion we have on this period of time is quite detailed. The second one, you're right to refer to IME road map. I think that's what I tried to explain a bit during the presentation. So for a long time, I think the advanced logic road map was driven by mobile application. And when mobile application was driving the road map, the justification to move fast to the next node was very difficult because the need for high-power computing was not there. The need for low-power consumption was there. So there was a bit of a different demand than what you see today where AI customers are, I will say, de facto now driving advanced logic. And their appetite for advanced node is pretty high. So if you look at 2-nanometer node, if you look who are going to be the first customer buying from 2-nanometer, those are the AI customers. The mobile customer will come a bit later. So there's been a bit of a changing of the guard, if you want, on who is demanding the most advanced application today in advanced logic. And that, I think, will create a dynamic that could a bit revert, but now I'm speculating. But you ask a technical question, so I give a technical answer. You could see basically the trend reverting a bit because mobile was kind of saying, well, it's okay, you can wait. AI is saying, no, I want it earlier because if not my cost goes like this and my energy consumption goes like that. So that's the dynamic we see. We talked about trend today. That's a trend we see. But like a lot of the trend, they have not fully played out in the market. But that's what I would call a positive trend. So AI driving advanced logic, if it remains like that will reserve as a much more aggressive road map in logic than when mobile was driving advanced logic. That's the bottom line.

Very clear. And my follow-up question is on the High-NA for memory specifically. To which extent 4F square might impact the insertion? I mean, do you think they would do both at the same time? Or if they decide to go for 4F square, does it change the timing of insertion you think in High-NA?

Yes. So I tried to explain that also in my presentation. The transition, you saw how complex is the whole transition in DRAM. I think our DRAM customers are mostly in the course of the next 7, 8 years have to make 2 major transition, which -- that's a lot. The transition will not be a cliff. That's the first thing to say. And they most probably be an attempt to try to push the existing node as far as you can. Now when you look at 6F square versus 4F square, if I oversimplify a bit, the cost of using EUV on either way, the difference between 4F square, 6F square is such that we don't see the transition having a major impact on us. That's a bit the way we look at it in our model because it's not a big change. So there, we see a very -- it is no way a cliff transition. It's a discussion you will have for many, many years to come. I think it will happen. So I think the whole industry think it will happen, but this doesn't change fundamentally basically the need for lithography.

All right. Maybe one from the online. A few here that are competitive based. Maybe this one to Marco. On the holistic lithography, you had e-beam in there. And e-beam, obviously, there's other competitors out there in e-beam. What is it that -- how is that competitive landscape? How do you describe it in a way where ASML has some advantage over being there versus, say, XYZ competitor?

That's a good question. I think if we look to the inspection side and especially to multi-beam, of course, we have been working together with our customers on the existing applications of voltage contrast. So that learnings that we had on the application, we took along and, of course, into basically introduction of multi-beam. So that's basically where we -- based on the application and working with customers, we could extend on that. And of course, we need to get the technology to be ready and to work for HVM. If you then look at the metrology side of e-beam, I think there, what I showed also in some of the trends, if we really want to characterize edge placement, we really need to have massive metrology. And that's there where our e-beam metrology actually is beneficial because we have a very large field of use. That means with very simple single acquisitions, we get a lot of data. And that's actually we showed also in some of the work we showed with customers, we get basically a lot of data at a very lower time, giving us the accurate edge placement maps that we need.

Very good. And maybe, Herman, this is also a competition question while we're on the topic. We know and ICON have been in the space for a while, but we also hear about Chinese competitors. Any comments on the competitive dynamic, whether it be inside or outside of China with respect to competitors?

Well, one way, of course, as somebody is playing catch-up with you is to make sure you're staying -- that you keep on moving yourself. I think that's a very important element, and I tried to show that also in my presentation. By keeping -- by staying -- keeping working on the cost, the cost for exposure, the cost of ownership for our customers, this is the way for us to stay competitive. And particularly in some areas, of course, also going ahead and while applying innovation, you need to learn, right? And in order to need to learn, you need to work with your customers. So for any new entrants in that market, right, it's going to be very important to learn. And we are in a very good position there. We have a huge installed base. So we are actually also using our service people, our application support to work with our customers actually, learn about what their future needs are and innovate based on that. So I think that combination puts us in a quite unique position competitively.

Very good. Roger, there's one here on share buyback. With the current stock price, are we looking to do anything accelerating the share buyback?

I feel like a broken record on this one. So the way we do share buybacks is we execute them when there is excess cash, right? And I think the excess cash, I think that goes back to the question that we had earlier on. So we do not opportunistically buy back. We buy back once there is excess cash. I mean that's our model, and that's what we suggest to continue to do.

Okay. We have maybe time for one last question. If you're -- Tammy?

Tammy Qiu from Berenberg. So the first one I have is about the 200,000 wafer start per month below 7-nanometer capacity addition every single year. Is that mainly relating to end market demand such as AI or that also include a big chunk of this geopolitical-related regional expansion as well? And how comfortable you are that every year, we'll add 200,000 below 7-nanometer, please?

So just to clarify, the 200,000 is -- I assume you refer to the advanced logic CAGR, which was shown there on the slide. And yes, that's purely driven by end markets. The 5% to 8% is strategic considerations on top of the end market-driven wafer demand.

Sorry, just a follow-up. So that 200,000 is driven by AI and smartphone, et cetera, for every single year. Do you believe that the visibility is good enough to confirm that 200,000 will be built and consumed every single year all the way through 2030?

So to be precise, I think it's 240,000 just to ensure I think I'm getting my numbers right. And yes, it is driven by the end markets which typically drive advanced logic are indeed servers, smartphones and PCs. But as you have seen in the end market view, it's clearly servers where bulk of the growth is coming from. And then, of course, that translates into a significant component of the growth in advanced logic wafers.

It is 200,000 based on the redefinition. Based on the redefinition, it is 200,000. But it's the same question we just had, and we saw it happen. We said we take a not too bullish stance on AI as we just explained. And we heard from the room, some people said, should it not be bigger. Also, I would say this is what we model on an average basis. Of course, there can be swings per year, obviously, right? So that should also be taken into consideration because at the end of the day, what we gave you is a 2030 view, right? We're not giving you a view for every single year. I think that's important to recognize as well.

Okay. Amazing. And lastly, on High-NA EUV. So you mentioned that the customer has been commenting that the progress is better than they thought. So are we going to see potentially some upside to the insertion layer you're estimating today if the tool is going better than expected? And worst-case scenario, if it's not going as per historically hoped in the next few years, are we going to see lower level of High-NA being compensated by a higher number of Low-NA tool? Or are we just going to see a potential delay of High-NA adoption?

Well, I think the answer -- the second part is if you don't use High-NA, you will need to use Low-NA. And instead of 1 mask, you will need 2 or 3 masks. So lower High-NA number will always translate into higher Low-NA number. Now on the upside, I think, of course, there is an upside because customers are just starting to expose wafer today. I think what Peter was explaining, I always say we were talking about the backlog before we had on High-NA, which is quite significant. And all those orders were placed by our customer without even having one data at hand. They started to get data since June. They have been extremely eager to generate data as quickly as possible so that they finalize a bit their strategy on High-NA. They decide also to -- for the foundry customer, bring this opportunity to their customer, right? So they get their process design kit also to their customer. And that create by itself more opportunity, right? And I would say, if customers continue to like High-NA, if they continue to believe as we do that there is a benefit in terms of cost, in terms of yield, in terms of lead time to use it, I think they will use it more. But we are just at the beginning of this phase where I think Peter said it very well in his presentation, data start to speak. Everything we have showed until now was just based on what I call the top-down models, which still makes sense. But now I think the data are starting to change the dynamic, and that's a very important time for High-NA for sure.

All right. I need to -- so let's formally close the event. Thank you all for your questions. And I'd like to also say that for any of you on the webcast, if you're unable to get your questions answered, please reach out to your Investor Relations team. For all of you here in the audience, obviously, we'll have opportunity as we go out for drinks and dinner here a little later. Now with that, I'd like to formally close the program. And on behalf of ASML, I'd like to say thank you all for joining us today.