Astera Labs, Inc. (ALAB) Earnings Call Transcript & Summary

Welcome, and thank you for standing by. I would like to inform all participants that this conference call is being recorded, where our company is presenting any recording may also be reproduced on their website. Views and opinions expressed by any external speakers on this call are those of the speakers and not of JPMorgan. Parts of this conference call may also be reproduced in JPMorgan Research. If you have any objections, you may disconnect at this time. Press participants are not permitted on this call and should disconnect now, unless otherwise permitted by internal JPMorgan policy, members of JPMorgan Investment and corporate banking are not permitted on this call and should disconnect now. I would now like to turn the call over to Harlan Sur.

Great. Good afternoon. My name again is Harlan Sur. I'm the semiconductor and semiconductor capital equipment analyst here at JPMorgan. Very pleased to be hosting the Astera Labs team for today's Tech investor webinar titled a Astera Labs as a Vision for expanding opportunities and infrastructure with UALink, right? It's a very relevant topic as AI compute models continue to scale in complexity, both training and inferencing AI compute clusters will correspondingly scale larger in size from a few hundred GPUs or XPs per cluster to a few thousands to hundreds of thousands, right? And a critical part of the performance of these AI compute clusters is the interconnect or connectivity between these GPUs or XPUs. These connectivity solutions require higher levels of bandwidth, low latency and other attributes required to synchronize GPUs or XPU accelerators at rack scale. UALink is an open high bandwidth, low latency connectivity architecture that forms the interconnect fabric in GPU or XPU rack scale architectures to tell us more about the UALink technology, good opportunity and how Astera will potentially lead this market. We have members of the team here with us today. Thad Omura, Chief Business Officer at Astera; Chris Peterson Fellow, Technology and Ecosystem at Astera and UALink Board Director; and Nick Aberle, Vice President, Treasurer and Head of Investor Relations. So with that, gentlemen, thank you for joining us today. And Thad, let me go ahead and turn it over to you.

Awesome. Thank you, Harlan. And thanks to all of those spending there afternoon and evening and even morning with us. I'm delighted that we've got a worldwide audience for this one. I'm Thad Omura, Chief Business Officer for Astera Labs and been here for the last 2.5 years leading our sales our marketing, our product teams and customer experience support teams and I've had the privilege to lead business teams at the forefront of driving new technologies to mass-market adoption, including Mellanox and RDMA technologies as well as early SSD and flash storage companies that includes companies like Sanforce and LSI. Now prior to Astera, I was at Marvell, leading their flash controller business and kicking off their CXL go-to-market plans. So continuing in the tradition of driving the market what's next, it's a pleasure today to share with the community Ultra Accelerator Link will expand opportunities in AI infrastructure. For many of you, UALink may be brand new. Our intent is to share the challenges we are seeing in AI infrastructure, specifically in the use case of scale up connectivity. My partner in crime Chris Petersen who is an active participant in the UALink community as a consortium Board member. He's going to take you through why UALink is poised to address these problems. Then I'll take you through how we look at the solution ecosystem for UALink and close with some final thoughts on the AI connectivity landscape from an Astera Labs perspective. Nick Aberle, who leads Investor Relations for Astera Labs is also on the line and is available at the end to help us field some Q&A. Please note that today's session contains forward-looking statements, including those related to AI infrastructure, activity and UALink opportunities and our response and plans and products. These statements are subject to risks and uncertainties described in our SEC filing and herein such as AI, demand changes, product development difficulties, all of these which may cause them not to come to fruition. Accordingly, we caution you to not unduly rely upon such statements. The information in this presentation is also as of today's date, unless earlier and earlier 1 is provided, and we undertake no duty to update unless required by law. All right. Let's dive into it. So those of you who are not familiar with Astera Labs, we are unique because since day one of the company being founded back in 2017, our mission has been consistent, and that is to provide purpose-built AI connectivity for infrastructure at cloud scale. Our founders identified that connectivity for multiprocessing AI applications would drive a significant step up, not just in the performance and low latency aspects of interconnect, but also in the reliability and the flexibility. And this would take place at a scale previously never seen in general purpose compute infrastructure. Now 7 years ago, it was not a question of if, but when. And we all know now the industry has answered that question. The when is right now. The company's product portfolio is really addressed to answer that when question and includes I/O and signal conditioning devices such as PCI retimers that have shipped to all the major hyperscalers and AI platform providers. Now we've built off of those to expand our footprint to include Ethernet retimers and now CXL controllers, these are all in production today. Then a watershed moment happened for the company, and this happened last October when we announced our first smart fabric switch products, and these products have put a Astera Labs in a totally different echelon of connectivity providers. We now provide all of our products at the ICE Board and modular level. And we've announced that we're expanding the portfolio to include both copper and optical media. All of our products are built on a software-defined architecture that enables a tremendous amount of flexibility and adaptability to customer platform-specific features. These soft layers are called COSMOS, which stands for Connectivity System Management Optimization Software. Now we integrate COSMOS and have -- and make it available for hyperscalers to integrate into their infrastructure management, so it's easy for them to gain visibility, telemetry, fleet management control, they can basically manage the entire data center where all of the Astera Labs products are deployed. And these software layers of COSMOS, they unify our entire intelligent connectivity platform so the customer experience is common across all the product families and generations. Now you heard me mention PCI Express, CXL and Ethernet. And today, we're here to focus on UALink, but it's worth noting that we recently announced we are a part of NVIDIA's NVLink Fusion ecosystem. Now this is really exciting because NVIDIA is extending their NVLink scale up infrastructure to custom, compute and AI processing XPU systems through this initiative. We are delighted to extend our collaboration with NVIDIA, given we've been a part of enabling multiple generations of their GPU getting to market with our PCI retimers for scale-out applications. We will participate by enabling select hyperscalers to more easily integrate their custom XPUs with NVLink through our connectivity technology that now includes I/O chiplets. The addition of NVLink to our intelligent connectivity platform expands the opportunity that hyperscalers have as we work with them to deploy next-generation scale-up solutions. In order to support all of the expanded product lines and protocols, we continue to scale the company worldwide. So I'm going to make a pitch, come out and check out the job openings on the Astera Labs website, we'd love to have you as we grow our organization to address all of these new exciting opportunities. Our comprehensive connectivity portfolio and our proven execution, these are what put us in a strong position to continue our close collaboration with all major hyperscalers, AI platform providers and really help solve their platform-specific AI connectivity needs. So before we go deeper into the presentation, let's make sure all of you on the call are clear about the terms of scale up versus scale out. When we refer to scale up, it means a bunch of accelerators that are interconnected in the effort so that they can all behave as one big supercomputer processing the same workload. And then when we talk about scale out, we're talking about a bunch of accelerators interconnected, but now processing a distributed workload. This means breaking up maybe a bigger workload into smaller tasks and then distributing them out. The reality is modern AI infrastructure, they actually use both scale up and scale out technologies to cluster computing resources because the jobs are so massive. So with that, what I want to do now is share with you how our intelligent connectivity platform support both scale up and scale out. Now state-of-the-art racks, they have multiple compute trays and scale up switch trays. Scale out and scale up connectivity often connect over a backplane that may be integrated right into the rack. They may be integrated through external cables or maybe it's some combination of both. But if you take a look at the compute tray, what we see are both CPUs and XPUs integrated on the same tray, and let me just be clear here, when I say XPUs throughout this webinar, we're using that term as a catch-all for GPUs and custom AI accelerators, okay? Now these compute elements, they're often PCIe connected through our Aries retimers and Scorpio P-Series switches, which are purpose-built for consistent line rate peer-to-peer modular traffic. These PCIe switches provide connectivity to scale out through NIC cards that can utilize our tourist Ethernet retimers and these retimers are used for active electrical cables for a top of the rack connection or maybe to a switch in another rack. We provide memory expansion connectivity through our Leo CXL controllers and our Scorpio PCIe switches, these are the devices that can be used for expanded SSD storage connectivity. And also recently introduced a new PCIe connectivity solution called a Gearbox, now this device easily bridges PCIe 6 to existing PCIe 5 devices in a very bandwidth-efficient fashion. And this example of what we're doing is we're efficiently connecting a PCIe CPU to a PCIe 5, and we're not wasting any of those valuable CPU IO lanes. Now let's focus on the scale up switch trade where Scorpio X-Series smart fabrics, which can be found, these switches, these are absolutely critical. They're platform-specific, low-latency switches, which connect multiple XPUs. Often, they're connected in parallel because what you're trying to do is increase the bandwidth of multiprocessing shared memory transactions amongst these XPUs. There's often a bunch of connections from these XPUs that run along the back lane to the compute trays in order to connect into this scale up fabric. And if PCIe or Ethernet-based protocols are used here, we have retiming solutions that help extend the reach of these signals, which can traverse a long distance over a rack's backplane. And in some architectures, we actually ship smart cable modules to drive those signals over active electrical cables. Now another way to look at what protocols we support is by looking at the scale-up and scale-out application and looking at it in a slightly different way. For scale out, we support PCIe, which is mostly on the actual compute tray board and then Ethernet for active electrical cable connections for network connectivity. Scale up now, we support PCIe and platform-specific products from a fabric perspective, and then our signal conditioning devices extend the reach of PCIe and Ethernet for XPU connectivity to the switches. Now CXL, CXL is used for connecting memory, and we can connect that to the CPU and both scale up and scale out applications happen to use expanded memory resources for -- through our CXL devices, and they can use this as required. Now I've just covered how we announced we are part of the NVLink Fusion ecosystem, and looking forward, we're excited about the opportunity to work with customers to connect their XPUs to NVIDIA's NVLink scale-up infrastructure through IO chiplets. And that being said, we're going to spend now the rest of today's webinar, really covering UALink and the challenges in this scale-up connectivity area that it addresses. Our goal is to expand our intelligent connectivity platform to support all of the leading protocols and solutions demanded by our customers to build optimal AI infrastructure. Okay. Now let's shift gears. We want to spend a little bit of time now to focus on the opportunity and challenges in AI as they relate specifically to scale up connectivity. The first opportunity has to do with the recent increase in compute demand due to inference processing. So previously, when we talked about AI compute scaling, we mainly focused on training. More training data requires more compute. It's pretty obvious. And the larger the model parameters that there are, they drive more valuable final model performance. But once the model was trained, inference processing requirements of large language models was fairly moderate, okay, especially when you're using the same cluster for training that you're using for inference. But as training continues and will always be a major driver for increasing compute demand as model sizes increase, what we have seen is the last and the latest reasoning models are driving inference to an inflection point. What's happening is the more valuable inference models are utilizing a multistep processing model, which is accelerating the demand for more compute by orders of magnitude. OpenAI's 01 model. This was just introduced last fall. And this was the first model to really use the so-called chain of thought processing to derive better and better results and we've seen this trend accelerate. Now this increase in AI inference compute demand is a huge opportunity for the industry as it delivers higher value AI applications. At the same time, it's considered one of the most challenging problems to solve because large cluster scaling is directly related to solving scale-up connectivity issues. The next major challenge we continue to hear about is return on investment for the massive hundreds of billions of dollars being spent on infrastructure that are all happening worldwide. Now across our customer base, we continue to hear about power consumption and cluster utilization. These 2 issues are being -- they're so critical when you start talking about where the resource is being spent and likely being wasted. The efficiency of the scale-up fabric has potentially the largest impact on infrastructure profitability and represents a significant challenge that must be addressed to improve TCO. And now we're also seeing many more specialized AI accelerators emerge that are purpose-built for very specific AI workloads and models. Now the challenge here is to integrate all of these XPUs into cloud infrastructure and the cost to align and specify a scale-up fabric or all of these different architectures is extremely high. Optimizing a scale-up connectivity solution to be used with a single accelerator only to have to rearchitect for a newly introduced XPU months later, this is a huge challenge because it's a huge cost investment, low time to market. So it's now, as we look at like all of these challenges, it's incredible to think, all of these AI infrastructure challenges, they're all related to scale up connectivity. And why now as you take a look at these challenges, is it the right time for a scalable, efficient and open connectivity solution Okay. So you may be asking yourselves, we're talking about scale connectivity in reference to UALink, Like, why is now the right time for such a solution? And a couple of things you can recall is that in the general computing market, scale up connectivity is used. I mean we see 2 to 8 CPUs being scaled up in these general purpose compute servers all the time. Now these processors are connected in the box. And therefore, CPU vendors have really not had the need to open up or share the protocol. We've seen UPI from Intel and Infinity Fabric from AMD, these are at this point in time and proprietor. They leverage a very simple memory semantic protocol, optimized for low latency memory sharing. We're going to cover more about this term memory semantic shortly because it's a big one, okay? And we want to make sure the audience understands it. But just think of the protocol interface is super optimized for a really, really small number of end points. Now this model continued as we started to see AI servers built to address the initial GenAI air of computing. In these platforms, we see eight GPUs utilized and it's basically the same proprietary and simple memory semantic scaleup protocol. But what we are now embarking on is a whole new era of AI server architecture. This is where the number of GPUs and XPUs are scaling to be much larger. We are quickly seeing a transition where the server, which was previously really confined to a single system and platform. We're seeing that this is now moving to an entire rack and in some cases, multiple racks. And the only thing that really is changing now is it's not just a CPU or GPU to GPU connection, but they're actually being connected into a switch fabric. Now we know deploying 72 GPUs on a single cluster today and already signaling 576 nodes right around the corner. We see this trend continuing, especially as AI compute demands are increasing. We're going to see this trend continue and spread to other XPUs. Scale-up connectivity is no longer limited to a box and we're now connecting XPUs throughout the rack and expanding the rack to rack to rack through switches to make hundreds of XPUs look like one single powered XPU. And then, of course, we will continue to use scale-out technologies for multi-server processing models. This is going to happen over a network in the range to tens the hundreds of thousands of nodes because that's what these protocols were built for, things like Ethernet and InfiniBand. They were built for hundreds of thousands of nodes. To summarize, we're seeing the transition to rack scale architectures, coupled with the integration of switch fabrics for large scale-up racks or what are now called pods. These forces are driving the demand for an open multiprocessing rack-level scale-up solution. So what is the answer to this. And, here we go, the industry has responded, what you need the UALink consortium. So at Astera Labs, we are a proud Board member, and we are invested to advance this initiative forward, along with hyperscalers and the industry's biggest technology giants. The mission, the mission is to drive an open accelerator communication protocol in the market. We're leveraging what has worked in the past in terms of a simple memory semantic-based protocol. We're initially targeting to connect up to 1,000 XPUs to be scaled up. Certainly, early deployments will start with less. But what we're doing is by limiting the scope to single-tier switching architectures, we're leveraging the existing Ethernet data rates, along with the low latency assets of PCIe, the consortium is now really focused on efficiency and low power. And by keeping the protocol simple, we also expect to accelerate time to market and build a strong ecosystem for all of these specialized XPUs in the industry. Now the organization -- we're moving forward very quickly here. And UALink was just incorporated back last October. And already through open collaboration with the members, UALink released its first protocol specification back in April. This is just a month ago, supporting 200 gig per lane and 800 gig per port. And what is so exciting about the consortium is that the level of innovation is really starting to emerge. The group is targeting to release a UCIe-based IO chiplet specification to speed the integration of UALink to XPUs, and already, the group is working on additional scale-up features that support in-network compute for specific multi XPU calculations that can dramatically be sped up by centralizing those compute functions in the switch itself. Now the goal of all of this innovation is to enable a purpose-built scale protocol for AI at rack scale. So now I'd like to hand over the webinar to Chris Petersen, Fellow here to Astera Labs, who is also our CXL Board representative. He will dive one step deeper into how UA Link addresses all of those scale-up connectivity challenges I previously mentioned. Chris take it over.

All right. Thank you, Thad, and hello, everyone. I'm a fellow at Astera Labs and have been here for the last 2 years, leading our technology and ecosystems team. Prior to Astera labs, I spent more than a decade leading the technology road map and architecture of servers, storage and silicon at Meta for their cloud infrastructure. I also represent Astera Labs on the UALink and CXL Board of Directors. Let's first quickly recap those challenges we're seeing as related to scale up clusters and connectivity. Large cluster scaling remains a huge challenge. As you add more and more XPUs to the cluster, we want to make sure that the full performance of each added XPU accelerates the workload processing in a very linear fashion. The issue is that as hundreds of XPUs are scaled up, connectivity and efficiencies can limit scaling of the entire cluster's performance. Those same inefficiencies can have a huge impact on power consumption and the utilization of the cluster. With billions of dollars being spent on AI infrastructure, the entire profitability in TCO benchmarks are constantly under pressure. And now with so many specialized and diverse XPUs coming to the market, it's extremely expensive and time-consuming for hyperscalers to take full advantage of these incredible AI processing innovations. We're addressing these challenges head on with our work in the UALink consortium by defining and driving to market the industry's first open and purpose-built scale-up protocol. My intent over the next few slides is to take one step deeper into the features UALink provides and how those address these critical challenges. First, let's start with how UALink is purpose-built to enable highly efficient cluster scaling for hundreds of XPUs. That previously used this term memory semantics, and it's an important fundamental architectural decision that we've selected for this protocol. So what does memory semantics mean? Memory semantics means that the exact same simple read or right command an XPU Core or a compute element in the XPU uses to access its local memory is the same direct command that is used to access the memory attached to any other XPU in that cluster connected on the switch fabric. In other words, the access mechanism is exactly the same. This simple, same tried and true model for multiprocessing connectivity that we've been using for many decades at a smaller scale in general compute applications that, that has just walked us through. So we're building from that. In the past, these multiprocessor protocols were proprietary. What we're now doing is standardizing the same access model so that it can be used at a much larger scale for AI clusters, while still maintaining very low latency and high cluster scaling efficiency. Now you may be wondering, how does this differ from some of the other standard connectivity protocols that already exist. PCI Express is widely deployed, and we have many customers using our PCIe connectivity solutions today, building cutting-edge scale of fabrics, as Astera Labs will continue to support applications for generations to come on PC Express. That being said, PCI Express supports a much broader set of use cases and UKLink aims to really standardize and streamline the complete end-to-end scale of protocol. Another approach used in the industry for this is called Network Semantics, which is widely used by Ethernet-based connectivity protocols. As Ethernet is designed for topologies that can scale to connect hundreds of thousands of nodes, there's a lot of additional addressing and routing information that has to be added to every single data request. This fundamental difference is what drives UALink to be much more efficient for multiprocessing applications versus those Ethernet-based protocols. The end benefit is ultimately the ability of the clusters to continue to scale efficiently with UALink. Cluster efficiency is the most critical factor to scale performance with this oncoming wave of highly compute-intensive AI workloads, including reasoning inference models. These reasoning and chain of thought models demand orders of magnitude higher levels of compute power and UALink is purpose-built for these applications. Just as the protocol has kept each memory transaction to its simplest form its most native and direct form. We've also defined the switching architecture to be extremely simple. Because this scale-up application targets a relatively small number of XPUs, we have confined the first UALink specification to only support a single tier of strain, plus each memory transaction consists of a very small fixed size data transfer. This combination optimizes the entire switching function and keeps it simple. In comparison, network semantic protocols support multi-tiered topologies with variable packet lengths Keeping the switching implementation simple is what ultimately results in a consistent and responsive user experience in these multiprocessing scale-up environments. This is yet another key feature of UALink that facilitates this large cluster scaling. One of the strengths of an open ecosystem is that the UALink consortium is taking the best ideas from its members and collaboratively working on these new innovations. It means the members are committed to developing scale up interconnect specifications that accelerate the deployment of these advanced features. We've already embarked on an IO chiplet specification, which will further accelerate the deployment of UALink across a diverse ecosystem of XPUs. And we're also looking to further boost the scalability of the cluster itself by having Work Switch perform compute functions called collectives. Certainly, if these features are deployed by individual XPU vendors the adoption and deployment of these innovations will be limited and at a reduced pace. Ultimately, the UALink Consortium is driving a scale of protocol to market that is simple scalable and open, which can be used across this growing landscape of XPUs. Now let's take a look at how UALink optimizes the efficiency of the infrastructure to ultimately optimize total cost of ownership. Since data transactions are optimized for multiprocessing, we're able to minimize the amount of addressing required for each of these memory transactions. It means that every single data transaction that is sent over this fabric carries a high percentage of actual data that needs to be processed or Ethernet-based protocols, there's a large amount of additional addressing information that consumes additional fabric bandwidth, means that for small memory semantic data transfers, a lot of this bandwidth is wasted and considered overhead. UALink, on the other hand, is built to maximize the XPU performance through very high link utilization. The purpose-built architecture and simple stack design of UALink also has a positive impact of inherently requiring less silicon dye area to actually implement. Whether you're considering the XPU or the switching silicon solutions, smaller dye sizes will ultimately optimize system acquisition costs or allow you to allocate more dye area for additional compute. And of course, efficient silicon translates directly into lower infrastructure power consumption. Power consumption remains one of the largest barriers to larger scale AI infrastructure build-outs. By consuming lower scale-up fabric connectivity power, rack-scale architects are able to allocate more power to XPUs and consider higher-density rack scale designs. We're very excited to see how these UALink optimizations are able to directly impact the utilization, cost and power of the entire AI infrastructure. UALink allows us to address these critical TCO challenges at a very large scale. The last major challenge UALink addresses has to do with the high integration costs and the slow time to market of the oncoming wave specialized XPUs that are coming to market. As AI workloads are better understood, more purpose-built solutions that can optimize XPUs for particular workloads and data center environments are continuing to emerge. The obvious benefits of a standard specification is that multiple XPUs can benefit from utilizing the same scale-up infrastructure. Additionally, hyperscalers can unify their infrastructure, knowledge and investment around a common scale of framework and streamline the deployment of all of these different XPUs. It also means that from a system vendor perspective, builders have this opportunity to select from a best-of-breed component ecosystem that is fully interoperable. There can be a wider range of solutions offered to the industry in terms of switch port count, lane counts as well as variation on the bandwidth per XPU that each of these racks is ultimately configured to support. All of this variation is enabled only if end customers have the confidence that this solution will truly be interoperable. One of the growing concerns that the entire industry faces is with the ongoing challenge of shifting supply chain dynamics for this AI infrastructure. We're seeing the need to remain agile with manufacturing locations and the optionality to multisource different vendors for each of the AI rack scale components. Multiple vendors can now come to market with interoperable compute and switch tray solutions for these racks as the RAC infrastructure itself can now be common. One of the key issues we focused on from a UALink consortium perspective is driving an open, interoperable standard for XPUs that supports a very resilient supply chain. So there was a ton of information about what UALink is about and how we'll address the major scale of connectivity challenges in the industry in a very short amount of time. So to summarize this information, we put this chart together to specifically compare how UALink compares to Ethernet-based alternatives, but also fall under the umbrella of open standards. UALink leverages the same data rate as Ethernet, while at the same time, remaining simple and purpose-built for scale-up applications. Unlike Ethernet, UALink is built with a simple memory semantic protocol that's focused on connecting hundreds of nodes together with ultra-low latency. Additionally, by reducing switch complexity but still providing equivalent bandwidth, UALink provides consistent and scalable performance. This ultimately maximizes the fabric utilization streamlines the silicon implementation lowers acquisition costs and power consumption and ultimately facilitates the wide, fast deployment of XPUs across the industry. In short, UALink is open and purpose-built for the most demanding AI scale-up workloads with the bandwidth of Ethernet, but the low latency of PCIe and simple memory semantics. On behalf of the UALink Board of Directors and the membership, I'm very excited to be part of this industry-wide initiative, and I look forward to contributing to even more innovation as we drive AI scale products and solutions to market. With that, let me hand the webinar back over to Thad to cover how we see the UALink connectivity solutions ecosystem evolving, the vision for UALink and some final thoughts from Aa Lab's perspective. Thad.

All right. Thanks, Chris. So now that you've heard about UALink and how it solves major challenges related to scale-up for AI platforms. Let's take a look at the solution landscape. Now I'm going to warn you I know there's a lot of investors on the call today. So what I'm about to build out for you, this is an example to apology, okay? It's illustrative, and it would be very unwise just to drive attach rates and volumes from what I'm about to show. But hopefully, you'll get an idea where all the different components for UALink are going to go. Let's start first from a RAC perspective. We'll continue to have compute and switch trays. Now the obvious first components that are critical to UALink is the switch silicon that will reside on the switch trays. And depending upon the rack architecture, talking 200 gig per lane signal conditioning devices are likely going to be required to make signal reach robust. We know the compute trays will contain XPUs. And each one of these XPUs will have multiple connections to all of the trays. This is your scale-up UALink fabric, which makes many XPUs look like one big XPU. Now to facilitate easier integration of XPUs into the UALink fabric, the consortium is working on an IO chiplet specification that utilizes UCIe from a dye to dye standard for connecting directly into the XPU. These chip lifts, they're going to help target faster integration of XPUs into the UALink switch fabric and provide connectivity to all of the switches. Now we know the industry demand scale up beyond a single rack. We want more XPUs than just a single rack can hold. And so we see rack-to-rack scale-up solutions that are evolving very quickly. What we're going to see both active copper and eventually optical connectivity solutions that will be critical for these rack-to-rack scale-up solutions. And last, but certainly not least, the management software, if you think about all of this infrastructure being put together, the management software is which so critical to make the solution ecosystem really all work together. Now whether this is switch management software or it's cluster management that provides telemetry and cluster utilization information, all of this software is an essential component to the UALink ecosystem. And when you put all of these components together, it will be a multibillion dollar connectivity opportunity. Now you've learned about UALink, the ecosystem of solutions, let's start to conclude with the vision for the technology. Now today, we see XPU deployments. They're directly tied to the scale of fabrics that are selected at the beginning of the XPU development cycle. Given the long time to market, we see these solutions are often incremental R&D work by the XPU vendor itself or there may be limited vendors to work with. So one of the other areas that we are looking at is that the innovations that are made of one XPU architecture or platform, the challenge is those are not easily translated to different XPU solutions. What UALink is driving is an ecosystem where the XPU development can be kicked off and aligned to an open scale protocol. And as the XPUs develop, innovation to the UALink fabric can still happen in parallel, different team of resources. Now what this is going to enable is an expanded list of vendors to support scale-up deployments with greater optionality for configuration, scale and performance. The UALink vision is to accelerate time to market for a data center that leverages heterogeneous XPUs that are target and optimized for specific large-scale AI workloads. So supporters of UALink, well, Supporters all believe in an open standard where the technology is purpose-built for scale-up and all the innovations that can be integrated into the fabric, those can all be applied to multiple XPUs platforms and design. And now I'm going to bring this back to Astera Labs and our direction to be the leading supplier of connectivity solutions for AI at rack scale. We're going to continue to add new product lines that accelerate and optimize both scale out and scale up AI connectivity applications. And this will be for rack scale compute, switch tray applications, and we are delighted to work with all of the major hyperscalers and platform providers with our connectivity solutions. Our platform integrates IO now chiplets, signal conditioning solutions, controllers and fabric devices, and we're going to deliver these in terms of IC board, modular form factors, module form factors and chiplets. And we are shipping to production connectivity solutions that support PCI Express, CXL and Ethernet. All of these products are managed under our common COSMOS embedded software and API framework. Our software is what unifies our intelligent connectivity platform and provides a consistent development and customer user experience across all of our products. Today, we spend and shared the opportunity and vision for UALink. We are excited about this opportunity and the industry initiatives that bring forward advancing a complete portfolio of solutions which is what we plan to do a complete portfolio of solutions around this open scale-up technology. And our goal is to work with the industry on really providing the connectivity solutions through the fabric of their choice. To that end, we're delighted to now be a part of the NVLink Fusion ecosystem, we're looking forward to working with customers who want to leverage their NVLink infrastructure investment for their own XPUs and provide connectivity solution that happening. Ultimately, our goal we're here to build the most comprehensive and complete portfolio of connectivity solutions for an increasingly diverse set of XPUs and AI accelerators that are all driving the next wave of AI rack scale deployments. So I want to thank Harlan. Thank you, Harlan. Thanks to you, the JPMorgan team. Thank you for hosting us, giving us this opportunity to share with you our thoughts on the UALink market vision. Hopefully, you gained some insights into the challenges it addresses the technology and, of course, the value proposition and market opportunity. We at Astera Labs, we have a vision to deliver high-performance connectivity for the entire rack, whether it's from the GPUs, custom ASICs and accelerators. As we cover today, modern AI workloads are driving the need for high bandwidth, low latency, scale-up connectivity that supports memory semantics. We are committed to drive and accelerate our efforts behind UA Link for this open multi-vendor scale-up solution, and at the same time, excited to have recently announced our collaboration with NVIDIA on the NVLink Fusion ecosystem. We continue to work with XPU vendors on their platform specific connectivity requirements, and this provides them with a full portfolio and complete optionality in the solutions that we can support them with. And as the market for connectivities continues to grow and diversify, we are excited to be well positioned to benefit rapidly expanding market. Thank you. So what I'd like to do now is hand it back over to Harlan and maybe we can take some Q&A.

Yes. Thank you, had. And that was a great overview of the A link technology opportunities, some of the challenges that you're trying to address with you a link that the industry faces. So I appreciate the great overview by you and Chris. As you mentioned, I've got a few follow-up questions for the team, while we have a few minutes left here. So I'll start off with, when the team introduced your Scorpio family of PCIe and XPU fabric switching products in October of last year, right? You quantified the 4-year market opportunity at around $5 billion. How does that break out PCIe switching versus XPU fabric spotting. And within that, how big do you think the opportunity is for UALink?

Harlan, I can take that question. So let me start by saying that UALink, I guess, for that matter now, NVLink both represent incremental market opportunities for Astera Labs relative to what we had previously outlined. So -- maybe we need best to quickly frame the market opportunity set that we previously provided, and then I can discuss the new addressable market opportunities that are unlocked by UALink. So if we go back to last October, we launched Scorpio Smart Fabric Switch family, and we provided an estimated total market opportunity for that product family of approximately $5 billion by 2028. So if you break down that a little bit more per your question, we stated that roughly half of that market opportunity was going to be addressed by our Scorpio P-Series fabric switches, designed for mixed traffic AI head node connectivity applications. So for that being scale-out connectivity between PCIe hosts end points. And then we stated the other half of the $5 billion TAM estimate was addressed by our Scorpio X-Series fabric switches with the primary application there being accelerator to accelerate or scale up connectivity. So that's kind of the high-level brief what we had previously announced for Scorpio fabric switch family TAM specifically. But I think it's also worth pointing out there's also actually a big scale up market opportunity for our signal conditioning portfolio as well. This would include opportunities for our areas in tourist product families as customers look to leverage PCIe, ethernet or even customized versions of each of those scale up to scale up their AI accelerator clusters. So we have already seen good traction within those applications. A great example is the strong growth that we've seen in our Aries SCM business over the last couple of quarters. But moving along to the additional UALink opportunity. So as I outlined, the previous $2.5 billion market opportunity, for scale-up connectivity application with special Scorpio X-Series family and its support for PCI Express and customer PCIe-based back-end technologies. So it excluded the potential opportunity for other protocols being leveraged for scale-up connectivity, whether it's Ethernet, proprietary protocol or now in NVLink. When we reported earnings a couple of weeks ago, we highlighted on the call that the potential adoption of UALink would unlock an incremental multibillion-dollar connectivity opportunity for us by 2029. And so the assumption here is that UALink will address additional scale-up connectivity, application opportunities above and beyond what we currently address in the PCIe market with both Scorpio X-Series and Aries. And then from a product perspective, I think one more thing, I hope we've hammered home today, and I think Thad did a good job of this, is that we are approaching these markets with the rack-scale mindset. So one of the main takeaways should be that a sterile Labs opportunity within the UALink arena will be addressed with a broad and holistic set of solutions, and this holistic solution set will drive the proliferation of UALink across the AI accelerators and should ultimately provide us with silicon dollar content opportunities, which we think will be in the range of multiple hundreds of dollars per accelerator. So net-net, UAL unlocks a new and meaningful content opportunity, and that's going to be across unit TAM that we were not previously addressing

That's perfect. And then my second question the team outlined many benefits of the UALink standard for scale up clinic applications. If you can just highlight maybe the top 1 or 2 key attributes that you believe will ultimately drive the proliferation of the UALink protocol.

Sure. I can take a shot at this one, Harlan. So Link essentially, from my perspective, wells down to 2 key benefits. The first one is that it's really focused on providing the bandwidth of Ethernet, but with the very low latency of PCIe and native memory semantics. So that's one. The second here really is that it's open, it's standardized and it's interoperable with a rapidly growing ecosystem and a roadmap of more features to come that will continue to enable further cluster scaling.

Perfect. And then you had mentioned the quick time to market as it relates to incorporation of the UALink consortium all the way to the recent ratification of the 200 gigabit per second 1.0 specification that was released in April. Do you believe that the adoption of UALink will happen with the 1.0 specification or that was released in April? Or is the industry you think going to need additional updates that are potentially going to be required to drive more prolific adoption of UALink.

Yes. I'll take this one as well. Good question, Harlan. So the 1.0 spec that was released last month, it's a complete stack, right? So it's fully implementable, and people have been building to this already for some time even before the spec was publicly released. So there's already an ecosystem of people working on the IP and the core components to be able to go build the UALink infrastructure. And we fully believe that the 1.0 products are going to be complete and coming to market. Having said all of that, there's more innovation coming from the UALink consortium and the ecosystem. And there's a very strong roadmap that we briefly touched on today. And two of those items that we mentioned are this IO chiplet specification, which having a standard pack for this, of course, really accelerate the adoption of UALink in the XPU environment, especially with all this diversity that we've got going on because people will be able to just integrate these chiplets much more quickly and expect the scale-up infrastructure to come along with that. And then the second here is this concept of in-network compute. So if you think about this, if we start adding some compute capabilities within the switches, now we have this further scaling factor that we can apply to these networks, to these clusters which will allow us to continue to scale the bandwidth per XPU and get even more cluster scaling as a benefit. And of course, we get better AI infrastructure efficiency out of that as well.

That's perfect. And then going back to the initial discussion and good to see the recent support and participation by the Astera team the announcement of NVIDIA introducing its NVLink fusion, right? Essentially offering his scale-up in NVLink architecture, IP, chiplets to be integrated into non-NVIDIA-based XPUs and obviously, Astera is an ecosystem partner, NVLink Fusion. Can you guys just talk a little bit about that announcement? What it means for -- I know that you talked about the triplet I/O architecture that you're going to use to offer as a part of the NVLink Fusion portfolio. But can you guys just talk about the announcement and what it means from a UALink initiative perspective? And what it means for just overall scale-up connectivity segment of the market.

Yes. Maybe it's best if I take this on this question quite a few times over the last 36 hours. So I think to start off, what we see in the market today is that XPU developers already have a multitude of options to adopt for their scale-up connectivity backbone. We see customers leveraging PCI Express. We see them leveraging Ethernet, utilizing other proprietary interconnect technologies for their accelerator to accelerator clustering applications. So the introduction of NVLink Fusion interconnect technology into the custom ASIC AI accelerator market, will now be an additional option for XPU developers to consider as they're making those scale-up connectivity decisions. And I think another thing probably worth pointing out is that all of these XPU developers have their own differentiated technology portfolios and capabilities. They also have their own unique connectivity goals, which are typically tied to their specific business models, and then also the workloads that they're trying to process. So the NVLink Fusion ecosystem now represents a solution set for customers looking to leverage the existing NVLink infrastructure to drive robust scale-up performance, and as Thad mentioned, we're super excited about being part of that ecosystem, helping to enable XPU developers to access NVLink interconnect technology. With all that said, our expectation is that there will also be strong demand for a purpose-built open industry protocol for scale up of connectivity. UALink will look to fill that demand. as an open standard, driving low latency, high bandwidth and need of memory semantics for a scale-up connectivity, and we believe it's poised to be adopted across a broad range of AI accelerators over time. For Astera Labs specifically, our goal is always going to be to support our hyperscaler enterprise AI customers with a diverse set of products and capabilities across multiple approaches to provide open-ended optionality, fast time to market and best-in-class performance. So overall, we're excited about the broad expansion of the purpose-built scale connectivity portfolio, with support for NVLink, UALink and PCI Express, PCIe Express and view all of these avenues as opportunities to support customers and to grow our business.

Yes. And I would agree with you that there's multiple optionality for our customers, although I would also agree that the bias over time would be towards more open architectures like the UALink protocol. That being said, there was a recent announcement of a new type of scale-up architecture also open as well called the scale-up Ethernet or SuE Protocol. I'm just wondering how does the UA linked protocol compared with just recently introduced scale-up Ethernet architecture?

Sure. I'll comment on this one as well, Harlan. So in the past, there have been multiple attempts at building some form of Ethernet-based scale-up solution. So this is just the latest in that series of attempts. The challenges that often these are built from a single company solution. And ultimately, UALink provides the simple, efficient and low latency scale-up solution but it's also an open and standardized solution. So that means the specification is driven by multiple companies working closely together to build this detailed and implementable specification and is built around interoperability as well, which is absolutely critical to make this ecosystem viable. So this approach that we're taking with UALink really allows the scale-up solution to not be unique to any one particular company in their specific implementation, but it allows us to build this robust ecosystem and then continue to build off this robust ecosystem as we continue to advance the innovation with this back.

You guys talked about the merits of UALink standard, right? But can you just maybe a little bit of a deeper dive into why the Astera team is specifically well positioned to deliver solutions to support the ecosystem what products are you planning to introduce? And more importantly, when do you believe systems based on UALink will be introduced and deployed in volume scale?

So let me take that one. So we just are labs, we really pride ourselves on our deep engagements with the hyperscalers, the platform providers and really working with them on roadmaps for products that service their needs, their platform specific needs. And in regards to the portfolio, we went through a whole kind of ecosystem of products that are going to be available to drive the UALink market forward, we plan to provide the most complete and comprehensive portfolio for UALink moving forward, And that's kind of our intent. And in terms of just getting customers and seeing this technology be deployed starting from kind of mid to second half next year, we're going to see platforms being brought up on the technology being qualified for production. And then really, we start to see deployment in the 2027 time frame.

Perfect. Well, we are just about out of time. I want to thank Thad, Chris, Nick and the entire Astera Labs team for this informative session. Look forward to monitoring the progress of the team and helping the AI infrastructure ecosystem adopt the UALink technology. And to all of the participants on the call, thank you for joining us this afternoon. A replay of this call will be available on both JPMorgan markets as well as Astera's Investor Relations website. So thank you, everyone. Have a great week.