BE Semiconductor Industries N.V. (BESI) Earnings Call Transcript & Summary

So welcome, everyone. Before we start, I would also like to welcome the participants from a distance. That we don't see or we don't hear, but who are listening into the call. Welcome. I was told it's 46 -- sorry, 70. I don't know where the number of 46 comes from, but anyway, so it's supposed to be 70 additional. So welcome. I hope you had a good tour that you got some more detailed impression of our different beautiful machines, also some thoughts beyond developments, where we're going. And now we will summarize that with a presentation or a set of presentations, one about Besi in general. Number two, about, of course, the famous, hold on I have to push this button. The safe harbor statement to repeat that also for our friends online. This is an Investor Day concept. So this is not a market update. All the information we share is the information either generally known to the public or it is assumptions we base on customer inputs. But this is not about our guidance. This is not about Besi's quarterly business. Anyway, here we go. Our agenda for today is first, a few words about Besi. Number two, is our technology trends and market trends, we call it. So our CTO officer, Chris Scanlan, who you have met in the group you were? Or if not, please Chris stand up. That's Chris was also here last year. Anyway, then we have Peter, who has the honor to present our wafer level, progress, hybrid bonding, DC, but also other concepts in those applications. Then we have Mainstream Die Attach, Christoph. Christoph you have also met, who is standing in the back. And then we have a Q&A session. But let me quickly start with the Besi update. So what's happening in this world? Well, not a surprise to you. AI is driving the bus and the bus is going faster and faster, with more and more stops, with more and more developments, which should evol is right by the outside analysts drive this industry to significant higher levels than we have witnessed ever before. Assembly has become from a necessary evil or the flea on the dog's tail. That's how I was brought up 30 years ago in this industry to a key enabler to further integrate on chip level and to create interconnects, which are at chip level. So assembly has grown in importance and we will share with you many of those developments, which will be critical for growth in the years to come. Although it's still early stages, we are in a component world. But ever more on chip level, we can connect and based on that connecting on chip level, we can create much faster circuitry, use less energy and especially where it is about manipulating data. We need to offer solutions which generate less heat, faster circuitry. And the enabler for that is hybrid bonding and to some extent, also TCB. But anyway, 35% to 40% of our orders are coming from this new technology world. Many of you may have concluded already with the ongoing reporting quarter-by-quarter, the last quarter end of April, where although the industry is in a major, let's say, downturn, Besi still performs very well in that downturn simply because our successful focus on the forefront of this advanced packaging technology. We service the major or the leaders you can say in this industry for those devices and the adoption is spreading from logic also gradually towards the space of memory. Anticipated ramp of both combined in the most advanced applications is getting closer to 2026, '27 is expected by outside analysts to be the kickoff of those modules using hybrid bonding technology. We've seen orders for 2.5D capacity began on a larger scale in the second half of last year. Particularly for CoWoS but also photonics but more about that later in the presentation of Christoph in particular, but also, Peter, and we will also, from a technology background, share with you what is driving this and what are the unique opportunities for Besi. Memory customers are certainly pursuing a dual strategy in this next generation, trying to further stretch existing technologies in reflow. Some in mass reflow and then gradually towards the transition for hybrid bonding simply because the geometries force this transition apart from the big advantages of energy savings using hybrid technology versus the reflow process. Besi further expands its R&D, which is, of course, a no-brainer because of all these wonderful challenges in AI. If we look at this chart, it tells you the forecast in the years to come. The source is Yole where it's clearly predicting a major growth and well above the average for the industry. Both were 2.5D/3D with advanced packaging in particular. And that is where Besi's focus has been for the last 30 years. If we look at what I already said earlier. It's amazing that in this industry, we all thought after cover supply chain issues. Yes, the virtual world, which changed society forever. So at that time, in 2021, '22, the sky was absolutely the limit. But everyone forgot that the world always comes back to models, which we have used in the past. Of course, some new models but in general, that meant that this industry had an enormous overcapacity and different from past cycles where usually 6 to 8 quarters. The industry would absorb an overcapacity. We are now faced with a bit longer, which is also not unusual. We had that in previous cases. The IT bubble, for instance, but also other moments in time. But anyway, it is what it is. But as discussed earlier, for Besi that offers unique opportunities to also grow significantly in new technologies. It's expected that this tight turns although if you look at the latest independent research analysts, they all take their model somewhat down for 2024, maybe too much looking at statistics and reality is catching up. So if we look at our customers, the whole infrastructure in this industry, H2 is expected to be better than H1, but still with some caution. Anyway, general information. If we look at our performance in this downturn, I won't go over the details, but in any case, reaching gross margins of well above 65%. And a situation where revenue is more than 30% down, tells you that our operating model is as unique as our technology development. So in any case, that gives us an enormous confidence in to develop this business in the years to come. Capital allocation always has been strong last year. Very significant returning over EUR 430 million to shareholders. In total, in the past 10 years, I think it is now about EUR 2 billion. Anyway, technology is what counts, and we are definitely enjoying at the forefront of next-generation technologies, wonderful positions. And if that continues, that can offer us a much stronger growth than what we have witnessed in the past. This is to remind you that this industry back to 2006. Can you imagine we acquired Datacon here where we are in 2005. And if you look at this wonderful revenue per quarter development, it definitely tells you that this is a cyclical world, and that won't change. But at the same time, you see the continuous development in downturns, preparation, upturns, demonstrating ever higher margins. That means our focus on customer developments, pick the winners is one of our major let's say, strategic focus is never ending. So pick the winners in the three categories: communication, data and automotive. And at the same time, continuously improve our operating model. Our operating model in that sense is unique compared to others in the industry, multiple sourcing from the start. But then also through contracts, which enable us the flexibility, both in upturns where we grow significantly faster than the average in the sector. But also in downturns to maintain our breakeven cost at the lowest levels, but adapt the cost that we maintain margins, which are better than we have performed in previous cycles. So that also is very important to understand about Besi's performance. If we look at this slide. It helps you to understand who is doing what. We'll let's say, remind that every single day that this industry is preparing for a next major upturn, but that's in every downturn case. But this time, it's even more than that. If you look at the massive investments announced by the leaders in this industry, and especially for 2024, where we are today, that tells you that it's based on a market which in the end, also needs assembly. Otherwise, these fronter fabs are not of much use. But in any case, a major investment in capacity in all technologies, and that is what is for new technologies basis unique opportunities. This was too fast. State of the industry, what is important at this time, and I want to point to you here on this slide at the right side. That we have, for the first time, a very significant imbalance between value, revenue and inventory. And that is one of the problems. We had, of course, a period of major inflation that is inflated pricing revenues but the capacities still are sufficient to on a unit-based respond to demand. And that is why this time the correction cycle takes longer than in previous cycles. Yes, some more details about planned investments, and it also says in progress. So there's an enormous investment going on in extending front end, but also back-end facilities, look at the [ M-core ], for instance, in the U.S., but also many others. So we can expect, at some point, return to growth once again. What does that mean, in particular, for assembly equipment. We see the peak reached in 2021 where supposedly, according to Tech Insights, the market was about EUR 6.6 billion, which is very important in itself because the market until that time, was always between EUR 3 billion and EUR 4.5 billion. So for the first time, partly because of COVID, but mostly because of new advanced packaging demand has grown above that high watermark. It has come down because of the overcapacity in the industry. And supposedly, this year, it should recover. But in a single-digit number is expected at this moment. Although if you also bear in mind that is added to this market size, the hybrid bonding. So anyway, it reflects the same pattern as for the whole industry. But then expected gradual return to growth in the second half of this year in this model and leading up to a next growth cycle '25, '26. And the question is, of course, do you have the right products? If we look at that question and we look at market shares, the only conclusion you can draw from this slide which is a bit updated, but also already presented end of April. But Besi has gained once again market share overall in the assembly market in particular, in the addressable markets. And then if you look for Die Attach, but also for packaging, Besi has done pretty well but that is also not abnormal. If you look at our financial performance, there must be substance behind that. So anyway, leading to a strong position at the beginning of the next up cycle. Explained in a bit more detail in these circles, somebody called the doughnuts, the other day, which I think is a nice name for these circles. You see the addressable market Besi's, 35% then for Die Attach, well over 40%. And Advanced Die Placement even close to 70%. For Packaging and Plating about below 20s. Again, here to emphasize which parts of the market are we addressing? And what is their expected growth rates? The CAGRs for Die Attach is around 29%, 30%. Packaging and Plating close to 22%. So in total, about 21.6%, and those are typically the segments where we are focused on. This is also a critical R&D spend many questions over many, many years, and in several ways. First of all, it's very easy to understand that our R&D spend is increasing in line with the complexity of the end product. So every smaller device geometry requires more complex solutions. You've seen examples downstairs where we are still able to successfully follow the ever smaller geometries have a more critical process requirements. And you see gradually year-by-year R&D spend go up. And if revenue then doesn't go up, your total return is an issue. But luckily, that is the case. If we look at the percentage of revenue, of course, in a peak year '21 as a percentage of revenue. It stays slightly behind. But then again, where it is currently around 11% is a very acceptable number and we can proudly say that with that spend, we can address the most successful, challenging applications for the leaders in this industry. Strong liquidity position maintained. Our balance sheet has been strong for many, many years. I mentioned at the beginning that also allows us to return profits we generate and especially cash profits to shareholders, which we have done consistently and will continue to do so. And as you see here, the gross cash and the net cash is in a very healthy position, even in an extended downturn. And that allocation partly in share buybacks, dividends is historically interesting, but that's how we try to maintain a very attractive return to our shareholders also in a cyclical environment. Our business model shared in every quarter is very constant. We are targeting in the next upturn to reach revenues of EUR 1 billion plus, plus, plus. And the plus, plus, plus is very much related to the advanced packaging hybrid bonding, DC segment. 40% plus in share in our addressable market. If you look at our gross margins, we have reached now consecutively above 65% gross margin. And that means in the model that we are somewhere between 62% and 66%. Operating margins on a comparable basis. And also the other targets remain simply intact, and that is our business model for the near-term future. And with that, I hand over to Chris. Questions are happy to be answered at the end of this presentation. Thank you.

Yes. Thank you, Richard. Good afternoon, everybody, and hello to all of who are joining remotely. My name is Chris Scanlan, and I would like to share with you what we see as opportunities and challenges for the future. First of all, Richard just got done telling you about the current conditions, what we see in the short and medium term. But in the long term, we're still in a very solid growing market. Our market has been growing at a pretty consistent rate over time. I started in the industry at about 1994, which isn't even on the chart anymore. But TechInsights is now projecting that by 2030, we'll finally tip $1 trillion in semiconductor revenue. And really, what's changed over time is only the end applications that are driving the growth. So in '94 when I started out, smartphones didn't exist. I was actually pretty excited. I already have a pager because most people don't even have that. And for the next 20 years, we developed smartphone technology, we're really focused on cost reduction on miniaturization, that's what drove the R&D spending in the packaging industry. What's been apparent for the last two years is that we're solidly now in the AI era. So we're no longer really focused on miniaturization of things. That's still is an issue for some end applications, but we're really in the AI era. And that's what's going to drive revenue growth probably for the next 10 years. In our end markets, as Richard mentioned, we're engaged in mobile. We're engaged in computing, automotive and industrial. But in all these end markets, we see that AI is a growth driver going forward. Even in mobile Internet, even in industrial where we see power devices that are powering data centers, for example. And in computing, it's really very obvious. Most of the R&D that we're working on is directly related to devices that are powering these AI applications. And the AI semiconductor market is poised to grow very rapidly in the coming years. By 2030, I just said that we'll be at about $1 trillion in semiconductor revenue as a total. And this data is suggesting that we'll be at about $150 million -- 1 billion rather on AI-related semiconductor revenue, so about 15% of the total. And the devices include data center devices. So these are devices like the CPUs and the GPUs or accelerators that are really responsible for training and inference of these AI models. Also the memory devices that support the GPUs, but also all the edge devices, the things that utilize the models and the data and also perform some local training. These are things like mobile phones, computers and even cars self-driving. The other thing that's really become an issue in the last 10 years, but as years go by, it becomes even more and more of an issue. Is that simply Moore's law is slowing. We all know this. What does it really mean though? Today, it's possible to fit about 100 billion transistors on a chip. 100 billion, that's a lot. But we already have CPUs, we already have GPUs with 200 billion, 300 billion transistors. There's simply no choice. Designers of these kind of systems have a no choice but to split the devices up and implement them as multiple chips or chiplets. And I'll explain how this is done in the coming slides. These are a couple of examples of chiplet devices, where designers have taken some of the functions that are most critical and implement them on the most advanced process nodes that are available in the fabs. And other functions, things like SerDes or things like that, can be implemented in trailing nodes, which are cheaper and put together in the package to form a fully integrated device. This is what we call chiplets. The data on the left shows the projected growth of chiplets as a percentage of the total foundry market, logic market and is projected to grow to about 25% of the total logic market within the next few years by 2030. Why is that? Because this chiplet approach, splitting the chip up, implementing as optimized subsystems or subchips has the advantage of reducing the cost, increasing the yield and reducing the cycle time for development. For our business, what does it mean? When a customer goes from SoC, a single chip and then takes the next step to split the chip into a couple of parts, and then further taking the next step to really implement multiple chiplet systems with many small chiplets, simply it increases the capital intensity and it does it in two ways. The first one, obviously, we need more Die Attach steps to build the same product. But also we need much more accurate Die Attach steps. So the interconnect density required to put these chiplets together and interconnect them as if they were all implemented in a fab node is much higher. And therefore, we need more accurate equipment like hybrid bonding. So I want to take a little bit of time to go through this slide. Those of you that were here on the tour, you have seen some of this information. For those of you on the remote link, this will be a little bit new. But this is what a typical high-performance computing product looks like in cross-section. So some of you might have heard of CoWoS. This is kind of a generic version of CoWoS what I'm showing you. What is CoWoS? CoWoS is taking the multiple chiplets, plus maybe memory devices and other things, integrating them onto a very high-density routing layer. We call that an interposer. This interposer is always or generally a wafer-level interposer, meaning we do Die Attach onto a wafer. So all these things are attached to the interposer could be silicon, it could be made of other materials. And then we mold that and we put it onto a substrate. So that's the on substrate part of CoWoS. And how do we do that? And what are the steps? It starts with the most advanced bonding technology that we have available to us today, and that's hybrid bonding. So hybrid bonding is used in multiple places. The first is in the fabrication of these chiplets. We call them 3D ICs. And what we do in the case of hybrid bonding. So we take advantage of direct copper-to-copper bonding to create very high-density interconnects between vertically stacked logic or logic plus memory devices. This is all done in the front end fab environment. It's not really a packaging process. So you can think of hybrid bonding is the last thing that happens in the wafer fab to create a 3D IC. Once the hybrid bonded chip is fully tested and created in the front-end fab, only then it's sent to the back-end factory for assembly to the interposer. We can also use hybrid bonding and HBM. And I'll share a little bit with you about the types of applications or the considerations in using HBM or Hybrid bonding for HBM. And then we have TCB chipped to wafer. So TCB chipped to wafer is used. Again, once we've created the 3D IC using hybrid bonding, we'll use TCB chip to wafer in order to assemble the 3D chip led on to the interposer. We can also use it in the fabrication of the HBM stack. From many applications, flip-chip mass reflow is used for the assembly of the Die to the interposer. A lot of applications don't have HBM. They just have multiple chips. And for those applications, we use standard flip chip mass reflow. And then in certain cases, for example, the nVidia B100 that was recently announced, we have things like Bridge Die, which provide a local, high-density interconnect between the chiplets. This requires very high accuracy placement because subsequent lithography steps are required after the Die Attach step. Then finally, the interposer has to be attached to the package substrate. That's more or less a standard flip-chip attached process. In some cases, it requires thermal compression bonding in the case that the interpose is warped are very large. And finally, we have to encapsulate the entire thing. So there's a wafer level encapsulation step. But there's also in some extreme cases, a secondary encapsulation step required. Basically, what is Besi's strategy. It's to provide the interconnect technology and the equipment to do all these steps. But why hybrid bonding? As I mentioned hybrid bonding is the most advanced interconnect, used to create 3D chiplets for logic, and simply the reason is because it has the highest performance, highest bandwidth and lowest energy for connecting chiplets in three dimensions. Hybrid bonding provides a direct copper-to-copper interconnect. So you can see at this layer, there's no solder and there's no other interfacial material between the back end of line features on the chip. And this provides the highest density and lowest contact resistance. TCB is also required. In many cases where you don't need quite the performance of hybrid bonding. You can still use TCB. And in the case of logic chiplets, typically, after you create the 3D chiplet using hybrid bonding, the next step will be to use TCB to connect the 3D chiplet to the interposer. So this is one recent example in high-volume production, showing how hybrid bonding has enabled AMD's MI300. So what AMD did as they use hybrid bonding again to connect 13 groups -- yes, sorry. So they used hybrid bonding to create 4 chiplet assemblies with a total of 13 active tiles that are hybrid bonded onto 4 base tiles. Once they have completed the hybrid bonding, which is shown here, they further assemble using micro bump or TCB. Those base tiles to a silicon interposer and then finally, using standard flip chip, attached the interposer to the substrate. So you can see there on product, hybrid bonding, TCB and standard flip chip. Hybrid bonding has been in production now for over two years. AMD first qualified this in Q1 of 2022. They've now qualified multiple products, gaming CPUs, data center CPUs, the MI300 accelerator. So there's many different products that are being continuously introduced by AMD. And they've built a lot of experience and really proven the technology to the market. So this is the next product that's been announced. This was announced in March. This is called Clearwater Forest and this is a new Intel data center CPU. So this will compute, for example, with one of the epic processers from AMD. This is the first Intel product to use hybrid bonding. And when you look at this, what do you see? We have 12 CPU tiles that are assembled on to free base tiles. And those base tiles are also advanced silicon, but they're on a trailing node. The base tiles contain memory. They contain power management and other functions. And then they're further assembled onto a substrate and combined with another couple of die that do higher functionality. So this really demonstrates that is not just one customer now, we have multiple customers and have volume production. And this device, as I mentioned, already is at 300 billion transistors. So again, there's no way that it would be possible to implement this as a single chip. I wanted to share a little bit about how these applications have evolved and what we expect for the future in high-performance processors. So if you look at AMD, they didn't just jump directly to hybrid bonding. They started with a single chip. They had an SoC. They started running up against cost and die-size limitations. They split the die first of all, into four identical chips, all having the same function and put them back together in package. Once they did that, two years later, they took the next step to a real chiplet implementation. What does that mean? In the chiplet implementation, they broke the functionality into different nodes. So the big chip in the middle is an IO chip using a trailing node and the small chiplets, 8 of them have the CPU cores and SRAM. After that, they took the next step to implement hybrid bonding to add more SRAM to the CPU chiplets. That was really the first implementation of hybrid bonding in the industry. The next thing that they did, they took the same technology. Now that they had hybrid bonding in their toolkit and they went through the same progression with the MI family of GPUs. We started with a single SoC. And then in 2022, they run into the reticle size limit. They couldn't implement as a single chip anymore. So they've broken in two, connected it with high-bandwidth interface in the package. And then two years later, they implemented chiplets using hybrid bonding. And we've seen now Intel go through the same progression from single-chip Xeon to Sapphire Rapids with four chips, all the identical four chips. And then finally, recently announcing Clearwater Forest, which will ramp next year. What do we see in the future? We now see nVIDIA, we see Apple going down the same path. nVIDIA recently announced their Blackwell family. So the B100 GPU. This B100 GPU is now implemented as two chips with well over 100 billion transistors. The Apple M1 MAX CPU was introduced in 2019. And in 2022, they implemented a dual chip version, which exceeded again the reticle limit. And we see these applications in the future transitioning to chiplet because we see these designs kind of facing all the same challenges as the designs that came before them. We don't know exactly when or in which particular configuration, but we see this as the next step. Now turning to high bandwidth memory. So last year, we talked about implementation of hybrid bonding in high-bandwidth memory. We talked about the limitation on thickness. And that, in order to fit 16 die into a package, we needed to eliminate the solder bumps between the chips. JEDEC since then has changed the thickness spec for the next-generation memory, HBM4 to increase the thickness to allow more room to extend the life of micro bump. So for that reason, we see that some of the -- or maybe even the majority of the volume for HBM4 will remain in micro bump. But yet, all the suppliers still have both TCB and hybrid on the roadmap. So you can see the roadmap on the left from Samsung and the roadmap on the right from SK Hynix. Here in the Samsung roadmap, you see TCB and hybrid copper bond, gapless and you can see the 7-micron gap, that's the thickness that they have to deal with. In the case of SK Hynix, you can see here hybrid bonding and advanced mass reflow, which is a kind of thermo compression assembly process. So we see our customers really pursuing dual parallel development path. We also see TSMC supporting both hybrid bonding and TCB by developing a base die and a set of design rules for both. So why are they doing that? We think the reason is performance. So thickness perhaps is not a constraint, but performance is a big constraint. So one of the most critical issues in these high-performance computing devices is thermo performance. So these devices are dissipating already over a kilowatt. As you can imagine, a very thin piece of silicon or maybe multiple generating 1 or 2 kilowatts of power. It's going to heat up anything that's very closely coupled to it, like the memory. And it turns out that it's very difficult to extract the heat from that stack of memory. You can see here the controller dies on the bottom. The heat sinks on the top. And in between, you have 12 or 16 layers. In the case of TCB, you have layers of epoxy, not very thermal conductive material between every single chip. And this adds thermal resistance. And as a result, the device runs hotter. It becomes a bigger issue, the more devices you stack and what we've found through our own simulation and what has been demonstrated by Samsung through their own experimentation is a hybrid bonding will reduce the operating temperature of the memory because it has about a 20% lower thermal assistance. And this is super critical because the memory has a maximum temperature limit. So we think in some applications, there won't be a choice other than to go to hybrid bonding for this reason. We don't know what the split will be, but we think there will be some implementation already for HBM4. In addition, in the future, people are already starting to talk about stacking DRAM, HBM directly on the processor. And as I just said, the processor is generating a lot of heat. And therefore, cover bonding is really required in order to more effectively extract the heat. You can see here from AMD, I'm talking about using hybrid bonding for the stacking of DRAM on top of logic. Timing on this, we think, is about equivalent to the HPM5 timing. Now let's talk a little bit about CoWoS. So as I mentioned, every bonded chiplets eventually go into typically a CoWoS package and these high-performance applications. CoWoS has two parts, chip-on-wafer and chip on substrate. We see this as a very rapidly growing market. A lot of this market is high-performance computing, but a lot of it is also mobile, PCs and things like that. And for this application, we see two steps where Besi participates. First is in the flip-chip attach process, chip to wafer. We showed this assembly in the tour. This is the 8800 Chameo platform. And then in the assembly of the substrate or the interposer assembly to the wafer or to the package substrate, our 2200 EVO was really the tool of record. And we see continued growth in this area. As Richard mentioned, we're also seeing big growth in Photonics. So this chart on the lower left shows the growth in the photonic transceiver market. What is a photonic transceiver? This is the pluggable device that is connected to a board in the data center that allows you to look a fiber directly to the server. Converting the light to electrons and delivering that to the processor. That's what it looks like here. This is one from Intel. Besi is participating in this market. We assembled about four of the components, four types of components in these transceiver modules using our 2200 EVO. But what's really exciting for us is we see opportunities for hybrid bonding as well in this market. So TSMC for several years now, we've been developing a new technology called COUPE. And this is a type of photonic chiplet that is fabricated by stacking a photonic chip with an electronic chip. So in EIC and PIC. The performance -- electrical performance is super critical. They're trying to achieve very high data rates. The whole job is to transmit the high-speed signals. And the data on the lower right shows the advantage in terms of performance for data rate and energy efficiency on hybrid bonding compared to micro bond is about a 40% benefit. TSMC has recently announced that they'll be qualifying this technology using hybrid bonding for pluggable transceivers next year and for co-packaged optics the year after that in 2026. Co-packaged optics means these assemblies is photonic chiplets will be placed next to the GPU or next to the network switch on the package. In this example from Broadcom, you can see that there's 8 of these chiplets. There could be more 16, perhaps, and these will provide the high-speed communication off of the GPU into the GPU. So another big opportunity for hybrid bonding. And we see a lot of opportunity as well and other edge computing applications like phones like laptops. We're working on projects and alternative reality glasses, automotive, self-driving many different applications. In the mobile phone market, so this market is growing at a low single-digit rate. But the growth that we're seeing is really driven by AI. The S24 from Samsung has been a very successful product in the market. Really, on the back of its AI functionality that it's offering. The data on the lower left from counterpoint is showing the growth rate and the penetration of AI-enabled phones over time. So we really see this as one of the key drivers for the mobile market, and we do anticipate at a certain point in time that the additional APU, MPU combination functionality will require conversion to chiplets, probably in order to provide additional memory capacity for the AI applications. And finally, on the automotive market. Right now, we're in a very kind of a soft phase in the automotive market. But long term, we see by 2030, the semiconductor TAM more than doubling. And this benefits all of our product groups at Besi. So from the EV drive trian, we have applications in molding. We have applications in plating and Die Attach, Power Die Attach. But here again, AI is really central to the growth. So as the development of self-driving capability primarily, but other AI applications as well in the car and then all the other components is thousands of components that contribute to this growth. So that's a little bit about what's driving our future business. And with that, I think I'll turn it over to Peter to talk about the particulars or Sub-Micron.

Thank you, Chris. Well, welcome everybody here. Let's move on with our third section, the wafer level section or to be more precise, let's talk even a little bit more in detail about hybrid and thermocompression bonding than [indiscernible]. In order to do that, I don't not want to talk about the technologies itself, but the adoption where you need it and why you need it. So we concentrate actually on the high-power computing portion and on the memory, the high-bandwidth memory portion of that so that will be our leading topics for this chapter here. In order to get into the chapter, we start looking on this chart, which is showing very nicely the long-term development of interconnect technologies. So on the very left side, starting with wire bonding, decades back and then gradually growing via flip-chip to thermocompression and all kind of these technologies. And always the driver behind the next step of interconnect was always the computers, always the microprocessors because they were on the most modern nodes with the most transistors. So they needed the most connectors. So that was always the driving force. So it's always in the end, the amount of connectors and that relates then to the x axis, which is the bump pitch, the connector pitch. And now as we all know, today with the real high-power computing applications, we have come to the very right side of this chart where the bump pitch is 10-micron or below. And that's well known. I don't think we need to repeat that the home turf of hybrid technology because there is no other technology that can connect these small bump pitches. But that's not the only one. Just left of these hybrid arena and micron, 10-micron plus. So 10-microns, 15, 12 to 20, perhaps 25. That's an arena, which is also very interesting because that arena can be covered by a special methodology of thermo-compression bonding, which is today, normally called the fluxless thermocompression bonding. And there is other thermocompression bonding even to the left side now of this arena with bum pitches of 30, 35, 40, which is, so to speak, the home turf of thermocompression. But really, I want you to focus on this neighboring area of hybrid because this neighboring area is really the interesting one for the -- also for future applications. Because also, if you don't go all the way down to below 10 micron, if you want to do a modern product, still need to go from 30-micron bump pitch to 2020 -- 15 and so on. And this area here, this what I call out here is a TC fluxless area. That is actually a TC area and everybody is thinking that's old stuff, but it is not. This is a new flavor of TC, and that is new and is coming up because it's a new version of it. And you will later see what you need special about that. Now, why I'm pointing this out on this chart? Because these are really the areas we want to investigate for yes, the high-power computing and the high-bandwidth memory because that's the arena where these applications will play out in the future. Now starting with the hybrid portion of it. Well, I think it's really well known in the market that since 3 years, we have established ourselves as the absolute hybrid market leader with our first-generation machine, which was capable of 200-nanometer accuracy, and which is still until today, the only machine which is used for high-volume production. And this machine and that's the scale below is capable of running products and manufacturing products, we have a bump pitch from 10-micron down to 7, if you push the limits even to 6-micron. And that's all products that are in volume production today. But as I said, it's always the computing power, which is pushing for more connectors and for that reason for less bump pitch. And so the next designs, which are just around the corner from our end customers, they will have even smaller bump pitches. They want to go down now to 4-micron some 3.5 micron. And for that reason, we have started early enough to launch and bring to the market our second-generation machine, which is the 100-nanometer bonder here in the middle, which, by the way, was not even more accurate, but even also more productive by 10%. And that is actually now taking over being the standard, the industry standard for hybrid bonding. That's happening actually right now as we speak. But for sure, we are not only talking actually to the production guys of our customers. We are also heavily engaged with the R&D departments. And if you look what is happening there, actually, these gentlemen, they are already working on test vehicles with a bump pitch of 1-micron. So the very, very right part of this scale here. And they're not only talking about it, they're acting on that. And for that reason, it's very clear that also with 100-nanometer, which is an exceptional accuracy for a die bonder that is not good enough for the future. And for that reason, we are already working on our third-generation machine, which will then have a capability of 15 nanometers accuracy and which will then cover the bump pitches all the way down to 1-nanometer. So that is in a nutshell also the roadmap here that we are working on, but that's really more the technical stuff. Let's not only look at -- yes, at the machine side, let's also look at the customer side. You have heard already a lot of things either, here when you were going around or also from Chris. I have put here some examples and also a lot of customer names. So we all know that AMD together with TSMC, they were the front-runners in this technology. And the very last picture, the APIC processor was really the first product in the world done with hybrid. And now it's the second picture here, it's the MI300, for example. And then you see and Chris explained it already, the Intel product, which was announced, but it's not only that these big logic manufacturers are in high-volume production. It's also that the memory guys that you see next Samsung, Micron and not only these two, they are also heavily working on hybrid. And they are heavily working on hybrid together with us. And not to mention Samsung is not only a hybrid company. They also have a logic division, and we are also working with them on their next-generation logic for hybrid as well. So it's really not like last year. But if you remember back for all of you who have attended also last year where there was more or less one high-volume manufacturer in the world and the rest was, well, will they adopt or will they not adopt? It's very clear that everybody is adopting right now. You have seen the big names here. But if you look without pictures just on top, there are small names. Perhaps you have read recently an announcement of company enhanced, which is a small-scale company which is doing special logic applications, but also very high end. But also the OSATs like ASE, they also do not want to be left out in the race of the next technology. So they all are starting to adopt to this technology. And finally, if you look to the very right side here, even in Japan, where they have this consortia Rapids, which is building the first 2-nanometer factory in Japan. Also, we are engaged with them to set up the packaging manufacturing then with the hybrid technology in Japan. So what you really can say is compared to last year, that it's not -- that it has gone from one manufacturer to really more manufacturers and from only the big guys, also to small companies and really everybody is adapting to it from starting in the U.S., all over the globe, all the way to Japan. Now once again, back to thermocompression, as we said before, because there are these 2 areas. Well, thermocompression, as I said, there's a wide area. There is, let's say, the standard to thermocompression, which is there for a very long time with the bigger bump pitches, which is more the left side here on this chart. And then there is this arena, which is really next to hybrid, which is 10-micron up to, let's say, 25 micron. And that's one that right arena. That's really the interesting one for these high-bandwidth memory and also for logic applications next to hybrid. And exactly for this arena, we have developed our next-generation machine, which is also called TC Next, which needs 2 very specific things in order to be successful compared to conventional. And that is really a much higher accuracy where we are poised for with our experience from hybrid. In that case, it's not 100 nanometer, it's 500 nanometer, but that's still very challenging. And you need a methodology in the machine to reduce oxidation of the bumps. That's what is called fluxless. And that's what we have come up with in a very nice package. And that's actually what we are now going to start with customers like Intel, Micron, but also all the others that you see here on the list to get engaged with them on their next future products that they have in the TC arena. Now while we are talking TC, let's switch a little bit. And once again, even so Chris did mention it already. Let's think a little bit once more about this high-bandwidth memory. Because -- you remember the last half year, I would say, or even perhaps more, there was this big debate in the industry, yes. Now as the [indiscernible] standard in height was lifted a little bit. Yes, does high-bandwidth memory need hybrid anymore? Or is now anyway, anything TC? That was actually the big debate. Let's once again do a deep dive here to really understand what is driving this industry. And this chart here is from Yole, which is only summarizing very simple, the specification of the different high-bandwidth memory generations. So that means what Samsung needs to deliver that NVIDIA [indiscernible] or Micron or Hynix. And I want to point out 2 lines here. One thing is from generation to generation, actually, the memory capacity has to increase because you need more memory for these AI applications. And from Generation 1 to Generation 4, you have a factor of 64x bigger the memory. And the other thing what needs to increase at the same time with the fact of 16 is the bandwidth, so meaning how fast can you read or write data from this memory cube. And that's the 2 major challenges, and that's also what -- yes, the big 3 guys are striving for in their R&D departments. Now let's look at that. What do you do when you want to have more memory capacity? Well, for sure, you can try to optimize your silicon, but there, they are pretty much at like also on the other side, at the end of the opportunities. They can do a little bit, but not much. So what you'd easily do is say, well, let's take dies. Let's put more together. Very logic, very straightforward. And then you run into the problem, yes, but it's getting higher then and there is a standard and they exceed the standard. Okay. Standard is increased, you think no problem, but that is not true because there is this other problem that I don't explain the second time because Chris did it nicely because it's generating heat. And with all the more layers, it's more difficult to get the heat out and you cannot overheat the part because then it's damaged. Bad enough, but it's getting worse because once again, at the same time, you need to increase bandwidth. And how do you do that? Well, you have 2 opportunities technically, very simple also. Either you make more connections that you can do more read and write operations in parallel because you have simply more electrical lines or you run at a higher clock rate. So you mean you do more read and write operations in 1 second. The bad thing is both of that methodologies leads to even more heat because you do more operations where you push electricity through your chip, and that means more heat. And so on one hand, because you have stacked more die, you anyway have a problem to get rid of the heat. And then you need to operate it at a higher speed, which creates even more heat. And that -- perhaps to try to put it a little bit simple words, that's ultimately the reason there is simply no way for these guys to avoid hybrid technology. They can try to extend TC, and that's what they are doing, but there is simply no way out. And let's -- now having that said, let's look at what are the plans? And actually, I tried to make a more overview table from the charts that Chris has shown from the individual road maps of Samsung and Hynix, which are official and everything. But I think it's perhaps a little bit a better overview here for you to follow it. So currently, with the HBM3 and 3E, which is the current generation that NVIDIA is using, they have their technologies which they have been using. So that's these NCF thermocompression for 2 of the gentleman and the mass reflow for SK Hynix. So that's what they have been done -- doing all along. Now if you look on their road maps, what they are doing for HBM4 and 4E, they all have on one hand, an improvement of their existing technology. So that means that thermocompression guys, they are going to fluxless thermocompression because that gives them an improvement or Hynix, who is using a different process, is advancing their own process, which they have developed on their own. But at the same time, they are -- all of them without any exception, they are working heavily on hybrid because of the problem that I have described to you before. And in the end, I think we should not think along the lines is now HBM 4E, all hybrid or all thermocompression. In the end, I think the tipping point for the technology is not the generation, it's the stack height. And 16 will be the tipping point, where you can go up to 16 with thermocompression. Perhaps you can even make a 16 with an advanced thermocompression version and 16 and above will definitely need to go to hybrid. And also, Chris mentioned that we think we will see the first 16 up stacks with hybrid technology in '26. That is our estimate according to what we see. And then after that, if you even need more memory and more bandwidth, you're anyway bound to the latest and greatest technology. And if we -- and actually to add to this more technical side, to add also a little bit at market side, once again, a chart of Yole, where you see the HBM market in total. And where you also, by the way, see this nice increase, this heavy increase now about in this year and next year, where -- which is, for sure, generating a lot of business for conventional interconnect technologies. But also if you look into the future, where there is still a nice growth overall, but what is more important is that really the old technologies, HBM2 -- 1, 2, and then later on also HBM3, that they will fade out quite fast because the industry will only look for the most advanced stacks with the biggest bandwidth. So that means it's not only about the pure growth rate of the whole HBM market, it's really also about a very fast adoption rate always of the latest and greatest HBM stacks. And that is, for sure, if you look at from that angle, a really nice business opportunity. And we, as Besi’s, we are prepared to really pick up on this business opportunity because as we have seen also on our tour for the company, we have on one hand, our -- on the right side, our hybrid machine prepared for that, and we are working with all of these gentlemen on developing hybrid. And on the picture below, you see a sample build with 16 high stacks. And we have put it here in writing because otherwise, you cannot count it. Even in the R&D lab, we are even doing 26 high stacks. So that's the one side. And on the left side, actually, you see the thermocompression bundle, which is precisely fitting into that specific version of thermocompression that you need. And you see here a cross-section of the [ test vehicle ] of hours of 16 high stack. Once again, even if this is a test vehicle, we are working also directly with the manufacturers on this one as well. So -- for us, this is one big opportunity ahead of us because also if they stay on TC, they need to go to the next generation of TC. They cannot prolong their existing machines any longer. They need also new generations of machine because it's not the same TC as they are using today. With that, I would want to come to my last chart. You know this chart, the gentlemen and ladies who have been here for the last year's know chart very well. This is our hybrid market modeling. So we are modeling here the amount of hybrid bonds that we think that will be used in the industry with a bottom-up model. And then we, for sure, divide it by average UPHs and availability factors and that's how we get to machines. Now, let's have a look what has changed from last year. I have pointed it out. So overall, our outlook for '23 has increased by 6%. So we are more confident overall than we have been last year. And why is that? Well, first of all, and I explained that on the other slide, the adoption rate and also the companies who are adopting has increased significantly and is much more broader today than last year. Then what we also can say, if we look at the logic, which was the front runner and which is also today the biggest contributor, is that besides TSMC, well known. Also, the second really -- real relevant supplier for logic and computing devices has adopted to a high-volume production now. I think you have seen some of our announcements of order intake recently. But also TSMC is growing further. They have made an official article, it was stated that they think that this type of technology and this type of devices in their factory will increase by 100% every year until -- for the next 3 years, until '26. So that is a big growth rate. And actually, just I think it was yesterday, [ that ] was also officially available, they announced their next capital expenditures. And if you read them, also they need to build new factories because they are running out of space. And if you read them carefully, you see also Besi named as a main contributor to their next expansion phase. So that meaning it's not only a starting point where they already have a lot of machines installed, they are really also growing like hell. Then the next one, the next point, once again, the memory. I think I tried to explain how we look at the memory business and why we think this is a big opportunity for us. And yes, we agree there was a certain shift in there. We modeled it with 1 year compared to our last year's model because there will be an extension of using thermocompression technology. But it does not -- as explained, it does not change the overall plan on the long run. And there is a third thing, and I think that's not discussed heavily, Chris mentioned it a little bit, but I want to put more emphasis on that because it's really important. Last year, I got a question here at the same event, what do you think, Peter, when will application processors adopt to hybrid? Or will they adopt to hybrid at all? And yes, the visibility last year was mediocre. Let's face it. But if you have been on conferences, let's say, for the last half year, roughly, and I know some of you have -- I have met on the ITF conference at IMEC in Belgium just recently. You heard everybody was talking about Edge AI. And Edge AI, and Chris also mentioned that in one slide, always does mean Edge AI on our phones, Edge AI on our computers and if some of you remember the BMW gentleman saying Edge AI on our cars. And it's getting more and more clear that AI will penetrate our personal lives with our edge devices that we are using day-to-day dramatically, and this is not a topic only for compute centers. And for that reason, also there, it is getting more and more clear that our processors that we are using in our edge devices need a lot of compute power and also specific engines for neural engines, and that is driving this whole Edge AI and with that application processor dives into the same direction. Of course, one more technical thing. Remember one thing that Chris said, hybrid is also a huge enabler to provide high compute power not alone, but in combination with the chip itself to provide high compute power at a low power consumption electrically. And that is exactly what a lot of Edge AI devices need because the batteries in our cell phones are not endless. And also in the car, the guy said from BMW, he needs the electrical energy for his drivetrain and not for the computer to calculate the AI. So for that reason, that one will be the third big thing coming up after the memory. And that's how we modeled it, and that's what it is. What is in there. And besides all that, there are also some nice add-on and upside potentials in co-packaged optics, mentioned by Chris, and also by special CMOS applications that we are working on with some lead customers. So all in all, I have to say our model from last year has been confirmed, and we are running on that track and getting the business there. And with that, I want to hand over to Christoph.

Thank you, Peter. Exciting news indeed. We've come now to the last part, which is all about the mainstream die attach. I am running that group, and I will walk you through the updates there. So let me start with a quick introduction of the Besi die attach product group. Just in a nutshell, it's about 80% of the overall Besi revenue, so a quite significant overall contribution to Besi. Market share has increased last year about -- in that meeting, I was talking about 40%. The latest numbers just recently presented by TechInsights indicated that we have increased now to 43%. Overall, for die attach, if you look into the advanced packaging segment, there, our dominance is even much bigger. We own more than 2/3 of that market. The market itself is a very interesting one, also bring new data from TechInsights talking about 29% CAGR in the time frame till '26. So definitely an interesting one. And if you look into drivers, I think it became clear today. And also in the presentations we have just seen, it's all about AI. AI translates into very advanced package formats like CoWoS. Photonics is a big thing for us as we speak. But still also the mobile is a very relevant driver for the die attach market. Automotive at this moment, I think you have realized a bit slower, but still expected to return to a growth mode anytime soon. Well, on that slide here, you see the die attach product portfolio. It's split into 4 different product lines. The 2 on the left-hand side are the more advanced packaging product lines, the 2 on the right-hand side are the real mainstream product lines. I start with the -- with a prominent one with the MMA platform, our 2200 EVO, which is a very versatile multi-chip platform, highly configurable and used in a very diverse field of different applications. The most prominent one, obviously, is the mobile market, whereby there we are very strong in the camera and sensor supply chain. On the flip chip side, we have a long list of different flavors of these machines, the Chameo platform for the wafer level assembly, the Quantum platform for the substrate level assembly and the 2100 flip chip for the lead frame assembly. So really, the full portfolio of flip chip processes is being supported, and this is really the flip chip platform of choice, no matter what application is behind. Then looking at the die bonding machine. This is the industry-leading epoxy bonder in terms of industry leading in terms of the currency, but also throughput. This machine, yes, also here, we see various applications. The most important one is mobile PAs because of its very tight bond line thickness control. And last, but certainly not least, our Soft Solder product line up here with 2100 SSI, which is industry-leading platform supporting the Soft Solder business, but also the diffusion soldering, which is our 2 technologies that are used in automotive and power applications. So today, the focus is more on the left-hand side. And in the following slides, I just want to highlight some of the recent introductions and also strong solutions at this moment. I start with the high-end smartphone market, which is still very relevant for us and also seen as a driver near and midterm for 2 reasons. We do see 2 driving vectors. One is what Chris already explained, the tendency that these large language models are getting on to our phones, the Edge AI or Gen AI phones. And yes, that is -- Counterpoint is talking about a very strong introduction rate now by '27, if I'm not mistaken. They predicted almost half of the mobile phones out there will be Edge AI phones already, and this triggers a whole replacement cycle of mobiles. The other driving vector on the bottom left is more an internal one. This is simply the fact that we as Besi are very much engaged, especially on the camera and sensor side with leading customers to introduce more and more process steps. And as you can see in the chart here, over the last 10 years, we have been able to grow the number of supported process steps by a factor of 10. We are now at about 40 different steps we are doing, and we are working a lot to increase that number again. We are working on things like variable apertures, own smartphones, so very SLR like features, but also lens system assembling. So very high-end stuff that will come to smartphones and will help to drive that business further. Solutions on our end, I have a couple of machines very active in that market. As indicated already, the EVO is the platform supporting the camera and the sensor business. The flip chip machine, which is very strong in mobile. And lastly, certainly also the 2100 platform with its contribution to the mobile PAs. The strong point here is that we as Besi working a lot on integrated lines, on fully automated lines that help to drive up the yield of the assembly process. Also cleanliness is a key topic. We have improved our machines a lot in the last time frame in terms of cleanliness. We introduced a lot of inspection and metrology in the integrated line also with the end in mind to improve the yield. And lastly, and that's probably also an interesting point. We are not only supporting the manufacturing of AI cards high-performance computers. We are also making use of AI a lot internally in our development. For instance, here, as mentioned, also our vision algorithms are more and more relying on AI, and we make good progress there compared to conventional systems. The second aspect I'd like to talk about is photonics. Data center growth, I think, is imminent. Everybody understands that, everybody hears that. With a growing data center capacity, there is also a communication part in the data center growing like hell. I think it was Chris explaining the transceivers that are basically translating electrical signals into optical signals and vice versa, which are needed to connect all those regs in the data center. All the short distance connections are meanwhile done optically, and this Yole chart you see here is talking about that. The guys on the bottom are the key players in that field in the transceiver field. And all of them, I can proudly say, are users of the photonics platform we are offering with our 2200 EVO. This machine is being used to do all these optical subassemblies, the TOSA/ROSA as it's called, lasers, VCSEL, et cetera. Why the EVO, you may ask, and there is one simple explanation for that. This photonics market is still a very diversified market. There is no standard available. Everybody has his own recipe and proprietary technology, which, at the end, means there is no equipment available off the shelf. You just have to develop to customize equipment -- customize your own equipment. And with our highly configurable and flexible EVO machine, we offer a perfect starting point to do that customization. And not only that, also, once the recipe approves to be working, we are able to ramp rapidly from low volumes into HBM versions. We can deliver many machines in the same configuration and with consistent quality. So that's the reason -- the main reason why this solution is used very much in that market. We are working to extend our process capability further to even take a bigger portion of that market, namely the active alignment side, which we are not supporting now, but we believe with increasing the accuracy to 1 micron, there is a good chance that we can capture that market as well. Then coming to CoWoS. We heard it a lot. We saw that pictures many times already. On the left-hand side, you see a typical high-performance computing board, where a logic has to be placed. HBM dies have to be placed. The -- all those components need to be placed on wafer level with higher accuracy with high throughput with best cost of ownership. And we have been able to develop an integrated line that can do both in one line the logic, which typically comes from a wafer as well as the HBM dies, which are fed in a tape and reel format. And yes, in this combination, we offer really an extremely competitive solution, which beats competitors really by factors. We have seen that in a recent installation in Korea, that dissolution really was much faster and providing the cost of ownership that is needed when a product goes into high volume, and that's what happens right now in this market. Once this subsystem has been assembled, so the logic, the HBMs, eventually other components as well, we end up still with a chip like structure that, at the end, needs to be packaged into the -- or to bond it into the final package. And this is where our -- where the only substrate part of CoWoS is happening. And here, we have another excellent solution available. Not only excellent solution, but also at the end, the tool of reference today. The vast majority of the CoWoS products that are out and are being assembled are done with our 2200 EVO on substrate attach because of the capability to handle very large dies to handle them carefully, reliably. And we have also development activities in place to further increase the capability, the die size capability to handle also future sizes. I think with many of them, we talked about it when being at the machine, it's really amazing to see how large those dies get and which are handled automatically. So with this few -- only a few highlights, of course, all the products are being sold and have their unique selling points, but I only wanted to point out a few of them. With that, I'd like to point our attention to the bigger picture where we are acting at with die attach, you see basically here the addressable market for die attach, for mainstream die attach, I should say, which is growing from currently $800 million to about $1.6 billion, so a factor tool in the next years until '26 is projected and again, referring to TechInsights, latest updates. What we also see is that this so-called Advanced Die Placement is the fastest-growing portion within our addressable market. And based on basic internal marketing data, we do estimate that within that Advanced Die Placement, which should be around [ $500 ] million in '26, about 1/3 is in photonics, another 1/3 in this before-mentioned CoWoS applications. So a very significant contribution coming from AI. So with what I have presented with our positioning of these AI platforms in that fastest-growing market and also knowing that there is a strong upswing in the overall market expected, we are very confident that we will not only benefit from the pure market growth, but are also able to increase our market share further with the drivers, AI, CoWoS and photonics. And that concludes my presentation and brings us to the last section, which is Q&A.

I'm sure you understood every single slide and it must have been a bombardment. But I see 2 hands sticking up.

[Operator Instructions]

I just had a quick clarification on TCB within HBM. So once HBM moves to fluxless TCB, do you expect your tool to take most of the share there? Or do your competitors also have a good solution?

For these suppliers who are using TCB because not everybody is using that when they are using fluxless then, we are well prepared to take a big portion of that business.

It's Alex Duval from Goldman Sachs. A couple of quick questions. Firstly, you talked about Edge AI as an opportunity. Clearly, in terms of what's in production with hybrid bonding, you have great progress that's happened on the data center side. Can you talk a bit about how you expect customer behavior to evolve in terms of working with smartphone chip players? And then secondly, you talked about advanced TCB. And clearly, that could be part of the solution potentially on this HBM4 as you get to higher stacks, although they're pursuing a twin track obviously, with hybrid bonding. So on TCB, can you talk a bit about your more advanced solutions, the customer traction you're getting there? And how we should think about the average selling prices relative to what you're getting on hybrid bonding?

There was a lot now. Well, the average selling prices are all about that. Think of these high-end TCB applications and hybrid from a die bonding machine point of view, think of it on a similar price level. So they are in the same range. UPH, also in a similar range. So the cost of ownership on our side here is not really that much different. So if you look for cost differences of these 2 different manufacturing parts, you really have to look in all the steps that are leading up to -- yes, to these 2 steps in the preparation on that. So that's really the dominating part there. Then once again, what else?

Traction in the market and on...

Traction in the market with TCB solutions, yes, well, I have shown once again this in this new, let's say, advanced area, let's not call it new advanced area of the very small bump pitches for TCB, we are really now. Last year when you were here, I don't know if you were here in person, but you saw also on the same spot the machine, which was an R&D machine. Now we have it finished, it's ready to sell, and we are now really engaged with a lot of customers. Once again, we -- you have seen some big names on my presentation, actually. We are all working with them, some -- on some we are working here in our lab, on some we are working with our machine on site with them. And so it's really now the time to do the development with these customers for this generation of products that are to come. And our traction is pretty good in there right now.

Great. And just on the point about Edge AI and smartphones.

I'll take that one. So I think Peter showed the time line that we're sort of predicting for the adoption of Hybrid, I think your question is specifically related to hybrid, is that correct? Yes. We -- first of all, I think we'll first see adoption in PCs and laptops and then in smartphone. So you already see AMD, for example, using hybrid bonding and gaming, application CPUs for gaming for PC. The next step will be higher volume applications in the PC space and laptop and then later, much higher volume applications in smartphone. And we see not only the application processor, but also other potential applications in the smartphone that includes the RF front-end module. There are certain companies that develop RF [ fees ] that are doing development on using hybrid bonding for that space, motivated by different things. And then also, there was a discussion earlier about image sensors. We also see something Sony, for example, last week at ECTC presented chip on wafer on wafer, meaning they have a 3-layer image sensor now, in which the first 2 layers are bonded together using wafer-to-wafer hybrid bonding and then the third layer being bonded using chip to wafer hybrid bonding. So we see more than just the application processor is potential for the smartphone.

Yes, great presentation. I just want to ask on the very last slide, you showed that in the mainstream advanced die attach market, you estimate about 1/3 of that is CoWoS in 2026. I just wanted to clarify, does that include TCB as well? And what is the size of that market in 2023?

Good that you bring that point up because I actually forgot to make that disclaimer that is excluding the TC and the hybrid part. This is really looking at the more conventional die attach products portfolio. So everything you have seen in the submicron presentation is actually adding to that business potential.

And the size of that market in 2023, do you have an estimate for that?

2023 -- is -- will be -- and you are talking about TC and hybrid related?

CoWoS?

It is I don't have a number out of the top of my head, but it is already quite relevant -- it has been already quite relevant for us last year. We have seen, and I think we were talking about it in one of our slides. We have seen basically early '23, mid-23 kicking that CoWoS business really in. We have seen it on the chip to wafer side, but also on the substrate side. So both platforms benefited a lot already from that CoWoS introduction.

Ruben Devos from Kepler Cheuvreux. I just had a first question on basically AMD, which has been let's say, with their products, the EPYC, the Ryzen, MI300 has been sort of flagship products with hybrid bonding adoption. Could you maybe talk about -- I mean, last week, we've heard about the 325 MI -- MI325, MI350 and so on. It looks like the areas of innovation is really accelerating. And in terms of logic to logic stacking, is there sort of, yes, acceleration happening as well? How should we think about the bonding steps for these next-generation products? And how should we look at that relative to your hybrid bonding market forecast for logic, which I don't believe have really been upgraded since last year?

Yes. I'll leave the forecast to you, Peter. But yes, we definitely see AMD on the -- really on their data center CPUs and GPUs that you mentioned, making basically employing more chiplets, which means more bonding steps. So if you look back to the first EPYC processor that used hyper bonding, there were 8 chiplets, 3DB cash-enabled chiplets. And there's multiple bonding steps in the fabrication of each chiplet. The picture I showed you had 12, and they've now shown examples of even higher numbers of these 3D chiplets. So that will continue to evolve. And the same on the GPU. So I think the first implementation, the MI300 had 13 active chiplets, but again, there are more than 13 bonding steps because our spacer die, there's some temporary bonding steps that we also have to consider in the process. And they have announced in this last week at the event in Taiwan on next generation. They didn't give many details, but they hinted at even higher levels of integration. And the road map that I showed you gave one example of that, which was the stacking of DRAM directly on to the accelerator. So with that, I'll let Peter talk about the forecast and how we implemented that.

Well, as I said, we -- in the presentation, we are doing this -- we are trying to do this as a bottom-up forecast. So that means we do whatever we know, we integrate that in our forecast, but there is not everywhere on each product and each customer, only positive development. So yes, that is considered also the overall number in the end is going up, if you perhaps refer that perhaps for just next year or so. Well, a forecast model has plus and minuses, but yes, it is considered.

Okay. And then just a second question on the TCB road map. How does that look like? Because I hear you saying that particularly as of HBM5, it's all going to be hybrid bonding for memory, so basically, if we -- if you bridge that period until HBM5, at which bonding, you have the dipping point and before you want to see a lot -- you want to meet a lot of demand with TCB, what happens with TCB after HBM5?

Very good question because you're right. Only for HBM memory alone, you should not do a TCB because you might simply say, I'll wait until the final technology comes along. But looking back to -- if you look to the model, this overall typical package model, there is much more interconnect steps in there, which are now not related to the HBM memory, but to the overall CoWoS back hedge, which are today done in C4 flip chips. So for example, the attach of the HBM and the logic or the already hybrid bonded logic assembly to the interposer. That can be -- which once again today is on a large scale or still a C4 reflow flip chip, but also there, you get more bumps. That means smaller bump pitches. And that once again transitions then to TC to thermocompression. So that means, yes, one opportunity is now big but will go away over time. But at the same -- in parallel on -- not on the HBM, but on the overall CoWoS package, you will get new opportunities because there is the shift actually then from reflow flip chip to TC flip chip. So that means it's worthwhile to invest into TC.

First one, last year, you also spoke a bit about the gap between the competition and you believed that it increased given they had the new generation and more machines in the field. How do you see that over the last year? It seems that the competition is doing something, but obviously, you're not standing still as well. Do you believe how much is you gap now?

You are talking hybrid...

Yes, hybrid bonding.

Well, considering that, as I have pointed out, we are still today also the only ones who are producing hybrid products in high-volume production and our competition has an R&D machine here and there. I would make a quite bold statement that they did not close on us, especially given the fact that we are already now launching our second generation or have launched and that our high-volume customers have immediately changed from our Gen 1 to our Gen 2 for their high-volume production, so that is also a very clear sign that we are up. And don't forget, the customers, they are looking at everything in the world. So they are not blindsided. And doing this fast move on our generation, switch from our generation 1 to generation 2 for high-volume production, I think that speaks for itself.

And the other question I had on the HBM side, it seems that you're well positioned with Samsung and Micron. What about SK Hynix? I think in the road map we had for the 3 companies, you said eventually also go to hybrid bonding. Is that the moment when you can get your inroad there?

That is actually -- as they are not using this, they are now using a complete different technology since a long time, by the way, already, which we are not pursuing with our machines. You're precisely right, the inroad to Hynix is when they change their technology.

And you already have that visibility today or...

We are working with them as well.

Michael of Petercam. I have a question about HBM. Ideally, you want to have your customers doing the 15 hybrid bonding bonds for the 16 layers and then also the bond underneath. But Samsung is going to be introducing 3D DRAM next year, and it's going to be higher than planar DRAM and more powerful. So is there a potential threat that eventually a 16-layer play in our stack will become an 8 layer 3D DRAM stack, which is same height, perhaps more powerful, but fewer bonds?

I don't think it will displace HBM. I think -- this is the potential for integration directly on logic as well. And this is where we also see hybrid bonding being even more critical. So we have to wait and see how that plays out.

It didn't mean that HBM will disappear, but that HBM would be 3D HBM with higher individual dies.

Yes. Yes. Well, our customers have road maps all the way to 24 layers of HBM and 3D DRAM is another implementation on the type of memory but also requiring 3D stacking. So when they make a choice of interconnect technology, they have to consider performance, they have to consider thermal and electrical performance, so we have to -- and we're working on both of those, right? So they will consider both TCB and hybrid. And we have to wait and see which one that is basically up.

Okay. And then a second question. Is wafer-to-wafer hybrid bonding a competitive threat to HBM for you or not?

We don't think so because when you consider simply the yield loss and multiply that by 16, it's almost impossible, we think.

So [ 14 ] good die where 2 decent guy [ will not do it ].

Right or one bad die, even worse, right?

Okay. Yes. You still have 95% power but with all the redundancy, but that would probably not do it for the customer.

We don't think so.

You tweaked the financial model in the slide that you presented, Richard, relative to what you told us last year and had reiterated in the annual report. Can you give us an update in terms of the timing there? So when are you expecting to achieve that? Yes, you said sort of the next up cycle, but just any further detail as to what's driven the upgrade there.

Well, you've seen the number one, the market share development over the past year and all the, let's say, convincing evidence what has been accomplished in the past 12 months in terms of new technology, but also improving on existing technologies. So as I said, with -- yes, let's say, the best evidence of that is the margin achievement. So that should simply underpin a model which we have in place. So it's more a confirmation based on the one hand, the market forecast, which has explained extensively for '25, '26, probably '27 will be the next growth cycle. And we as Besi should benefit from that. The air is a bit dry here.

Martin Jungfleisch from BNP. Two questions, please. First one is a bit on pricing. Can you give a bit of detail on the pricing road map on hybrid bonding when you go from the 200 to 100 to 50-nanometer too? And how does this tie into your lifted or uplifted gross margin expectation? And the other question is more on the -- this new glass interposer or substrate technology. How would this from a technological side impact you? Would you need a new bonding technology for that?

Well, on pricing and margin, if you look at the model, we are not expecting higher margins, well, compared to last model. It's more a refinement as set and the evidence is the margins in the past 4 quarters, how that has developed. On the pricing -- we mentioned several times that the first-generation hybrid bundler is between EUR 1.5 million and EUR 2.5 million, depending upon what configurations customers order. And then we set for a next generation, the range increases by about 500,000, but that also depends on which configuration is it integrated in a line or is it stand-alone, which type of loaders, which type of software interface, but that's roughly the range. It was also answered by Peter in terms of the comparison between TC bundler and hybrid bundler generation 1 plus or 2, how ever you want to call it, also points in those ranges. And you had another question?

I think I will give it to Chris.

Sure. Yes. So Intel is really the most aggressive in terms of their glass substrate road map. And yes, we are aware of what they need without sharing too much detail, the motivation is really to support these very large packages that they have in the road map, where it becomes very challenging to handle the warpage and the formation of an organic substrate. So we will have to learn how to handle larger single unit substrates through our machines. Also, the glass core can be a little bit more fragile and so on. So the material handling has to evolve in order to make sure that we can handle these things with high yield and avoid defects and handling. The bonding process onto the substrate will not change that much. There's some potential for hybrid in there on the road map, and that's very far out. The one thing that is a potential or new thing for us is embedding components into the core on the panel, which would have to be done in a 510 x 515-millimeter format. So that is something that we're looking at and something that we have in our road map.

But then you can easily conclude the more complicated it becomes the more complex, the tighter the accuracies, process parameters, the more opportunity. So that's a very consistent line in our history. We always benefit from those kind of developments. Next question. Not too difficult, please.

It might be a bit cheeky. But you had a slide that shows NVIDIA and also Apple moving to split die and then kind of potentially moving to [indiscernible] after that. I just wondered if you had kind of a time line or are they currently working on it? Or is this just more of an expectation?

It's more of an expectation. We see -- we can monitor their patents that they filed that describe the use of hybrid bonding. But of course, you don't know from reading patents that people are actually going to implement those things. So the fact is we don't know exactly when they're going to implement these things.

We're at the hour. So any last question, most welcome. Nigel?

So I've got a question on the TCB time line. Sorry, confused a little bit in terms of the tool we saw downstairs, which is R&D, but now in production and then you're introducing a NextGen tool. There's a slide, so I might have mixed up some of the time lines, but do you expect to ship that Gen 2 too or get orders for that sort of in the next 6 to 12 months? Or is it further out?

Sorry for confusing you, that was not our intention. Now actually, this machine downstairs that you have seen during our walk through the building is the latest and greatest, which has all the features in there for the small bump pitches. So from what I said for the 10 to the 15, 20 micrometers, so that's all there. And we are expecting orders actually, yes, within this year, so the next months, yes, out of our R&D and activity that we -- that I mentioned that we are having any way since a while with these customers.

So with that, and I just took a picture to remember this wonderful event. Thank you all again for coming this way. And any further questions, don't hesitate. We're always happy to answer if we can. So all the best, and have a nice summer.