Cadence Design Systems, Inc. (CDNS) Earnings Call Transcript & Summary

All right. Good morning. Let's go ahead and get started. Welcome to the second day of J.P Morgan's 52nd Annual Technology Media and Communications Conference. My name is Harlan Sur, the Semiconductor & Semiconductor Capital Equipment Analyst here for the firm. Very pleased to have Anirudh Devgan, President and Chief Executive Officer of Cadence Design Systems here with us today. Cadence, leader in electronic design automation or chip design software and hardware solutions that help semiconductor companies bring their most advanced chip SoCs to the market, and Cadence is also a leader in the emerging area of Systems Design and Analysis Solutions. Now so Anirudh, thank you for joining us today. Before we get started, I am going to read on the team's safe harbor statement. Today's discussion may contain forward-looking statements, including Cadence's outlook on future business and operating results due to risks and uncertainties. Actual results may differ materially from those projected or implied in today's discussion. All forward-looking statements during this meeting are based on estimates and information available as of today and Cadence disclaim any obligation to update them. So with that, Anirudh, again, thank you for joining us today. Maybe to kick things off here and for those of you that may not know cadence that well, the team is an enabler and beneficiary of 3 major trends, right? First, you've got significant growth of leading-edge chip designs targeted at accelerated compute and AI; two, the move of semiconductor customers from developing chips to developing systems, right? And number three, the move of your systems OEMs and hyperscalers from developing systems to developing chips. And so maybe you can summarize how the portfolio of solutions at Cadence addresses all three of these trends?

Thank you, Harlan, and thank you, everyone, for your interest. So like Harlan mentioned, we are basically a software company, and what we like to say is computational software. So this is not your regular software. This is more mathematical numerical software. Because these chips are too complicated to be designed by hand and they haven't been for a long time. So they're mostly designed by Cadence. So what we say is almost any chip design in the world today uses some form of Cadence software, okay? And then the growth drivers, like Harlan mentioned, there are several of them. The three big ones are -- so right now, about 55% of our revenue is from what we would call semiconductor companies and 45% is from system companies. And semiconductor itself is in a big renaissance, as you know. So right now, the semiconductor revenue is roughly $500 billion or so going to -- is widely projected to be $1 trillion by end of the decade. And I think that may prove conservative. It might reach there before that. So there's a lot of growth in semiconductor design anyway. And I think the big drivers, as you know, about going from $500 billion to $1 trillion, there are at least two big drivers. So one is all this AI and data center demand and then the other is definitely automotive. We can talk about that. So those are multiple hundred billions each, right, growth drivers. And then all the other edge devices, consumer devices that may have. We're glad to participate in all that. So there's a massive growth in semiconductor content. A good example is like yesterday, this announcement by Qualcomm and Microsoft. And Cristiano was at our Cadence conference a few weeks ago. So we have a long history working with Qualcomm and all their advanced CPUs and also history working with Nuvia which Qualcomm acquired, which is the basis of this SnapDragon XElite. So it's really good to see that AI coming to the edge in disruption in that kind of market and in a lot of other kind of semiconductors. And of course, we have a long-term partnership with NVIDIA, we can talk about. And Janssen was also there at our CadenceLIVE conference a few weeks ago. So that's the semiconductor part of our business. And also, these companies like NVIDIA and Qualcomm are perfect example, they are not just semiconductor companies anymore. They are almost like system companies with massive software stack, firm ware stacks. The second big growth for our business the last few years, which is expected to continue, is system companies doing silicon, okay? And of course, it started a few years ago, almost 10 years ago by the big mobile companies doing it, and they kind of led the path of doing silicon and they're phenomenal in their own way. And then last few years is all the data center and automotive companies. So I think this is public -- it's fairly public, all public information that all these big data center companies, whether in the U.S. or outside like are all doing -- have massive silicon investments and same thing is true in globally, right? So that's a big part of [indiscernible] -- that's what is like what we would call the 45% and that's also growing well. And I still think that's in the early innings because there's still a lot of things to be done in AI and also automotive and other kind of mobile. So that's the second part of our growth, and we can talk more about that. And then the third part is we are expanding our TAM anyway. So as we work with these system companies and semi companies, our traditional suite is EDA and IP chip design software. But like even NVIDIA, they talk about not just designing the chip, designing the data center, or not just designing the phone, designing the mechanical part of it. So there is a convergence between electrical and mechanical design that is happening for a long time. And I think Cadence is the first one to recognize this in 2017, 2018. So we have a new category, what we call in sort of EDA SD&A, System Design and Analysis, and that's growing 20% plus last several years. And then even this year, we announced like partnership with NVIDIA to do data center design and then some other tools for car design, with McLaren and Honda. So that's also a good growth business for us. That's about a $10 billion TAM for us, and we are like $500 million, $600 million. So there's a lot of growth opportunity there. So those 3 would be the kind of systemic growth drivers, which should continue for the next 5, 10 years. And then coupled with that, we are always very disciplined financially. So we have very good financial performance, margin. We always focus on that EPS growth. But at the same time, we have the highest investment in R&D. So we have about 35% of revenue invested in R&D, but at the same time, have very high profitability.

No, that's great. And we'll get into all aspects of that through our discussion here. I do want to start off with the core sort of chip design software EDA business, right? We do our best to track and chip design activity primarily with the large ASIC semiconductor companies, right, that are helping hyperscalers and systems companies, co-design their custom chips because we think that they're a good proxy for just overall sort of leading-edge chip design activity. And chip design starts have accelerated just over the past 18 months, right, given that there is this AI arms race amongst these cloud and hyperscale titans and off-the-shelf guys like in NVIDIA. They all want to bring their leading-edge silicon solutions to the market sooner rather than later. How has this acceleration in leading-edge design starts manifesting itself in terms of how you see the growth outlook for your business not just this year but over the next several years, right? Is it -- does it just provide you with confidence on to your low to mid-teens type revenue growth target? Or do you think about it as a TAM expansion opportunity that can buy us the growth towards the upper end of the growth range.

There's going to be a lot more Silicon design in the next few years, right, even like our foundry partners have commented on like how much more design activity, as you know, is that N3 or 3-nanometer versus 5 nanometer or 7 nanometer.

Early 2-nanometer, right?

Exactly. So we are working on 2-nanometer for some time already. Several years already because some of the early customers are already designing at 2-nanometer and most of our R&D with like TSMC or the fabs like Samsung, Intel now switching to 1.4 nanometer. So one good thing is that we are at 3 so there is 2, 1.4 and 1. So there's at least 3 more nodes. So there is at least 8-10 of Moore's Law that we can see right now. And each node requires bigger and bigger chips because Moore's Law may have slowed down in performance becuase one question always is, okay, is there -- how much room is there to keep this semi conductor? But in my viewpoint, at least 10 years of pure scaling, okay? And whenever you have pure scaling, the performance may not improve as much as in the past. But the area scaling is there. So when you go from 3 to 2 nanometer, there is a massive area scaling. So that means more things can be put on the chip, right? And then all these chips have to be designed and they always need more software from Cadence, because the design effort is roughly proportional to at first or a proportion to chip size even though the chip complexity also goes up. So if you look at from now until 2030, and the way I look at it, right now, the chips are $100 billion to $200 billion. Blackwell is $200 million, but most of the other chips are $100 billion. And it's widely projected by 2030, there will be $1 trillion. To answer your original question. So that is at least chip size will go up by 10x in the last -- next 5, 6 years, but the chip complexity will go up more than that with the software. And also, it's not just the size they have more cores, more GPUs the complexity and verification of the chip goes up exponentially with size. So the chip complexity, the design may go up by 30x, 40x from now until the end of the decade. And it's not possible for our customers to hire like 30x, 40x more engineers. I mean they will hire more engineers but there's not even enough engineers graduating that can be hired 30x, 40x more. But I think they will still hire more. So let's say, there are 2x, 3x more engineers. So then there is a 10x productivity gap. That has to be made up by better software and better compute and using AI in our own tools. So I think the real opportunity for Cadence and the industry is that from now until the end of the decade, the more of the R&D can go to automation rather than what has done in the past. So even if you look at EDS spend now as a percentage of R&D has improved in the last 5, 10 years. But there is opportunity to do a lot more in the next -- and that should help in terms of our top line growth.

And that's a good point that you bring up, right? Because on one hand, your solutions help NVIDIA's and Google's and Broadcoms of the world bring their most sophisticated AI chips to the market. But then in return, you need the compute power and also integrating AI capabilities into your own set of solutions, right, in order to boost sort of productivity. And the team has been developing and integrating AI and machine learning-based methods across your entire portfolio, right? For digital implementation with Cerebrus verification with Verisium. And even into your system design and analysis portfolio. So talk about the use cases and adoption of your Cadence.AI solutions portfolio? And any metrics that you can share with us in terms of adoption curve?

Yes, absolutely. So first of all, one thing you have to be careful these days, everybody calls everything AI. That's another issue. But -- like I said, we have been doing this computational software for a very long time, right? The history of EDA is over the last 30, 40 years is this kind of mathematical software. So we have done all kinds of automation over the year. And AI is another way to -- it's another significant way to provide that automation. But even if you go back like 20 years ago, a chip would take -- I remember like these big chips at that time would take like 4, 5 years and 400,500 people, okay? And these days, you can do it by like 50x or 100x easier than that, both in terms of time and people. And I think the foundry ecosystem has played a role in it and our software has played a role. So it's much easier to design these chips than 20 years ago. That's why all these system companies are doing it now. but there is still more room to go. And I think the one thing that we never did before is if you go to our customers, they design -- they are running our software on a daily basis. But there -- we -- our software was mostly what I would call an -- all software was more [indiscernible] run that is you give it an input, and it runs for 1 or 2 days and gives you a very good output. But the design doesn't happen in a single run, right? Typically, what is happening in these -- all these big companies the designers, they run it, they change something, they run it again, they change something, they run it again, okay? This is what happens over 6 to 12 months to design one of these chips. So -- so we never provided automation in that, the workflow automation. Not that we didn't want to provide it, but there was no mathematical way to transfer the learning from one run to the next run. Okay. But now with AI, with real AI, okay, not -- a lot of times people would call simple automation -- AI, but what we would call real AI or GenAI or a real reinforcement learning, we can actually model the what the human is doing manually into an AI model, and we can automate the workflow. So that's how we applied these AI techs. And I can give a lot of examples. But what that does is it can shorten the time, design time, but more -- so that's a productivity improvement, which is well known from an AI standpoint. But I think what is more interesting to me is that it can give a better design. To give you an example, one of our customers is designing automotive CPU, and they are changing a lot of things. In that case, they were changing 17 different wearables. Some of them are design wearables, some of them are process variable. Some of them are power options. So you do the design, it takes you 6 to 12 months. But you're doing it by human intusion, right? I used to do this before, let me try this, try this. So even though our tool Innovus is very complicated, the driving of that tool is done manually. But with AI, we can do it mathematically. So it can give like 5%, 10%, 15% better PPA than a human design. It depends how good the original design was. But that's remarkable. So PPA stands for our Power Performance in Area. So we have like 8%, 10% better power, okay? That's like huge compared to -- when you go from 7% to 5% or 5% to 3%, you may be getting 10% to 15% PPA improvement with massive investment. -- and you're getting like roughly that or slightly less than that with better software. So there is a huge value in automation and also PPA improvement. So we are applying all kinds of AI techniques to improve this whole workflow from a single run to optimizing the surge of the design space.

In terms of productivity gains, right, hardware verification, emulation, prototyping, this has been a big contributor to the team's double-digit growth profile here. you're essentially creating a digital twin of your chip design on a high-performance compute cluster, you're accelerating verification efforts and also getting a head start on the embedded software design that will eventually be running on these chips, right? 10 years ago, these hardware-based verification systems were sort of a nice to have, not necessary. But given the sheer size of current generation chip designs, the usage of hardware-based verification and emulation is now mandatory, right? You're also at the start of an upgrade cycle with your next-gen Palladium Z3, Protium X3 platforms with a strong near-term demand profile. But I think the investor question comes up after 3 strong years of hardware sales, will customers have enough hardware and compute emulation and prototyping performance capacity? Or does the team envision continued growth beyond this year, just driven by sort of the sheer increases in chip complexity and software development?

Yes, that's a good point. So I'm super excited about the new hardware. So I mean we are primarily a software company, but just people who don't know, we do sell some hardware products. and this is to help the design process. So what happens is if you want to -- NVIDIA is a great partner and a public supporter. So I can talk about NVIDIA. So -- good thing is like, like I say, Blackwell is announced, the chip comes back, but all the software is also available at the same time, okay? So this is a new change in the last few years now, NVIDIA has been doing it for a while, but now everybody else is in which hardware and software development is overlap. So in the past days, like 20 years ago, you would do hardware development and then you would do software development and then the chip would system would come out. But now it's overlapped. So hardware and software is developed in parallel. So when the chip comes out, 3 months later, you can buy it from Super Micro whoever your favorite vendor is and everything works, right? So the only reason that's possible is when you're writing software and all these system companies are writing software and semi companies, there is no chip. So we have a product called Palladium that will mimic as if the chip [indiscernible]. Okay. And it will mimic it like thousands of times faster than journal purpose hardware like CPU or something. So then it became like an essential part of the design process. It's almost impossible now to design any of these complex chips without having emulation on palladium. That's why, of course, Jensen was saying it's more important to him that a refrigerator or ...

I think when he came on stage, what was his first comment? "I love Palladium, I need more Palladium" right? Isn't that what you said to you?

It's great. NVIDIA is a great partner. I think he publicly said that design of Blackwell would not have been possible without Palladium. And this is true for all the other kind of chips as well and big chips. And so this is happening for a while already. Now what happens is as the chips get bigger and bigger and then you have more software running on them. The need to verify these things also goes up exponentially. So where we sell Palladium is, for example, and this is -- also was talked about. So GPUs have more logic than a CPU, like you have a CPU could be 100 billion transistors but a lot of it is memory. So in emulation, it may require less capacity. But GPU is always not only they are big, but they have more memory, okay? So Blackwell is about 200 billion transistors. It was emulated on 8 drags of Z2, which is our previous product okay. And now with Z3, which is our new product, we just announced in April, we can go to 16 racks on Z3. So that's about 5x bigger capacity than Z2. So we have our ability to now emulate chips with 1 trillion transistors, okay, which is huge. So that should be good for the industry for at least for the next several years, several generation. Even a partner like NVIDIA said they can use Z3 for several generations of next-generation GPUs and then the other industries. So it's just a big jump. Now the question is how -- what does the demand look like by these systems? Like -- so first of all, even with the transition year this year, I expect to have -- every year, we have had a record year, like you mentioned, in our hardware business. So at this point, I do expect '24 should be a record year also. Our guide is fairly we are not assuming a massive growth in the functional verification business, which hardware is part of, but it still should be record than last year. And of course, we are not guiding next year or year after because we are pretty conservative in those things. But historically, a new refresh should add to future growth. And then what happens in these things, so like I was telling earlier, what's going to happen for the next 10 years is there's going to be this Moore's law. There's 3, 2, 1.4 and 1, okay? And on top of that, there would be -- there's 3D-IC even Blackwell or even Intel's latest ship or Amazon, they're all multiple chiplets on [ diet ] on a package, right? So it's no longer limited by the radical size. Blackwell is like 2 full reticle. So the actual capacity of the system whether it's a single chip or multiple chip in a package is going to go up exponentially in the next 5, 6 years. Okay. It's just because of the Moore's Law scaling, you add 3D-IC to it. And it's all driven by the demand of more compute and whether it's in self-driving cars or data center AI. So the bigger the chip gets you need more emulation capacity because these things, when we sell Z2, Z3 is based on how many gates it can emulate. So if the number of gates is 10x bigger, you need much more ambulation capacity, not only for -- to fit the design, but also as the chip gets bigger, it has more verification to do, exponential more corner cases to. So the verification demand should go up, which translate to hardware demand and also our software demand. So I mean, we'll see how it goes. But fundamentally, there is a lot of reasons that this should continue for sometime.