Cadence Design Systems, Inc. (CDNS) Earnings Call Transcript & Summary

Okay. Good afternoon, everyone. Welcome to San Francisco. We're on the stage with Anirudh Devgan, CEO of Cadence. Welcome, Anirudh.

Maybe if I just kick things off. I mean, no pressure, but we were in here, all of us earlier. Jensen gave a call out to Cadence, talking, I think, really around the sort of emulation space. And of course, you talk a lot about that sim to real gap and how you guys can plug that. So maybe help us understand, how does that segue? And how is this an opportunity for you guys, looking at physical AI in particular?

Yes, yes. Well, thank you. It's good to be here. Thank you for the interest. And we love working with Jensen and NVIDIA too. We have a long-term partnership with them, of course. And then I think what I've talked forever -- so sorry for people who are familiar with this -- is like the 3-layer cake. Because there's all this worry AI is going to replace software or something like that. And the thing is that there are different kinds of software, right? There's a whole range of software. And for us, the reason I call it a cake and people say, like, "Why do you call it a cake? It's like a Cadence bakery or something?" I'm not a good cook, by the way. I'm a horrible baker, but definitely not a great. But the thing is unless you are like 2 years old, normally, when you eat a cake or you consume a cake, you consume all 3 layers of the cake together. At least that's what I do. So -- and then you bake it together. And then what are the 3 layers are -- is AI at the top, and I can get into more detail, which is more like data science algorithms, AI at the top. The middle layer is more ground truth, physics and the good old stuff of how things actually work, like molecules and transistors. And then the bottom layer is compute and data. And now it's accelerated compute and data with NVIDIA and others. So -- and then people who graduated last few years, they say, "Well, I just need AI. Give me like input and output. I'll create a model, and it will do everything." And people who graduated 30 years ago say, "Well, what you know is the real truth," how transistors actually work and all that. But the reality is that you don't need to take side of that, any side -- it's both together, and then running on top of data and compute. So by the way, this is going to happen in all markets. All markets. And then the slice of a cake is, of course, domain dependent. It could be chip design, it could be self-driving cars, it could be robots, right? And now -- so first thing to remember is, in our case, the middle layer is very scientific, numerical. Physical -- if you're designing like 100 billion transistors at 2-nanometer, it better be accurate and you really do need to know the fundamentals. So -- and then when AI runs on it, it uses more of the middle layer, which is what I think Jensen is talking about also. So when you do more physical AI or Agentic AI, so there are at least two. And then there are -- I also talked about this for years about the 3 main slices of the cake, okay? And so the first slice is what is happening now, which is driven by data center, deployed in software. So that would be a lot of like even for us, like chip design flows or other flows. But I always believe that -- and for years now that the second slice will be huge, which is physical AI, which is cars, robots, drones. And then the third slice of the cake would be sciences AI, which is, of course, life sciences, material sciences. So in all cases, the 3 layers are different. So in case of the current one, of course, we have Agentic -- LLM-based Agentic AI at the top level, our basic kind of tools at the middle level and then GPUs at the bottom level, right? So that's how we -- so that, we can talk more about. We have all these new products for AI. Now the second part which you asked me, which is more specific to physical AI. So because physical AI will be huge, right? I mean, we can talk more about cars, drones and robots. So we're also building a flow on that. So there, there is a sim to real gap. There's more opportunity for simulation.

Okay. Yes. It sounds like a huge cake because that's 3 industrial revolutions, one after the other.

Yes, it's 3 by 3.

Yes. That's phenomenal. So maybe if we go -- first of all, I should have read out a disclaimer, so I will apologize. So let's imagine we've done this from the top. Today's discussion will contain forward-looking statements, including Cadence's outlook on future businesses and operating results. Due to risks and uncertainties, actual results may differ materially from those projected or implied in today's discussion. I apologize, that's on me. If we think about, however, the wider ecosystem in relation to what you talked about, silicon physics and then AI as the 3 layers, what is your position, particularly around that physics layer that we just mentioned?

Yes. I mean, we have a great -- I mean, first of all, again, the physics, I mean, the ground truth is different in different slices of the cake. So if it is chip design, of course, we have the strongest position. See, Cadence, you have to remember, has the biggest portfolio in core EDA, core chip design. Digital, analog, verification, packaging. And you are seeing that in the market, right? Competitively, we are doing great in our core business, okay? So now on the second slice of the cake, physical AI, we had to do some M&A. So the one we did recently was Hexagon. And the reason I did that was in the second slice of the cake, like I was saying -- so if you're going to build -- so in the second slide, the physical AI model, the AI model is different. The AI model is no longer an LLM model. It's a world model, like W-O-R-D and W-O-R-L-D. My wife says my Ls are difficult to -- so it's a world model in the second case. So in the world model, there's not enough data on the Internet. The LLM model, you can train with data in the Internet. But in the world model, you need to generate data, synthetic data. And so either you capture the data by sensors, but that's too difficult, right? It takes too long to do it. Or you simulate it. But if you simulate it, you have to make sure that it is very accurate. So that's called the sim to real gap. So in that case, Hexagon had the most accurate robotic simulator with Adams. So we're going to put Adams in that loop to improve the accuracy of simulation for physical AI. And then the third part, which is the silicon, is going to be different because the silicon is more mixed signal and more low power. The silicon for physical AI is different than the silicon for data center AI. So -- like silicon used in cars and robots. So that is actually also in Cadence's core strength because it's more mixed signal and lower power. So we have historically worked with all the big semi companies that make auto chips, right, or like these kind of embedded chip, mixed-signal chips, and then now with OEM players like Tesla and Rivian or BYD that are designing their own chips. So again, with the physical AI, the critical thing in these slices is that all 3 innovate together, and we want to make sure we are well positioned for that.

Got you. Okay. Very clear. Maybe take us back to some of the discussions we've heard in and around this whole conference is the sort of worry that AI volatility is disrupting traditional software business models. And maybe if you could just help us understand how you would stand apart from that disruption? And where indeed you would be moving to change your business model or augment it against this volatility?

Yes. I think the one thing to remember is that I think for us, it's not disruption, it is amplification. And I can talk more about -- and the question is how do we monetize that amplification. Because what AI will do is that it will naturally drive more usage of the middle layer. The top layer drives more usage of the middle layer. And there are a few things that are different for chip design. Because if -- so what I think what people get worried is if something is 10x more efficient, does it reduce the usage, okay? But in chip in EDA, going back to 20, 30 years ago, we are 100x more efficient. It just -- when I was in IBM in the late '90s, we would have 500 people design a CPU in 5 years. It is a real thing, by the way, okay? And Intel, same thing or [ DEC Alpha ]. Now you can have 50 people, sometimes even less, design a CPU in 6 months. So it's 100x more efficient. And we have even more usage of our tools. The reason for that is that the workload is exponential because our customers are designing bigger and bigger chips. If the workload -- that argument only applies if the workload is constant. I don't know, like you are doing something like -- I don't want to pick on anybody, but like if your workload is not growing, workload is linear to the number of people, for example, then if you are 10x more efficient, you may use 10x lower. But in our case, we are doing 3-nanometer chips now. It will be 2-nanometer, then 1.4 nanometer, then 1-nanometer. Then there will be 3D-IC. So there's a wide projection in 5 years, the chip size will be 5x to 10x bigger. Complexity will be 20x, 30x bigger. So you need that 10x to keep up because our customers don't want to hire 30x more engineers. So AI will modulate the headcount growth for sure, but instead of 30x, it will be 2x, 3x. And the remaining will be with automation. And this is the history of chip design industry because of Moore's Law. So this is a very different thing. So one part that is different for us is that the cake, the middle layer is critical. You have more scientific software. Second part that is different is the workload is exponential. So as a result, like we have customers that will spend months optimizing things to get a few percent better power because they're going to have like millions of these devices. So as things get more efficient with AI, they run more things. Like NVIDIA, they will run more optimization to improve the GPU further or more optimization to improve the mobile CPU or more optimization for the car. So if you look at the license count, I think that is going up nicely. We just have to make sure that we get our value for that. And the way to do that is to demonstrate the value to our customers.

Got you. And talking about more optimization and some of the things that are different. A few weeks ago, you did launch the ChipStack Super Agent. So maybe just help us understand, how does that differ from the GenAI tools that you had out in recent years? And how could that accelerate the growth for you in the next couple of years?

Great question. So I'm super excited about ChipStack. This is a new product category, okay? So if you look at LLM or Agentic AI, what is the biggest use case right now? The biggest use case in the general market is coding, right? C, C++, Java, you can just talk to it and it writes code. Now -- which is great. Now one issue is -- and we use it internally for our coding. We are a software company. So we can use that to become more efficient in R&D. Now one issue is if you write like 80% of the code is good and 20% is not good, then you spend a lot of time figuring out which 20% is not good. So this is one issue with LLMs. Now if you go to chip design, it's actually the opposite. If you look at our history over 30 years, chip design also has a language. I don't know if you -- for those of you who did engineering in undergrad or -- there is RTL is registered transfer language or system dialog is the language that all our customers will define the chip with, okay? Now so far, they manually write that language. So they not only write the design manually, they also write the verification plan manually. And then we have all kinds of tools to verify that it is correct. This is our core business is that we have automated the 80%, 90% of once you have RTL, how to design a chip. Because it was so -- these things are so complex and expensive, you had to automate that. Now what we have never done is ability to write RTL or test bench. But now with ChipStack, we can do that because that is the core engine of LLM. So we have these -- and we have a new method -- and ChipStack has a new way of doing it using a mental model and knowledge graph. So it's a much better use of LLMs. And we can write the RTL, and then we can write the test bench because verification is as important as design. So this is an entirely new product category where there was no automation. So there's a lot of customer pull to deploy that. And then to verify that this RTL or test bench is correct, of course, it runs a lot of the middle layer or the base tools. So then we will monetize as an agent plus the use of the base tools.

So the optimization here is really just in relation to the test benching as verification and the process flow. But equally, it's a pull-through on the base software layers as well on your tool sets. Pretty clear. Maybe let's jump to IP because it's been something that's been something of a focus. And I've heard you earlier today talk about this as being super hot as a category area, maybe not so much for others in the field. But maybe help us understand what are the dynamics behind the growth in IP with Cadence at this point? And is this supported by recent acquisitions? Or is this a moment in time perhaps driven by SerDes and other standard libraries?

Yes. So IP is doing well. And actually, this is the -- we normally don't talk about it if it is a onetime thing. We only talk about it now. So it's the third year of very good growth we will have. So that's our style anyway. We don't want to say things unless they are fully verified. So I feel very good about IP. We are at third year of very strong growth. And there are multiple reasons for that. One is that our products are better. We finally have a good team. We always say team, technology, customers, right? So we have a great team finally in IP. So our products are doing pretty well, especially in advanced node TSMC, which is the most exciting part of the market. Our portfolio has grown. That's the second reason. And more on AI HPC side. So there, we want to focus on some high-value IPs like HBM. Now that, we did acquire from Rambus. That's a great acquisition. But then DDR is organic, UCIe, PCIe, SerDes. So I think the portfolio is better. That's the second reason. And third reason is there are more and more foundries. Like -- of course, TSMC is doing remarkable, but there are at least 3 major advanced node foundries of -- sorry, 4 with Intel, Samsung, Rapidus and TSMC. So that's also driving more demand for it.

Yes. Okay. Pretty clear. And maybe just with the chiplet coming into focus, and I've heard you talking about COT and hybrid COT sort of designs coming through, how does that all make a pull on the IP business for you as well?

Yes. I think that trend is good for both EDA and IP business. Because as customers do more and more of their own chips, they use more EDA tools. And also, because these things are so big and they're moving so fast, right, every year, every other year, the customer, of course, wants to focus on their key part. So if you can buy a standard-based IP which is good from Cadence, they would rather buy it and focus on the CPU part or the AI part or the auto chip part. So I think as long as we can deliver good perform PPA, the customers will rather buy that. I mean not all of them, but enough of them want to focus on -- some customers will do IP themselves because they think that's a differentiator. But a lot of them will buy it because they want to focus on some other part of the...

Got you. Makes sense. Maybe just turn to the core EDA business. I mean, I think you've guided up something close to 12-plus percent for this year. Last year, you grew about 13%. So clearly in that sort of low teens, moving back into that sort of category. What's the durability on the growth here? And what should we be thinking about as indicators for growth in the next couple of years?

Yes. I mean, if you look at it, we always look at growth plus margin together. We have, I think, world-class margins. Because that's what our investors want, right? We want to grow at a certain rate, but we want the profitability to be better than that. And then we buy back some stock, so we want EPS to be even better than that. So last year, we grew like 14% and EPS grew around 20%, right? So this formula, we have done for several years. And -- but if you look at a Rule of 40 metric, I think we are in the high 50s, right, last few years. So I feel good about that. And I think we will definitely -- my goal is to crack 60.

60?

Yes, yes.

Okay. Make sure somebody noted that. There we go.

So that's a combination of growth, but also, of course, we need to make sure the margin is good. And if you look at our incremental margin -- I mean, our margin last year was 45%, but incremental margin was 59%. Like if we add $100 million more in revenue, we added $59 million in profit. And that's also making our internal operation more and more efficient with AI and things like that. So yes, we always look at both. But yes, my goal is to cross 60. And that should be good for our investors.

Yes. You would have thought. You did mention Hexagon, and congratulations on closing that deal. Maybe just help us understand how this all fits into systems design and analysis? And when do you think that can make an impact, particularly on the margin side for Cadence?

Yes. I think any M&A, normally, whatever company -- I mean, Hexagon or the simulation business of Hexagon is a great group, great company. They're one of the original simulation companies. It was just not ideal in Hexagon because Hexagon is more hardware company than software, and they realize it would be better with Cadence. But anything we buy is never as profitable as Cadence. So -- but it takes us about a year or so to get it to that -- to better profitability. So I think definitely, this year, there is some hit. I mean, most of it is not on operating part. Most of it is on financing side because there is some dilution or there is some debt. But we will take care of that. And next year, it should be accretive.

Okay. Makes sense. Maybe just turning to China. We did see pretty decent growth last year. And this was despite, I think, some of the concerns you had expressed that this could be a strange year, '25. It turned out to be 18% growth. And this year has gotten off to a good start. How do you think that will continue to grow through this year? And what are the dynamics that you're looking at in China, certainly by EDA, but also in the IP space as well?

Yes. China is doing -- I mean, did well. It was very turbulent in '25, and we wanted to be prudent in our guide in the beginning of '25. I mean, I don't know that all those things would happen, but there was just a lot of uncertainty so we want to be more careful in beginning of '25. This year, I think -- I mean, it's difficult to predict, but the environment seems more stable than beginning of '25. So this year, we think China will grow. And we'll see how much it grows because it's difficult to predict by region. The growth rate by region is like double derivative. So we'll see how much it grows, but the environment is good. There's a lot of design activity. Physical AI is big in China, of course. And even a lot of the other parts of the market. So I feel good about China right now.

Got you. And no competition from the local guys in that market either?

Well, there's always some competition, I think. But again, we want to make sure our tools are best-in-class. And EDA, we have a very good position in China. Hardware, we have a very good position, Palladium. IP, we do less in China historically. Because IP, we are focused more on really advanced node and AI. But in EDA and hardware, yes, it's good, and it should grow.

Got you. Before I move to further questions, I'll just maybe give the floor an opportunity to ask Anirudh directly anything.

I'm curious about the [indiscernible] and the SRAM-related chips. Do those all need your EDA tools to design, Anirudh?

Absolutely, yes. Any kind of chip, you need. I mean, there will be a lot of innovation on the hardware side and software side. So yes, no, all of these will -- you can't design them by hand. They have to use our tools. And they will need Palladium, they will need our EDA software. They will need IP. I mean, one thing I want to say, it's very difficult to predict, but I mentioned this earlier also that -- like some people -- I talk to some of our customers, they say, "Oh, the inference demand will go up by 1,000x in the next 5 years." And that's amazing, and maybe a little more than that, right? So -- but then we have to normalize that with the improvements in hardware and software. So this is from current levels. So I think there was that customer or that one already assumed that the hardware will improve by 10x. They assume software will improve by another 10x. So the actual improvement is 1,000 divided by 100, okay? So which is 10x. By the way, 10x over 5 years, 60%. Even if that gets modulated by power and other things, maybe it's 30%. So what I'm trying to say is that you know this already that it will not be static. The hardware and software will improve dramatically, whether it's this new hardware architectures or advanced nodes. Software will also improve, right? I mean, software has already improved a lot. And all these new CS algorithms will be applied to AI, right, whether it's partitioning, abstraction, latency, also the lower precision. All those things that happened in CS over 30 years will apply to AI. So I think it's going to be very exciting. Now of course, it's possible the software improves even more, right, than 10x. But then a lot of times, the software improves more than 10x, the demand can go up even more, right? So it's like a very exciting double exponential, but I think it will be great to see all this innovation.

Yes. Makes sense. One area we didn't touch on was hardware. I know it's an area that you've done really well in, particularly with the launch of Z3 over a year or 2 ago. Any updates you've got there? Because it does look as though there's quite decent growth. It's represented well in backlog. And by the way, congratulations for your record backlog as well. So maybe walk us through that. How does hardware grow this year?

Yes. So hardware, when we say hardware, I know you know that it's like a full stack. So we make our own chips. So we also make our own chips to accelerate logic verification. So what happens is at the verification level, in chip design, there are 2 kinds of software. So one is like a more Boolean, if you remember, like 0, 1, Boolean logic, like how GPU or CPU will work. There's a lot of Boolean logic. And then the other part is numerical. Like simulation or timing, power, noise, it's more numerical. So for numerical, we can accelerate it with CPU and GPU, okay? For Boolean, we build our own custom processor. It's a Boolean supercomputer. It's as complicated as any processor in the world. And when we do that, it runs like 1,000x faster than standard silicon. So we are our own kind of designer, using our own products. So when we put that together in hardware and software, those things -- this is called Palladium -- become indispensable to design of modern chips. So all the big chips right now are designed by our product. Because you want to verify -- see this is what happened in the old days, you would design a chip and then do software development, and it would come out of -- to production, right? Any CPU or GPU. But the issue is that you don't want it to be wrong because if it is wrong, you have to iterate, okay? That's one problem. Second problem is the customers want to overlap hardware and software development. You don't want to wait until hardware silicon is ready and then start writing software because that takes too long. So the demand for Palladium is driven by these two things. So what happens then is we overlap hardware and software. So the customers are writing software when no silicon exists. So that's why they use Palladium to emulate the silicon. So there are two advantages. One, you can start writing software. You can boot like Android or Windows or iOS, whatever you want. And the second is you can make sure that the silicon is correct. So it became like -- and to do that, you need to run 1,000x faster because if you run on a regular CPU, it's not going to be fast enough. So this is the reason that Palladium became like indispensable tool for chip design. So now as the chips get bigger, you need more and more Palladium capacity. And then as there are more and more software, as the system companies start doing silicon, I mean, there are system companies because they have software and hardware, they need to run more Palladiums. So I mean, we have like 6 years in a row of record growth in Palladium. And so I think this year will be another record, and we'll see how it goes. But whenever we start the year, we are more prudent in the assumption. But I'm pretty bullish on Palladium this year as well.

Got you. Maybe with a couple of minutes to go, I have to ask about how you're going to monetize the Agentic EDA. So when we go back -- if we go back to ChipStack. And John was pretty clear on the callbacks, that this could be -- this is on a value-based basis. And this will be perhaps based on tokens. So maybe help us understand, how does that work? And could this be margin accretive in a couple of years' time for the group?

Yes, I mean, we always want to be margin accretive. You know us, right, over all these years. Every year, we're trying to be. But this is another big thing, right, that can help us. So again, yes, I think it will be token-based. And there are all these -- I mean, we want to have a base subscription plus tokens on top. That's how we want -- because these new tools will be new product categories. And then as they consume work, they can use tokens. And this kind of model in AI that is well established now. So we would hope to have a base subscription plus tokens. And that also gives good visibility to our customers, and it's good for us.

So they can see the meter, basically. Yes. Makes sense. It looks like we've run down the clock. Anirudh, thank you very much.

Thank you. Thank you very much.