Intel Corporation (INTC) Earnings Call Transcript & Summary

Today's events include forward-looking statements about our process technology and other topics, which are based on our current expectations and subject to risks and uncertainties. Please refer to today's press release at intc.com for more information on the risk factors that could cause actual results to differ materially.

Good afternoon, and thank you for joining us today. It's great to be with you again. Back in March, shortly after I rejoined Intel, I unveiled the evolution of Intel's integrated device manufacturer, or IDM model, IDM 2.0. This is our winning strategy to remain a leading developer of process technology, a major manufacturer of semiconductors and the leading provider of silicon globally during what I believe will be a sustained period of global demand. There are 3 key aspects of IDM 2.0. First, we will continue to build the majority of our products in our internal fabs using our internal factory network. Second, we will expand our use of third-party foundry capacity across our portfolio to deliver the best products in every category in which we participate. Third, we will invest to become a world-class foundry business and a major provider of U.S. and European-based capacity to serve customers globally. Since we last spoke, we have been moving at a torrid pace to deliver on this strategy. I am proud of the progress we are making, but there is still so much more to do. In addition to the more than $20 billion in investments we announced previously for our Arizona site, we shared additional investments, including the $3.5 billion in our New Mexico facility to support manufacturing of our advanced packaging technology, and there is more yet to come. While a primary focus of our last webcast centered on the strategic decisions and investments we've made to build more manufacturing capacity, today, I want to zoom in on our process and packaging technologies. Delivering leadership products requires the right combination of process and packaging, silicon and platforms, software and at-scale manufacturing. This is a combination only Intel has, including our own Question leadership and breakthroughs in areas like 3D packaging technology. But as you've heard me say before, we need to accelerate our clock rate of innovation. Today, I will share with you 1 of the most detailed road maps we have ever provided spanning process and packaging technologies, a road map that shows how we will continue our own question packaging leadership and how we will get to process performance parity and then leadership sooner than you think. Before we dive into the technology and what customers can expect from us in the future, I'd like to first tackle one of the more confusing issues faced by our entire industry, no naming. Intel, like the rest of the industry has recognized that we need to evolve the way we talk about process nodes. For those not as familiar with how we build chips and what we mean by nodes, let me give you a simple explanation of a few critical pieces relevant to today's discussion. Microprocessors consist of billions of transistors connected together in a specific pattern. These transistors are on/off switches that process the 1s and 0s of electrical data. A region at the top of the transistor is called the gate. And this determines whether the transistor is on or off. The process node refers to the intricate recipe for thousands of steps we take to build these transistors. The goal is to make them smaller, faster, cheaper and more energy-efficient, all of which leads to more powerful chips. Originally, process nodes were named after the physical length of these transistor gates and were measured in microns. As transistors became smaller and the gate length shrank, we started measuring in nanometers. In 1997, as the technology continued to progress, other innovations such as strained silicon, aside from just shrinking the transistors, became equally important to making them faster, cheaper and more energy efficient. This is when the traditional naming approach stopped matching the actual transistor gate. The industry diverged even further in 2011 following our introduction of FinFET, which was an entirely new way of building transistors with unique shapes and structures. These days, the various naming and numbering schemes used across the industry, including ours, no longer refer to any specific measurement and don't tell the full story of how to achieve the best balance of power, efficiency and performance. So today, we are refreshing our lexicon to create a clear, consistent and meaningful framework to help our customers have a more accurate view of process nodes across the industry to make better-informed decisions. Let me walk you through it. We are already in high-volume production with the 10-nanometer SuperFin node that we introduced last year with the largest single intra-node enhancement in Intel's history. This name will not change. Based on performance and power projections, our next node, which we previously called Enhanced SuperFin now becomes Intel 7. Intel 7 will be followed by Intel 4 and Intel 3. After Intel 3, the next node will be called Intel 20A. This last change reflects that Moore's Law is alive and well. As we get closer to the one node, we will be moving to naming that better evokes a new era where we are crafting devices and materials at the atomic level, the angstrom era of semiconductors. We have a clear path for the next decade of innovation to go to one and well beyond. I'd like to say that until the periodic table is exhausted, Moore's Law isn't over, and we will be relentless in our path to innovate with the magic of silicon. Our new names are based on key technical parameters that matter to our customers: performance, power and area. We'll go through all this in more detail today. A few of the technologies we have talked about before and others, you'll be seeing for the first time. To help unpack the incredible innovations Intel is delivering today and developing for tomorrow, I'd like to welcome the leader of our global technology development team, Dr. Ann Kelleher. Ann?

Thanks, Pat. It's a pleasure to join you today. Process and packaging are at the very heart of Intel's heritage and the foundation of everything we built. Today, we will unveil our process and packaging road maps that show how we're accelerating to deliver an annual cadence, our process and packaging innovations through 2025 and beyond. With the exploding demand for silicon across a swath of applications, it's also important to emphasize that many of the innovations we discuss today will also be available to our Intel foundry services customers. We have many innovative technologies to cover, and I'm really excited for you to see what we've been up to. First, let's begin with what we have in production today. We have made tremendous progress with our Intel 10-nanometer process technology. Again, remember that the new naming structure will begin with the node after 10-nanometer SuperFin. We have ramped our production into high volume in 3 factories. That's in Oregon, Arizona and Israel. Furthermore, our volume production has crossed over. This means we are manufacturing more Intel 10-nanometer wafers than 14-nanometer wafers. In short, 10-nanometer is doing really well. Now let's look ahead at what's coming, starting with our next process generation. We have previously referred to this node as enhanced SuperFin. We're expecting an approximately 10% to 15% performance per watt increase over 10-nanometer SuperFin as we evolve the node with additional transistor-level optimizations. This is equivalent to a full node of performance gain. As a result, we believe that Intel 7 is an appropriate name to help customers understand the kind of competitive performance being delivered by the node. Intel 7 realizes this big jump in performance had 2 amazing innovations, including moving electrons through the channel faster by using increased strain and more lower resistant materials; delivering better energy control through novel, high-density fashioning techniques and streamlined structures; enabling improved power delivery and better routing and higher metal stack. We will begin shipping products on Intel 7 later this year. The Alder Lake client family will start rolling out in 2021, followed by Sapphire Rapids for the data center, which will be in production in the first quarter of 2022. Intel 4 comes after Intel 7 and will be ready for production in the second half of 2022 for product shipping in 2023. These products include Meteor Lake for client and Granite Rapids for the data center. In March, we told you we had put the previous issues with this process now behind us. I think it's important that we spell out what that means. First, we hit an important milestone when we taped in the Meteor Lake client compute tile last quarter. Beyond the actual wafer, we're right where we expect to be relative to our performance and defect density expectations. Indeed, our defect density trend is on the right path to meet our product commitments. Intel 4 is also our first node to fully embrace the use of extreme EUV lithography or EUV. EUV involves a highly complex optical system of lenses and mirrors that focuses a 13.5-nanometer wavelength of light to print incredibly small features on silicon. This is a vast improvement over prior technology that use light at a wavelength of 193 nanometer. Intel and ASML have a long working relationship, and we are confident that working together, we will be able to support our requirements. As EUV evolves, Intel plans to adopt the latest tools as soon as they become available. This ensures our fabs have the latest features from ASML to deliver the highest productivity in support of our technology requirements. Ramping EUV into volume requires an entire ecosystem surrounding the equipment, photoresist, mask generation, pellicle production and metrology. And we have put a great deal of effort into building this ecosystem. In fact, Intel's IMS subsidiary is the primary supplier of EUV Multi-Beam Mask Writers worldwide. These tools are essential for creating high-resolution masks, which are a critical part of enabling EUV lithography. This mask writing technology is a competitive advantage for us as well as a key enabler for the industry. We are working together also to define, build and deploy the next generation of EUV tools, referred to as high numerical aperture EUV or high-NA. High-NA will integrate even higher-precision lenses and mirrors, improving resolution and allowing for even smaller features to be printed on the silicon. We expect to receive the first production High-NA EUV tool in the industry and intend to be the first to implement High-NA in production beginning in 2025. Progress also depends on close collaboration with other key industry players. Our partnerships with equipment vendors, including Applied Materials, Lam Research and TEL are critical to enable our road map and leadership technologies. I am so proud of the work we have done on EUV lithography and other equipment technologies over the last several years. Intel 4 will be followed by Intel 3, which will be ready to begin manufacturing products in the second half of 2023. Intel 3 will continue to reap the benefits of FinFET. In fact, our early modeling and test data is showing that Intel 3 will deliver around an 18% transistor performance per watt increase over Intel 4 along with additional improvements in power and area. These amazing results derived from several factors, including the addition of a denser higher-performance library beyond Intel 4; increased intrinsic drive current to fully optimize the FinFET transistor, an optimized interconnect metal stack with reduced via resistance; and increased use of EUV compared to Intel 4. This is a higher level of improvement than a standard full node improvement for us. Our next node after Intel 3, as Pat said, will be called Intel 28, marking the start of the angstrom era of semiconductors. Intel has a long history of foundational process innovations. We led the transition from strained silicon at 19-nanometer to high-K metal gate at 45-nanometer. We led again with the introduction of FinFET at 22-nanometer. All these innovations propel the industry forward by leaps and bounds as we continue the relentless pursuit of Moore's Law. Intel 20A will be another watershed moment in process technology when we introduce it in the first half of 2024. It will feature 2 groundbreaking technologies, an entirely new transistor architecture named RibbonFET, a first of its kind innovation called PowerVia, to improve power delivery. Here to tell you more about both of these amazing technologies is Dr. Sanjay Natrajan. Sanjay leads the team developing our future process technologies. Sanjay?

Thanks, Ann. I am pumped to take the wraps off 2 innovations that I believe will transform silicon process technology as we continue to push the boundaries of physics. The first is our new backside power delivery network called PowerVia. This is a unique technology developed by Intel engineers and will make its debut in Intel 20A. Traditional interconnect technology connects on top of the transistor layer. With the resulting intermixing of power and signal wires, routing inefficiencies arise, hampering both performance and power. Our solution is a novel process where the power wires are placed underneath the transistor layer on the backside of the wafer. By eliminating the need for power routing on the front side of the wafer, more resources become available to optimize signal routing and reduce delay. This also enables better power delivery by reducing droop and lowering noise. This allows us to optimize for performance, power and area depending on the product needs. We have been perfecting this process over the last several years, and PowerVia will be an industry-first deployment of a backside power delivery network. As we look to productize this innovation, our defect density, performance and reliability give us confidence that it will be ready to ramp into production. In fact, we expect to test PowerVia on earlier nodes to ensure this groundbreaking technology is fully ready before it ramps in volume with Intel 20A in 2024. These test chip and sim images show the structure of our PowerVia here. We can't wait to get PowerVia into customer products so that they can reap the benefits. And there are even more innovations to come. Intel 20A will also introduce our first new transistor architecture since we pioneered FinFETs in 2011, Gate-All-Around transistors. Gate-All-Around has been in development across the industry for several years, and the name comes from the transistor architecture. Wrapping the gate completely around the channel means better control and a higher drive current at all voltages. This delivers faster transistor switching speeds, which ultimately translate to higher performance products. And by stacking multiple channels called nanoribbons, we can achieve the same drive current as multiple fins but in a smaller footprint. Our implementation of nanoribbons enables the width of the ribbons to be modulated to accommodate multiple applications. We call our version RibbonFET. These test chip and sim images show the architecture of our RibbonFET. Based on test chip measurements, we expect our RibbonFET transistors to deliver performance and density improvement beyond today's FinFET transistors. The introduction of Intel 20A with PowerVia and RibbonFET highlight Intel's innovation leadership. Beyond Intel 20A, Intel 18A is already in development for early 2025, with refinements to RibbonFET that will deliver another major jump in transistor performance, along with clear process performance leadership. But you're going to have to wait a little longer to hear more about that. Because predictability is critically important to our customers, we have put a concerted focus on schedule predictability throughout our development process. This frees Intel's innovation engine to lead in high-differentiation areas such as PowerVia and RibbonFET. I am truly proud of the team and can't wait for our customers to realize the incredible benefits of products built using these technologies. Back to you, Ann.

Thanks, Sanjay, and thank you to you and your team of engineers for their hard work on delivering these innovations. Our engineers in the fabs in Oregon, Ireland, Israel and Arizona are working to get the sites ready for Intel 4, Intel 3 and Intel 20A production. Another area in which Intel is driving industry-leading technologies is advanced packaging. Packaging is becoming even more important as we now need to scale and stack tiles vertically to realize the effects of Moore's Law. Packaging is also a crucial component for our IDM 2.0 strategy, enabling us to create leadership products, incorporating disparate nodes and processes. Let's start with EMIB, Intel's 2.5D solution. Now Intel has been shipping EMIB since 2017, but here's a quick video refresher on the technology. [Presentation]

Not only will Sapphire Rapids be the first Xeon product to ship in volume with EMIB, but EMIB enables Intel to build products that were impossible a couple of years ago. Indeed, Sapphire Rapids really is a big deal. It is the first dual-reticle-sized device, delivering nearly the same performance as monolithic designs in the industry. That's a great achievement, but we have to build it in a cost-effective manner. Here again, EMIB is a great solution. Sapphire rapid structural costs will benefit from EMIB's inherent efficiency of using local silicon interconnect embedded in the substrate versus using a large silicon interposer. By comparison to a standard package interconnect, EMIB has twice the bandwidth density and 4x better power efficiency. With current EMIB technology already in production, we are working on the next generation of EMIB, starting with solutions for future high-bandwidth products. Our next-generation EMIB will scale from the existing 55-micron bond pitch to 45 microns, and we'll then move to 40 microns in the third generations. We are also using that 45 micron pitch EMIB on a 92 x 92 millimeter package, which will be the world's largest ball grid array package. As we look at Foveros, Meteor Lake is our second-generation implementation of this advanced packaging technology in the client product. Meteor Lake with Foveros will feature a microbump interconnect pitch of 36 microns, tile spanning multiple process technology nodes on the same product, a dynamic thermal design power range from 5 to 125 watts. We can't wait to get Meteor Lake into the lab for testing in anticipation of volume manufacturing. And as we said in March, our Ponte Vecchio GPU will be the first product powered by both EMIB and second-generation Foveros. In addition to assembly technologies that enable interconnect scaling, we have industry-leading advancer technologies that allow higher precision identification of non-good as prior to EMIB and for Foveros base packaging. These innovations help us optimize product performance and yield, which are keys to affordable manufacturing. Intel's foundational advanced manufacturing technology, EMIB and Foveros, along with our assembly and test technologies, enable us to deliver leadership products to our customers that redefine integration. As Pat pointed out, many of these innovations and technologies will be available for both Intel products and our foundry customers' products. But we are not resting on our laurels, and are working on innovations beyond EMIB and Foveros. If you look at the road map we presented at Architecture Day last year, we briefly talked about 2 new technologies: omnidirectional interconnect, which we are calling Foveros Omni and hybrid bonding interconnect or Foveros Direct. I'd now like to welcome Dr. Babak Sabi to join us and share more about Foveros Omni and Direct. Babak. leads the team driving our road map of future packaging innovations. Babak?

Thank you, Ann. Let's start with Foveros Omni, which we expect to be ready for volume manufacturing in 2023. Foveros Omni provides unbounded flexibility for modular design and die-to-die interconnect as part of our ongoing shift to wafer-level packaging. As the name Omni implies, Foveros Omni allows integration of multiple disaggregated top tiles with multiple base tiles. Both the top die tiles and base tiles can be mixed across fab nodes. With this flexibility, the design possibilities and performance improvements are literally endless. This sounds like magic, but here it is in reality. Foveros Omni uses a combination of through-silicon via and through-packaged copper columns to balance high-speed signal and power delivery with dense die-to-die interconnect. It improves on the original Foveros with die-to-die interconnect starting at 36-micron and scaling down to 25-micron microbump pitch, which quadruples pump density to 1,600 IOs per millimeter square, all while delivering the same interconnect power of Foveros at 0.15 picojoule per bit. Now let's look at the hybrid bonding, which will also be ready for volume manufacturing in 2023. We call it Foveros Direct. The name Foveros Direct stems from the move to solderless copper-to-copper bonding, which enables lower resistance interconnects. This technology will transform heterogeneous integration and truly takes packaging technology to the next level. We are blurring the lines between where the wafer ends and where packaging begins. Foveros Direct enables sub 10-micron bump pitches. This provides an order of magnitude increase in the interconnect density for 3D stacking, the resulting capability of 10,000 IOs per millimeter square opens up new concept for functional die partitioning that were previously unachievable. For example, one could have a multilevel cache or logic stacking on a die, with very low latency, without any power penalty. I can't wait to get this 2 new packaging breakthroughs into customer hands in 2023. Our unique advantage is the ability to combine any of these leading advanced packaging capabilities to create truly amazing products. With that, I'll send it back to Ann.

Thank you, Sanjay and Babak. This is absolutely amazing stuff. At the end of the day, all these technical innovations mean our customers can count on Intel to continue delivering products with improved performance and lower power consumption. These products will fuel the continued digitization of everything and create world-changing technology that improves the lives of every person on earth. But of course, there is more. I want to take a moment and preview what we're thinking about beyond 2025. On the process innovation front, there is more to Gate-All-Around and backside power, and this is already in the works. For example, we are already working on future nodes beyond 2025 that utilize stacked-in masks and PMOS and take Gate-All-Around to the next level. To continue our leadership in advanced packaging, we're looking beyond the delivery of Foveros Omni and Foveros Direct in 2023. As we continue to push the envelope in advanced packaging, we will be transitioning from electrical to optical packaging with integrated silicon photonics in future generations of our technology. And of course, we continue to work closely with partners in the industry, including Leshi, IMEC and IBM on these and many other innovations to further our process and packaging technologies. With that, I'll hand it back to Pat to close out today's webcast.

Thank you, Ann, Sanjay and Babak. Wow, truly awesome. I hope you've enjoyed seeing a bit more detail on what we're doing and hearing from some of the smartest technologists leading our innovation engine. Collectively, these innovations will continue our leadership in packaging and will put us on a clear path to process performance parity in 2024 and leadership in 2025 with the introduction of RibbonFET and PowerVia. It's also important to remember that all what you've seen today is being developed here in the U.S. In fact, the process technologies we've discussed today will begin high-volume manufacturing in our Oregon fabs. If you think about it, we are the only leading-edge player doing both R&D and manufacturing in the U.S., creating a domestic lab-to-fab pipeline. But even more needs to be done to ensure a geographically balanced supply chain for the world. This is why we're aggressively adding capacity across our fab network. As you've heard me say before, we expect to announce the sites for our next expansions in Europe and the U.S. before the end of this year. These will be large investments enough to support mega fabs, and it's how we will help the world get to a more balanced and sustainable and secure supply chain. While we are already moving forward with some of these investments on our own, we applaud the policymakers in both the U.S. and EU for acting with urgency on programs that will accelerate our progress and the progress of others in the industry. We are encouraged by the recently announced CHIPS Act to support semiconductor manufacturing and R&D in the U.S., and we're excited by similar efforts underway in the EU. In summary, Intel is innovating the future of process and packaging technology. Intel will deliver those innovations on a regular cadence, will enable a wider cross-section of the industry to take advantage of our amazing technology. Like I said earlier, we are moving at a torrid pace, and the industry is responding eagerly to the fact Intel is back. So let me close by emphasizing the progress we are seeing with our own foundry business. One of the strengths of IFS is that we offer both leading-edge process and packaging innovations as well as modernize access to our historical technologies. The interest from customers in IFS has been strong, and some of the most intense energy has been in our proven advanced packaging technologies. I'm thrilled to announce we have signed AWS as our first customer to use IFS packaging solutions, but there's more. I'm also excited about the opportunity to partner with Qualcomm using our Intel 20A process technology. Both Intel and Qualcomm believe strongly in the advanced development of mobile compute platforms and ushering in a new era in semiconductors. IFS is off to the races. We have dramatically accelerated our innovation pipeline. And wow, that was quite a lot of process and packaging ground to cover. And you can hear even more about Intel's incredible innovation machine at our Intel Innovation Event on October 27 and 28. Join us in San Francisco or virtual. This event will be fully hybrid. Thanks for your attention. With that, let's go through some live Q&A. I'm excited to be here in the studio today with Ann, Sanjay and Babak, and we'll be happy to take questions. So operator, how about a reminder of how folks can ask questions and then send us the first one.

[Operator Instructions] And our first question is from -- I'm sorry, from Ian Cutress of AnandTech.

Great presentation. Love the detail. I would like to ask, though, because Intel's foundry services, yes, its strong commitment to delivering high-performance semiconductors in the next 5 years, it would naturally suggest that Intel might start working with traditional companies that have been competitors for decades. Aside from Qualcomm, are there any highlighted names to note here that you can discuss that you're going just beyond talking to because talk is kind of cheap?

Well, I'm very excited about Qualcomm's announcement today. And obviously, they did a lot of technical diligence with us over the last couple of months on Intel 20A, and it's a strong statement right, of how far along we are in 20A and their belief in its strength as a leadership process technology that they can commit a major mobile platform, too. So quite excited about that. We've also said we have over 100 customers in the pipeline, and those engagements are progressing very well. Some of those are the packaging technologies, like our AWS announcement. Some of those are what I call modern nodes, Intel 16, our 16-nanometer process. And a lot of interest in Intel 20A and Intel 18A is already underway. Beyond the 2 names we have today, we don't have any others to announce right now. Some of these are very traditional names, some who might be seen as competitors of ours in the past, but now we're working with them in this exciting area, some across industrial and auto companies some as other semiconductor companies that need a foundry opportunity to leverage as well as others in the industry. So overall, a breadth of customer engagements across a range of industries, across a range of the technology offerings. As I said, IFS is off to the races. Next question?

And our next question is from C.J. Muse of Evercore ISI.

Yes. I guess, Pat, wanted to dig a little bit deeper into EUV, clearly, an important part of the presentation today. And it looks like really adopting an Intel 4, which is your old 7. So it doesn't seem like a change statement there. But 2-part question. Number one, are you worried about falling behind on the learning curve? What are you doing to kind of accelerate your learning there? And then secondly, given that it sounds like you're not able to get meaningful slots until 2023, does that mean that we should see meaningful outsourcing to TSMC over the near term until you're able to get to that parity in 2024?

Yes. So overall, the EUV engagement, and I'll ask Ann to help me here in a second. Overall, we're seeing great momentum. And as I like to say, it's easier to be #2 in the bike race than it is to be #1. And you're able to just catch up much more quickly by exerting less energy, and we're really leaning on the learnings that we have from ASML and the deepening relationship that we have with them. Also, the other industry, IMEC and IBM that we're working with. So we're able to catch up quickly. But as you heard us say as well, unquestionably leadership position around high-NA or high numerical aperture. So that relationship, very critical. We believe that we have adequate capacity of the EUV machines, and we're working very closely with ASML to ramp our capacities internally. Separately, we've talked about our use of external foundries in the 2023 and 2024 road maps, and that will augment our internal capabilities. As we said, IDM 2.0 is the majority internal, right? It's leveraging foundries as well as then being a foundry for the industry. So this is entirely consistent with our overall strategy. And Ann, maybe a few more comments just on how well the EUV ramp is going for us these days.

Thank you, Pat. And I'd like to echo what Pat said. Lithography team, which is part of the technology development, has a very strong working relationship with ASML. And the teams are working together, not only in setting up the technology for our Intel 4, our Intel 3, and our Intel 20A but we're also working on the productivity of the tool sets and basically the manufacturability of the tool sets. So based on the work that we're doing, we believe we are really well positioned as we go into the ramp of Intel 4 and beyond.

Our next question is from Kevin Krewell of Tirias Research.

Just wanted to clarify something that it's great that Qualcomm has committed to the 20A technology because that looks really impressive. Is this going to be all the foundry customers get access to Intel new processes as Intel internal customers?

Yes. Thank you for that, Kevin. And the simple answer is, yes, we're going to be making the capabilities of IFS available very early, if not concurrent with our own design teams internally. And what we described today with Qualcomm on Intel 20A is they're essentially concurrent with our own internal ramp-up. So in summary, we're making the best of Intel available to our foundry customers, and this is part of the excitement that we're seeing from the industry as they look at IFS and look at this new engagement model with Intel. And Amazon, wow, they're saying, "Boy, I can now collaborate with Intel in new and exciting ways." Qualcomm, somebody that we wouldn't have partnered with in the past now engaging us in deep and strategic manners. And these are just the first 2 of what we believe will be many, many such engagements as we look to the future. And we said widely that this will include people who are customers, people who are partners and people who might have been considered competitors in the past. So the Intel fab doors are open wide to the industry, and we look forward to many of these announcements in the future.

Our next question is from Ross Seymore of Deutsche Bank. .

Thanks so much for all the great details on the aggressive plan to accelerate the road map and clarify the naming of it as well. I wanted to get to the Tick-Tock side of things that you said on your recent earnings call that Intel was going to return to. Historically, you did that so you weren't putting out new process technology and design simultaneously, mitigate some of the risk, et cetera. But it seems like in this instance to catch up to the competition, to get back to parity and then a leadership position. You're doing both simultaneously. And you're talking about giving high levels of scheduled predictability -- of not only the node side of things for your foundry customers down the road, but also for your internal customers, the traditional customers, how do you balance doing these simultaneously having the process technology and the design changes happening simultaneously to ensure the scheduled predictability that you're desiring?

Yes. And the idea of Tick-Tock was always to limit the amount of new risk and new innovation you're taking at any 1 particular moment in time. And for instance, the leadership product on Intel 20A will be a client product, but it will be a proven micro architecture design that will be first put on to Intel 20A. So the design is low risk, but the process technology will be higher risk and higher innovation. Also, and I'll ask Sanjay to add here a bit, we also mentioned that the PowerVia technology. And it, as well as RibbonFET will be part of Intel 20A, but we'll have already proven that in an earlier node, and this idea of limiting the risk that you're taking at any point in time and really building on that capacity. We've already built much more parallelism into our design teams, into our R&D teams and giving them the capacity, both capital capacity and R&D capacity to have more parallel innovation going on across them. Sanjay, since you're responsible for this? Maybe you might add a few thoughts.

Thanks, Pat. Yes, I'd love to. So just as Pat outlined, we have this torrid pace of annual -- almost annual cadence of new process technology from Intel 7 to Intel 18 in 4 years. That, as Pat alluded to, is a well-funded effort. It's -- we have funding for people, funding for the equipment, funding to really enable us to take these chunks and get each chunk done in a healthy, high-yielding, robust manner. We also, with this annual cadence, have limited the scope of each of these things to be more manageable to be completed in this amount of time. Pat alluded to PowerVia on Intel 20A. And one of the ideas we're doing to manage the risk is to exercise PowerVia on an earlier technology. So we will have options, test chips, detailed options to take PowerVia and combine it with something like Intel 3. So we can do the derisking work of PowerVia before we go into Intel 20A and combine it with RibbonFET. So this is one of the ways we're trying to just manage the risks so that each of these changes is going to deliver on time exactly as we promised.

So thank you, Sanjay. And I'll just say the spirit of Tick-Tock is alive and well. We're just doing it at a very torrid pace. Next question, please.

Our next question is from Mark LaPedus of Semiconductor Engineering..

Quick question. One of the foundries is looking at bringing the Gate-All-Around or the so-called nanosheet sooner than later, that is at their 3-nanometer node next year. It looks like you're trying to push the FinFET as far as -- as long as possible, is there -- what's the idea behind pushing instead of bringing the RibbonFETs? What's the thinking in terms of bringing the RibbonFET at 20 versus 20A versus, say, a 3.

Yes. Thank you. Good question, Mark. And Intel has a long history of being the leadership transistor performance in the industry. If we go all the way back to strained, high-K metal gate, FinFET, just multiple generations of being able to do that. And as we look at Gate-All-Around, we're building a transistor that is unquestionably the highest performance. And again, Sanjay, maybe you could add a few more thoughts on this.

Yes. Yes. Thank you, Pat. Thanks, Pat. I'd love to. So if I talk first about FinFET, as Pat said, we have a tradition and a long history of innovation on planar transistors and on FinFET. First to do strained silicon in production, first to do high-K metal gate, first to do FinFET on 22-nanometer in 2011. As you can see, when we talk about Intel 7, Intel 4, Intel 3, we're still delivering substantial performance per watt gains on each of these nodes. So we are not out of ideas on how to continue improving a proven FinFET architecture. When we go to Intel 20A, we've made the decision to switch architectures from FinFET to RibbonFET. One thing we and our team is very, very confident about is I can't comment on the timing of whenever anyone else says they're going to do this. But I am confident that when we do this, we're going to do it best.

And our next question is from David Kanter of RealWorld Insights.

Sanjay, Ann, and Pat, congrats. It's great to see this and hear about some of these innovations. So I'm really excited for Foveros Omni and Direct, certainly for really high-performance chips like the online or AI accelerators would be a great fit. I'm wondering if you have some intuition about the scalability down sort of to the low end of the price stack. If you think about sort of mainstream notebook chips that might be closer to like $100 rather than $1,000 ASPs. Do you think we can drive those technologies into that price point both for Intel and foundry customers?

Yes. So great to talk to you, David, and thanks for the question. The simple answer is yes. And we do see that packaging technologies, maybe even more than any other aspect, have to be cost effective. And they have to be trading off all sorts of considerations at performance, power delivery, cost effectiveness, manufacturability, yield. And as we already mentioned, the Alder Lake will be 1 of the first examples of these advanced packaging technologies, which has to be very cost-effective for the mobile market. Babak, maybe you could characterize a little bit more some of the cost considerations as we look at Foveros Omni and Direct?

David, great question. Actually, if you look at Foveros Omni, it really gives you a good cost advantage over Foveros by replacing that really big silicon interposer with a small piece of silicon, giving you a very efficient direct connection. And actually, our first thought is that our first Foveros Omni product is going to be a client product in the mobile segment. So good thinking along that line there. Foveros Direct also gives us a lot more capability in terms of getting performance. Right now, we are looking both at client as well as several products, and we are examining the performance and see where is the best fit for that technology that gives us, again, another huge advantage.

Yes. Thank you very much. And I'll just say, overall, Babak and team have done just an extraordinary job to position Intel as a sustained leader in packaging technologies over now a number of generations. And we think with today's announcements, that advantage has secured multiple years' advantage well into the future. So thank you, Babak for the great job you're doing in that area. Next question.

Our next question is from Thomas Arcuri of UBS.

Pat, I was just wondering if you can give a little more detail on some of these in between nodes, to sort of bridge the gap to get to process parity in 2024. You gave a 10% to 15% performance number for the enhanced SuperFin and you gave 18% for what you're now calling 3. But I mean, I can get there if you get sort of 15% to 18% for each of these 4 nodes, but can you provide the performance improvement for which you're now calling 4-nanometer and which you're now calling 20A because you can kind of get close to where TSMC will be out in 2024, if those also have similar 15% to 18% performance improvement.

Yes. And I'll ask Sanjay to help me a little bit on this one. But I mean, we've given you some of the numbers, you do the math of where those are. I think you get to the answers that you're saying. And we've tried to do the numbering with thoughtfulness in mind of how they compare with the industry as well and the other foundry offerings. We've looked very closely at the power performance in particular, but also the area considerations. And obviously, we expect, as we go to Intel 20A and then the refinement of RibbonFET with 18A that we feel pretty confident that our best view, and we take a conservative view of where we see the competitors to be at that point in time that we're saying, yes, we'll be parity or parity plus in 2024, and then unquestioned leadership in 2025. And Sanjay, maybe you can add a little bit more specific to that.

Yes. Thanks, Pat. I'd love to. So Intel 7, like we said, we expect 10% to 15% gain over 10-nanometer SuperFin primarily through increased strain and lower resistance materials. Intel 4, we think, is shaping up to be about a 20% performance per watt gain over Intel 7. That's going to have extensive use of EUV, and we're really going to lean into EUV as a path to simplify the process and to get scaling. Intel 3 is also a pretty substantial gain. It will be our last FinFET technology, but it will deliver 18% performance per watt. We're going to have more drive current from the transistor, better interconnect resistances in the back end, even more EUV usage to allow us to shrink some of the libraries. That's how we're going to get a solid 18% off of Intel 3. And then Intel 28, it's going to be revolutionary. When we go from a FinFET to a Gate-All-Around, nanoribbon, RibbonFET. What I've said is when we do it, we're going to do it best, and you'll see that in 2024.

And of course, as part of Intel 28, you get performance benefit from PowerVia as well, right, a better power delivery network. So don't want to undersell yourself there, Sanjay.

Our next question is from Vivek Arya of Bank of America.

Historically, Pat, when Intel discussed process technology road map, it was also a discussion of the cost side and a commitment to lowering cost per transistor. So I'm curious, like-to-like, what is the cost delta between if you use kind of 14-nanometer as your very optimal baseline, how are the current cost of 10-nanometer today? Where do you think Intel 7 can take that cost structure? So just any color on the cost side would be extremely helpful also.

Yes. And obviously, we didn't cover those aspects in today's discussions very much, and we're probably not prepared to go deeply into that. But we sort of view that continuing cost performance comparison, there are aspects of that as well that get more complicated when you go to a smaller die with the advanced packaging technology. So as we go to 2.5 and 3D packaging technologies, you can think of carving up the dies differently. And smaller dies, of course, even have better cost characteristics, the larger ones and less susceptibility to defects at a given defect density level. So overall, we continue to see our ability to deliver cost improvements generation to generation. We're being very aggressive in terms of all aspects of the manufacturing wafers through fab, the productivity of the tools, our ability to keep driving defect densities. And Ann, would there be any other things that you suggest that we add to that?

I think one of the key -- thank you, Pat. I think one of the key items I'll also add, not only how we our key focused in terms of improving our performance per watt and our overall performance gain, but we have a very active program across all our technology nodes in terms of ensuring that we hit the cost in terms of -- and we benchmark that cost. We look at equipment productivity. We look at all our commodities. We look at all the components that feed into our overall wafer cost and our overall cost of our technology. So I'm very happy with the road map we have right now that we are on the right trajectory as we move from node to note.

And our last question is from John Pitzer.

Yes, Pat, Ann, thanks for the conference call. Pat, there are well-defined metrics to compare performance on front-end processors and transistor density and the like. It's less so on the advanced packaging side. And maybe you answered this partly when you answered Vivek's question, but I was hoping you could help us just better understand what you can do with EMIB and Foveros either internally or potentially at the foundry level that you can't do with other advanced technologies either on the cost or the performance side.

Yes. And I'll ask Babak to jump on this and then I'll close our time today as well. But there's a lot of things that we -- that Babak sort of pointed to, for instance, pitch densities, you allow to have more interconnect right? As we move to some of the advanced technologies like EMIB, right, you're able to decrease the size of, for instance, the interposer requirements as well, you're able to go to higher performance, so you're able to have very high-performance chip-to-chip interconnect, which essentially makes it almost like it's part of 1 die, even though you're able to go to a smaller die that have still high-performance connections associated with them. So this lever of trade-offs of packaging with die trade-offs becomes a very powerful new tool in our toolbox. Babak, would there be any other points that you want to add to that?

Yes. Thanks, Pat, so there are several metrics that we can use just to look at the connection between the 2 dies. You have the number of IOs per millimeter. That's one very important metric. The other metric is that what is the energy it takes to move 1 bit from 1 die to another in terms of picojoule per bit. So those are 2 big metrics. There are also many other important normal factors in packaging, like how well can you deliver power to your die? How well can you actually get your signals out at the speed they have. So we actually have a whole list of them. And I don't think that time allows to go through a lot more detail but I'll be happy to sit down with you and share those performance benchmarks.

Well, thank you very much, Babak, and trust me, Babak will take you through the benchmarks. So he's happy to spend as much time as you need on those topics. And Sanjay, thank you for the great updates on the breakthroughs associated with RibbonFET and PowerVia and Ann, just laying out the details of our road map. Thank you all so much. and to everybody who joined us today. Thank you for the great questions. And as you think about everything that we've talked about today, announced today, this is the most detailed road map we've ever provided for process and packaging technologies. And I hope you just take away 3 things. First, we are significantly accelerating our clock rate of innovation. 5 process nodes in 4 years. That's tremendous. And the breakthroughs within them, our first new transistor architecture in over a decade, this is substantial. -- and to Sanjay and Ann just congratulations on these breakthroughs. Second, we're in a clear path to process performance per watt parity in '24 and leadership in '25. Coupled with the ongoing leadership in packaging, we're in a great position to achieve unquestioned leadership for our customers, our industry. And as you saw from the great support from our ecosystem, including our first IFS customers, the momentum is building. Intel is back and we are picking up the pace. The torrid pace that I've talked about internally is now being felt across our customers, our partners, our industry. Thank you again for the time today. And if you like today, you got to come back in October because we're going to have a geek fest at our innovation event in San Francisco. And if I don't see you before then, I look forward to seeing you in October in San Francisco. Thank you so much.