Intel Corporation (INTC) Earnings Call Transcript & Summary

Welcome to Architecture Day 2021. In 2018, Intel highlighted the need for continued innovation in 6 key areas. Intel also identified 4 foundational compute architecture that are necessary for the next era of compute. Since then, Intel has continued to execute this vision, shipping technologies and products like Ice Lake and Tiger Lake CPUs, Intel's first discrete GPUs on Xe LP architecture and Agilex FPGAs. In March, Intel announced our new manufacturing strategy, leveraging both internal and external Fab infrastructure. In July, Intel unveiled one of our most detailed road maps yet, extending the promise of Moore's Law with new transistor, interconnect and packaging innovation. To accelerate these innovations, Intel created oneAPI, a unified programming model that seamlessly works across domains and is now being used by developers worldwide. Please welcome Intel's Chief Architect and Senior Vice President of Accelerated Computing and Graphics, Raja Koduri.

Hello, everyone. It's great to see you all. Thank you for joining us for our third Architecture Day. Me and my fellow architects and engineers are so happy to be with you virtually. However, I'm so, so, looking forward to doing this with you all live in the same room and immerse in deep, geeky conversations over some quality ice cream and hot wings. This is an awesome time to be a computer architect. Technology is changing at a torrid pace. Looking back at just the last year, technology was at the heart of how we all communicated, work, played and survived through the pandemic. Enormous computing power proved crucial. We witnessed the development of life-saving vaccines, advances in computer vision, cryptocurrencies, decentralized finance, augmented reality and space travel. And it's accelerated. We are seeing metahumans, GitHub Copilot, software creating software and this little thing called AI. Some of these save lives, others altered our lifestyles, some are game-changing and some controversial. No matter where you look, our lives are intertwined with digital technology. Every demanding workload we look into and every innovating customer we talk to have 1 metaperformance ask 1,000x. They ask, "Can you make our workloads 1,000x faster by 2025?" So that's just 4 years away. 1,000x is Moore's Law to the power of 5. And that's something impossible, right? How will we do that? To meet this 1,000x demand by 2025, we will need to achieve the minimum Moore's Law improvement, 4x or so in each of these technology areas, process, packaging, memory and interconnect and architecture. Architecture is the alchemy that brings them all together with software. And together, they give us the multiplicative factor. So all those 4x improvements could combine to give us the 1,000x we need for demanding workloads. This is just an illustration to show why it's an exciting time to be an architect. And speaking of architects, Pat Gelsinger recently rejoined us as CEO, and he is a renowned architect. Pat reminds us that what we do is important because the world is counting on engineers to solve the most difficult problems, to enrich people's lives, to make them happier, healthier, safer and to architect our silicon at the speed of software, which means a torrid pace. We have a rich selection of compute engines to choose from, several flavors of scale or vector matrix and spatial engines, to combine and make hybrid computing architectures, that deliver nonlinear gains on demanding workloads. When we leverage the best transistor for a given engine, connect them through advanced packaging, integrate high-bandwidth low-power caches, equip them with high-capacity memories and low latency interconnect, we have hybrid computing clusters in a package. Every product I look at in our road map looks like a collection of systems on packages, products ranging from watts to kilowatts. Today, my fellow architects will share our advances in accelerated hybrid computing with architectures that establish new foundations in products whose releases are imminent. You'll hear about one of the biggest shifts in x86 architecture in over a decade. We will begin by introducing 2 next-generation x86 core microarchitectures. First, we will present the Efficient-core, a highly scalable microarchitecture optimized for multicore performance per watt. Next, we will present the Performance-core optimized for single-traded performance and AI. Then we will walk you through the architectural magic that combines these 2 cores to deliver our first performance hybrid architecture, Alder Lake, which will delight billions of PC users. You will hear about the advances we are making in visual computing architectures with Xe HPG and our discrete graphics. Later, we will look at a new accelerated hybrid architecture designed for data center, Sapphire Rapids, which combines our Performance-cores with new accelerator cores. Next, we'll show you Mount Evans IPU, infrastructure processing unit. This is the beginning of hybrid infrastructure computing in a package. And we'll close it with the tour de force of all the latest silicon technologies, our moon shot, Ponte Vecchio. Now, let's get started. I'd like to welcome the Chief Architect for the Efficient x86 core, Stephen Robinson.

Hey, Raja.

Stephen, start us off with a bang.

Absolutely. Hey, everybody. I am excited to introduce to you our new microarchitecture, previously code-named Gracemont. When we started this journey, we wanted to deliver a scalable microarchitecture that could address computing needs across our entire spectrum of products, from low-power mobile applications to many core microservices. Our primary goal was to build the world's most Efficient x86 CPU core. We wanted to do that while still delivering more IPC than Intel's most prolific CPU microarchitecture to date, Skylake. We also set an aggressive silicon area target so that multicore workloads could be scaled out using as many cores as necessary. With these architectural anchors in place, we also wanted to deliver a wide frequency range. This allows us to save power by running at low voltage and create headroom to increase frequency and ramp up performance for more demanding workloads. Finally, we wanted to provide rich ISA features, such as advanced vector and AI instructions that accelerate modern workloads. I am pleased to say that we delivered on all of our goals. It's my honor to introduce Intel's newest Efficient x86 core microarchitecture. Thanks to a deep front end, a wide back-end and a design optimized to take advantage of Intel 7, this CPU core delivers a breakthrough in multicore performance. Let's now dive deeper into the details, starting with the front end. The first aspect in driving efficient IPC is to make sure we can process instructions as quickly as possible. This starts with accurate branch prediction. Without accurate branch prediction, much of the work ends up being unused, which is wasteful. We implemented a 5,000 entry branch target cache. We complemented it with a long, history-based branch prediction. This helps us quickly generate accurate instruction pointers. With accurate branch prediction, things like instruction cache misses can be discovered and remedied early before becoming critical to program execution. Workloads like web browsers, databases, packet processing, these all benefit from these capabilities. We also have a 64-kilobyte instruction cache that keeps the most useful instructions close without expending power in the memory subsystem. This microarchitecture features Intel's first on-demand instruction length decoder, which generates predecode information that's stored alongside the instruction cache. This gives us the best combination of characteristics where code that has never been seen before is decoded quickly yet the next time it's executed, we bypass the length of decoder and save energy. The new core also features Intel's revolutionary clustered out-of-order decoder that enables decoding up to 6 instructions per cycle, while maintaining the energy efficiency of a much narrower core. It also includes hardware-driven load balancing, which takes long chains of sequential instructions and automatically inserts toggle points to ensure parallelism. The second main aspect to achieving performance is ensuring you extract any parallelism inherent in the program. With 5-wide allocation, 8-wide retire, a 256 entry out-of-order window and 17 execution ports, this microarchitecture delivers more general integer IPC than Intel Skylake core, while consuming a fraction of the power. The execution ports are scaled to the unique requirements of each unit, which maximizes both performance and energy efficiency. Four general-purpose integer execution ports are complemented by dual integer multipliers and dividers. We can also resolve 2 branches per cycle. Now for vector operations, we have 3 SIMD ALUs. The SIMD integer multiplier supports Intel's virtual neural network instructions. 2 symmetric floating point pipelines allow executing 2 independent add or multiply operations. Thanks to advanced vector extensions, we can also execute 2 floating point multiply, add instructions per cycle. Advanced crypto units round out the vector stack, which provide AES and SHA acceleration. Now the final aspect to achieving efficient performance is a fast memory subsystem, 2 load pipelines, plus 2 store pipelines enable 32-byte read and 32-byte write bandwidth at the same time. The L2 cache, which is shared among 4 cores, can be 2 or 4 megabytes depending on product level requirements. This large L2 provides high performance and power efficiency for single-threaded workloads by keeping data close. It also provides enough bandwidth to service all 4 cores. The L2 can provide 64 bytes of re-bandwidth per cycle with 17 cycle latency. The memory subsystem has debuffering and each 4 core module can have up to 64 outstanding misses to the last level of cache and beyond. Advanced prefetchers exist at all cache levels to automatically detect a wide variety of streaming behavior. Now Intel Resource Director Technology ensures that software can control resources among the cores. A robust set of security features, along with having an ISA that can support a wide range of data types, is important for every new microarchitecture. We support features like Intel Control-flow Enforcement Technology and Intel Virtualization Technology Redirection Protection. We put additional focus on security validation and developed several novel techniques to harden against certain attack vectors to maintain tight security. We also implemented the AVX ISA along with new extensions to support integer AI operations. This allows software to run with great performance. In addition to choosing what to include, one of the most important aspects of designing new microarchitecture is deciding what not to include. We balance this trade-off by focusing on those features that were needed and keeping out the rest. This results in area efficiency, which in turn allows products to scale out the number of cores. This also helps reduce energy per instruction. Now minimizing power is the biggest design challenge for today's processors. Power is a combination of multiple factors at which voltage is the most important. This microarchitecture and our focused design effort allow us to run at low voltage to reduce power consumption, while at the same time, creating the power headroom to operate at higher frequencies. Okay. Now let's take a look at the results of this new design. First, looking at latency, if we compare our core to a single Skylake core for a single logical process, we deliver 40% more performance, the same power. Now we also delivered the same performance while consuming less than 40% of the power. To say it differently, a Skylake core would consume 2.5x more power to achieve the same performance. This is a tremendous achievement. However, we're even more excited about the throughput results. If we compare 4 of our new CPU cores against 2 Skylakes running 4 threads, we deliver 80% more performance while still consuming less power. Alternatively, we deliver the same throughput while consuming 80% less power. Again, this means that Skylake would need to consume 5x the power for the same performance. As you can imagine, these are very exciting results for us. What makes all of this truly incredible is when you consider that we can deliver 4 of our new cores in a similar footprint as a single Skylake core. In conclusion, we are extremely proud of our new highly scalable microarchitecture. Thanks to our deep front-end innovations, our wide back-end and design optimizations using Intel 7, we created a microarchitecture that excels at throughput efficiency. We exceed Skylake core performance while consuming less power and a smaller footprint. I want to thank all of the talented engineers on the architecture and design teams. And I also want to acknowledge the support we got from everyone within the company. Thank you for your time. Back to you, Raja.

As we just heard, the new Efficient x86 core provides a highly scalable architecture that will address compute requirement across the entire spectrum of our customer needs, from low-power mobile applications to many core microservices. Next, we're going to take a deep dive into our new performance x86 core architecture. While maintaining efficiency, this core is designed for raw speed, pushing the limits of low latency and single-threaded application performance. So without further ado, I'd like to hand things over to the Chief Architect of the Performance-core, Adi Yoaz.

Hey, Raja.

Take it away.

Thank you, Raja. It's an honor to be here. Hello, everyone. I'm really excited for this opportunity to make the first public introduction of the new Performance-core architecture, which was previously code-named Golden Cove. When we started this journey, we did so with an ambitious goal, not only to deliver the highest-performing CPU core Intel has ever built, but also to deliver a step function in CPU architecture performance that will drive the next decade of compute. To do that, we focused on both general purpose compute as well as accelerated compute for emerging workloads. As we looked at the trends in current and future workload patterns, we saw that workloads are growing in their code footprint and in their demand for compute resources. We also thought that data sets are massively growing and data bandwidth requirements are becoming increasingly critical. We also see exciting trends in demands for greater AI compute. So we wanted to not only continue on the path of improving the performance of our existing AVX vector acceleration, hardware and ISA, but also to expand on this with a new technology to deliver yet another step function in AI performance acceleration. Last, but certainly not least, we wanted to deliver a scalable architecture with a wide dynamic range to power the broader set of devices from low TDP laptops, to desktops, to data centers. Thus, with our new Performance-core architecture, we wanted to enable co-configuration options to cover the various needs across all these segments. I'm thrilled to announce that we delivered on all of our objectives, and it is my privilege to introduce Intel's new performance x86 core architecture, designed for speed, pushing the limits of low latency and single-threaded application performance. To keep driving general purpose performance, we have architected the machine to become wider, deeper and smarter. It has a deeper out of order scheduler and buffers, more physical registers, wider allocation window and more execution ports, making the machine wider and deeper can expose higher degrees of parallelism and provide higher performance only if it is fed with instructions from the correct path and with data coming in on time for execution. To make this do wider and deeper machine effective, we also made it smarter with features that improve branch prediction and the instruction supply, collapse dependency chains, and bring data closer to the time when it is needed. On top of the baseline features that speed up most common workloads, we added dedicated features for workloads with particular properties. For example, in order to better support applications with large code footprints, we are now tracking many more branch prediction targets. For emerging workloads with large, irregular data sets, the machine can simultaneously service 4 page table works. And for the evolving trends in machine learning, we added dedicated hardware and new ISA to perform matrix multiplication operations for an order of magnitude performance increase in AI acceleration. This is architected for software ease of use, leveraging the X86 programming model. Additional performance is achieved through core autonomous, fine grain power management technology. The Performance-core integrates a new microcontroller that can capture and account for events in granularity of microseconds instead of milliseconds and tighten the power budget utilization based on actual application behavior. The result is higher average frequency for any given application. This is our largest architectural shift in over a decade. And with that as an introduction, let me now dive deeper into the details of our Performance-core architecture, starting with the machine's front-end. The first step in building a balanced, wider core is to widen and enhance the core's front-end. Micro operation supply was improved both from the decoder side and from the micro op cache path. The length decode is now doubled, running at 32 bytes per cycle, and 2 decoders were added to enable 6 decoded micro ops coming per cycle from the decoders. When delivering micro operations out of the micro op cache, we can now get 8 micro ops per cycle, and the micro op cache itself has increased to hold 4k instead of 2.25K micro operations. This allows us to better feed the out-of-order repair engine, deliver higher micro op bandwidth and do so in the lower-latency, short-term pipeline. To better support software with large code footprint, we doubled the number of 4K pages and large pages stored in the ITLBs. We have a smarter code prefetch mechanism, hiding much of the instruction cache mislatency, and improved branch prediction accuracy to reduce jump mispredicts. The branch target buffer is more than 2x larger than the 1 on the previous generation, which greatly improves the performance of workloads that have a lot of code. It uses a machine learning algorithm to dynamically grow and shrink its size. It shuts off excess capacity when it's not needed to save power, and it turns on extra capacity when it's needed to improve performance. With a wider and smarter front-end, we now turn to the out-of-order part of the machine. The out-of-order engine is where the magic happens. And this is what separates CPU architecture from all other architectures. We are widening the machine by going from 5 to 6 wide rename allocation and from 10 to 12 execution ports. The machine is also becoming significantly deeper with a 512-entry reorder buffer, more physical registers and a deeper, distributed preoperation type scheduling window, all tuned for performance and power efficiency. To further improve both performance and power efficiency, P-core smart features enable collapsing dependency chains by executing some simple instructions at the allocation stage, thereby saving resources down the pipe. This allows other operations reside on the critical path, run faster while better utilizing execution bandwidth and save power. With a wider, deeper and smarter out-of-order engine, we also wanted to enhance our execution unit significantly. Let me start with the integer part. We added the fifth general purpose execution port with the fifth integer ALU and the fifth single-cycle LEA. All 5 LEA execution units can also be used for generic arithmetic calculations like additions and subtractions as well as for fast multiplications by some fixed numbers. The LEA added on port 10 can also do scaled operations in a single cycle, similar to the LEA we have on ports 1 and 5. It was important for us to increase compute resources here as ALU operations are so common that much of the software will take advantage of it. Similarly, on the floating point vector side, for the many cases where vector code is prevalent, we have added new fast adders on ports 1 and 5. These are 3-cycle fast adders with 2-cycle bypass between back-to-back floating point add operations. In our previous generation cores, floating point add operations are executed on the FMA units with a 4-cycle latency when executed on port 0 and 1 and the 6-cycle latency when executed on port 5. The new Performance-core supports the execution of new data types with [ 2 ISM associated ] hardware. FP16 data type is now added in AVX512 mode, where it comes with a complex numbers support and is highly effective in speeding up networking applications. I'm super excited about one more big thing regarding our new matrix execution architecture, but before I get to that, let me finalize our general purpose compute advancements. So turning now to the memory subsystem. The L1 data cache was opened up to supply more data to the new wide execution machine planned for 50% higher throughput for the most common scalar and vector loads, while still supporting 1K bits per clock in the case of efficient 512-bit-wide vector loads. A very deep out-of-order machine with deeper load buffer and store buffer has the potential to expose much more memory parallelism. But unlocking that potential requires a whole lot of smarts. The new Performance-core tackled this problem from multiple angles. The memory subsystem has learned how to identify independent loads and stores more effectively than ever before. When conflicts are recognized, functionality has been added to react immediately and recover with minimal disruption. We have greatly increased the opportunities where store data can be directly steered to a load and latency for such cases has been optimized. The new Performance-core was architected, recognizing that modern workloads demand more data from all cache levels. To better address midrange working sets, the L1 data-TLB has been increased by 50%, and the L1 data cache itself can fetch 25% more misses in parallel. The L1 data prefetcher has been enhanced to confidently lock on to stride patterns even in the face of an aggressively out-of-order execution architecture and has extended its reach 8x compared to the previous generation. The machine can now simultaneously service 4 page table walks. This is a 2x capability improvement beneficial for emerging workloads with large irregular data sets. A hungry compute engine needs feeding, and the L2 cache subsystem is engineered to satisfy that need. The L2 cache itself has been customized for 2 different market segments. The client Performance-core gets a latency optimized, 1.25 meg L2 cache, while data center Performance-core gets a generous 2 meg private cache, allowing large code and data workloads to scale to larger core accounts. For big data workloads, feeding the core means pulling data into the core from across the system. To that end, the L2 cache subsystem has more than doubled the number of demand or prefetch operations that can be serviced in parallel. A completely new L2 prefetch engine was developed to leverage a deeper understanding of program behavior. The prefetch engine observes the running program in order to estimate the likelihood of future memory access patterns. It can identify multiple potential future sequences and can prefetch down multiple potential [ paths. Each path panned had depth ] individually tailored for its estimated likelihood. This chart shows the performance improvement of our current 11th Gen Core architecture to the new Performance-core at ISO frequency. As we see, the effect of the microarchitectural enhancements we've discussed thus far on general purpose performance provides an average improvement of 19% across a wide range of workloads. This level of improvement is even larger than what we delivered with the [ Sanico core ] over the Skylake core. And it is just to give you a taste for what the performance improvement looks like for existing workloads. Of course, for new workloads that take advantage of our new ISA and architectural advancements, the numbers go up significantly. To dramatically increase the IPC of AI applications, we developed a new technology called AMX. AMX is our next-generation, built-in, AI acceleration advancement for machine learning, inference and training, targeted for data center. Today, we are already in industry leaders in CPU AI acceleration in the data center market. With int8 used for inference, our VNNI technology delivers 256 int8 operations per cycle per core, and that's already over 2x of x86 CPU competition. But we were not satisfied with that. So with AMX, we will expand that by 8x, delivering 2,048 int8 operations per cycle per core. There are 2 components in the AMX architecture today. The first component is tiles, which is a new state component, consisting of 8 2-dimensional registers, each 1 kilobyte in size. The programmer part of this architecture is straightforward, configure, load, store, clear. The more interesting operations or to be carried out by coprocessors that operate on tiles. Tile state is always managed, which required a new extension in the XSAVE architecture. The second component is TMUL, which stands for Tiled Matrix Multiplication, and is the first coprocessor attached to the tiles. It is a systolic array, supporting all flavors of int8 with 32-bit accumulation and bfloat16 with single precision accumulation. I also wanted to give you a broader view of the underlying architecture behind AMX. The architecture is highly flexible and can be expanded to implement further coprocessors down the line to address different types of computation needs. In the current implementation, we have the TMUL engine as a tightly coupled coprocessor within the P-core host. The host is doing all loop and address management as well as the SIMD processing of the data. The TMUL engine performs matrix multiplication in parallel to the host. The resulting power performance is much better than simply running these algorithms on the SIMD hardware. If the matrix engine is much more efficient, and the remaining work on the host is generally light. So all of the core power budget is given to the matrix engine and the cache subsystem to feed it, which is exactly what you want. The typical flow of a layer in a deep learning topology is for the data to come in straight to the tiles. Meanwhile, the host is running ahead dispatching tiles loads, while TMUL is operating on the ready data. At the end of the multiplication, the tiles are stored to the nearest cache level to the host, thanks to the tight coupling with the core, then SIMD code is used to postprocess the output and store it to the location where the next layer will get it from. There are software techniques to fuse and interleave these operations. So that both the host and the AMX unit are busy simultaneously, which provides maximum performance. As I said on our current implementation, AMX peak compute throughput is 2K int8 operations per cycle per core, which is 8x higher compared with VNNI running on 2 wide FMAs at less than 3x the execution power. With AMX, we can also perform 1K bfloat16 operations per cycle to get higher accuracy, multiply, accumulate computations for training workloads. These are the order of magnitude-type increases developers and users are looking for. And that is what we have delivered with our new AMX technology. In conclusion, we are very excited about this new Performance-core architecture. This P-core is not only the highest-performing CPU core Intel has ever built, but also delivers a step function in CPU architecture performance that will drive the next decade of compute. It is a wider, deeper and smarter machine that delivers substantial improvement for general purpose compute. It is tailored for the increased needs of large data sets and large core footprint applications. And it also delivers an order of magnitude in accelerated performance for AI workloads. The new architecture has enhanced power management capabilities that improve frequencies and optimize power budget utilization. And it also supports core configuration options for scalability across different market segments. Finally, I really want to thank the team of talented architects and engineers at Intel that made these advancements possible. Thank you all for your time. Back to you, Raja.

Thank you, Adi. With our new Performance- and Efficient-cores, you have seen the details of 1 of the biggest advancements in x86 architecture in over a decade. So let's put that in context. We have shown you this road map of coves and monts in the past. You may have noticed, we have changed our nomenclature since. Our monts were designed for the best area-efficient multithreaded performance. Our coves were designed for maximum, single-threaded performance. Now while Efficient-core truly excels in throughput efficiency, it's also getting a boost in single-threaded performance. And the Performance-core is not only pushing the limits of low latency and single-threaded performance, it's also getting a boost in multithreaded performance with additional AI acceleration. But where we want to be is here, where we can combine the best of both, best of both in one system to get the raw performance of the P-core with the scalability of the E-core. We need a very high-performance hybrid. Talking about hybrid. Everyone understands the idea of the hybrid car as using hybrid technology to get the most miles out of a tank of gas. And that's a good analogy for the conventional notion of hybrid computing, getting the most hours out of a battery. But there is another type of automotive hybrid. The fastest racing cars in the world, like in Formula 1, use hybrid technology to achieve maximum performance. In addition to the conventional turbocharged engines that give them top speed and enough range to make it to the finish line on a tank of fuel, they add electric power to blast them out of the corners with acceleration that cannot be achieved with conventional engines. We need a high-performance hybrid. The biggest challenge, the magic is to bring these 2 cores together, working efficiently with existing software. This is a huge undertaking, and we have been hard at work on this problem for years. We now have the solution. To share more, I would like to invite our Client Architect, Rajshree.

Thanks, Raja, and hello, everyone. I'm really excited to share with you unique solution we have developed to ensure 2 new cores you just heard about, Efficient-core and Performance-core work seamlessly together, so we can maximize system performance and efficiency. As we all know, performance expectation can vary drastically for different computing tasks. So one of the most important consideration we had while designing our next-generation client CPU SoC was ensuring optimal task scheduling across 2 different core types. The challenges given to the team were, first, how do we go beyond traditional hybrid as we know it? And second, how do we get both core types to work together intelligently to maximize performance? As Raja mentioned, we could have taken conventional approach of simply assigning threads to cores based on static rules. But that leaves a lot of performance on the table and creates overhead with software development. Our solution needed to be dynamic and autonomous to software stack that is running on top. So we decided to help OS make more intelligent decisions. It is needed to handle a wide range of common client activities such as gaming, gaming with streaming, content creation, productivity, while dynamically adapting to operating conditions such as temperature and power budget. We also wanted to eliminate the need for software developers to having to rewrite their existing code and remove overhead of handling scheduling task in software. Only a hardware solution could meet all these requirements, so we developed Intel Thread Director technology. Thread Director technology is one of the most significant and exciting innovations in our client road map. Thread Director technology allows us to provide smarter assistance to the OS by monitoring instruction mix, current state of each core and relevant microarchitecture telemetry at a granular level. This also allows OS to utilize information, it didn't previously have any visibility into at time of making it, scheduling decisions. By implementing Intel Thread Director in hardware, we are able to keep advantage of our performance monitoring unit, which provides the best hardware telemetry in the industry. Access to this information allows Intel Thread Director to assist us in optimal runtime scheduling. Traditionally, OS would have made decisions based on limited information that was available, such as foreground versus background. Thread Director adds a new dimension to the hardware telemetry. So threads with higher performance requirements are assigned to most Performance-cores. Let's walk through a scheduling example on a real scenario. Let's say, a user starts a performance-critical as such as a game or a content creation software. Those threads first will be assigned to our Performance-cores. Now if a background such as e-mail synch or network drive backup starts, those lower priority, less demanding tasks will go to our Efficient-cores. Next, let's assume a case where all the Performance-cores are busy, but a threat needing even higher performance becomes ready, such as AI thread using CPU AI instruction. In this situation, Thread Director provides what we refer to as a hint to the OS indicating there's a higher performance thread needing attention. Thread Director also identifies a candidate thread that could be moved from Performance-cores to Efficient-cores based on relative performance ordering, making room for that AI thread. This is where the dynamic nature of our innovation shines. Nothing is static based on any software. Everything is dynamic based on the current context of whatever is running on the system, all augmented by hardware telemetry. And last, if a thread running on Performance-core in terms of spinning stage, waiting for work to show, then Thread Director reports this situation back to OS. This thread will be moved all to an E-core, thereby making room for a more performance thread to be allocated to our Performance-cores. This is our animation explanation of the technology. Let's see it in action on Alder Lake, running Windows 11, incorporating Thread Director feedback in real time. [Presentation]

In typical cases, we see a combination of scalar and vector instruction, mix of important and background task. We are going to see how Thread Director helps OS with placement of these threads. In the first example, we have a representation of a typical media content creation usage we see with real world software. The green threads that you are seeing here are mostly scalar instruction. The dark blue threads that you see are vector instructions, and the light blue are background tasks. The vector instructions, for the most part, get prioritized on Performance-cores as they require more performance, while some of the green threads and the light blue thread go to Efficient-cores. Let's look at one more example, this time with office productivity and background application. Office productivity, video conferencing, CPU AI instruction usage in these cases is increasing consistently. Placement of these AI threads is going to be key to maximize performance. As we have seen with previous example, we have green threads, which are mostly scalar. Then we have the orange AI threads added to the mix where you can see Thread Director prioritizes them to Performance-cores. As seen before, the light blue tasks are running on Efficient-cores. All these threads here in this mix go through various phases within their own execution. You might have noticed there are phases once in a while where the dark blue vector threads or the orange AI thread go to E-cores. These are the phases where they have some scalar instructions in them. This is where the dynamic nature of this technology, prioritizing right thread to right core based on current execution context comes in. Lastly, I do want to show something else. I want to show fully multithreaded synthetic workload running same instruction mix. Here, all threads go use all available core. To enable this level of fine grain coordination for real performance, Intel jointly worked with Microsoft to incorporate this revolutionary capability into upcoming Windows 11 release. Speaking of which, I would like to invite Mehmet Iyigun from Microsoft to share more details.

Hello. Throughout the Windows 11 development cycle, my team has been working with our colleagues at Intel to enlighten and optimize our upcoming OS to take full advantage of the performance hybrid architecture and Thread Director in particular. Much of this work centers around the OS thread scheduler, the current component that decides which threads to run and where to run them. These decisions have a huge impact on user per seat performance and power consumption, especially on devices built on hybrid processor architectures. To make its decisions, the scheduler considers attributes such as thread priority, the owning application and whether the application is foreground or background. For example, threads belonging to foreground applications should be scheduled to high Performance-cores. However, up until now, the scheduler had no visibility into the workload running on a thread, whether it's copying memory, spinning in a loop or performing complex calculations. As such, when demand for high Performance-cores exceeded supply, it made suboptimal decisions because it couldn't identify the workloads that would benefit most from the Performance-cores. Thread Director helps close this gap. With Thread Director feedback, the Windows 11 thread scheduler is much smarter about dynamically picking the most appropriate core based on the workload to achieve the best power and performance. Even when all P-cores are busy, it can preempt a thread running on a P-core to swap it with a thread running on an E-core if the latter can benefit more from the P-core. The schedule, of course, does this without violating any of its priority-based fairness guarantees. Beyond threat scheduling, Windows 11 also uses Thread Director hints when deciding which cores to park and unpark for power savings. For example, if all outstanding work targets E-cores, the system can refrain from unparking at P-core. In addition to automatic workload classification provided by Thread Director, Windows 11 also extends the power throttling API, which allows developers to explicitly specify quality of service attributes for their threads. The new EcoQoS classification informs the scheduler that the thread prefers power efficiency over performance. Such threads get scheduled on E-cores, reducing power consumption and leaving the P-cores available for performance-critical threads. The Edge browser as well as various Windows 11 components now take advantage of the EcoQoS API to boost energy efficiency. This was a short summary of the improvements we put into Windows 11 in collaboration with multiple teams at Microsoft and Intel. There are many more optimizations I did not talk about and many more in planning stages. What is clear is that we're at an inflection point in heterogeneous computing, and we're going to continue seeing tighter integration and information exchange between hardware and the OS to unleash further performance and better life improvements. I'm looking forward to continuing our collaboration with Intel. Thank you.

We are very excited about the performance benefits of this technology and the potential it holds for future innovation. With that, I would like to hand it over to my colleague, Arik Gihon, to give you more details about Alder Lake SoC. Thank you.

Hi, everyone. I'm very excited to introduce Alder Lake today, Intel's new client architecture on Intel 7 process that scales from the highest performance enthusiast desktop to the thinnest, most responsive Evo laptops. Alder Lake is Intel's first performance hybrid core design, introducing 2 core types brought together seamlessly through Intel Thread Director technology. Alder Lake supports the latest state-of-the-art industry standards in memory, I/O and connectivity for no compromise PC experience. Let's get to know Alder Lake. Alder Lake was built for performance. We started with desktop architecture and scaled all the way down to automobile. One of our most important goals when designing Alder Lake was to support all client segments through a single, highly scalable SoC architecture with 3 design points. First, a maximum performance, 2-chip, socketed desktop with leadership performance, power efficiency, memory and I/O. Second, a high-performance mobile BGA package that adds imaging, larger Xe graphics and Thunderbolt 4 connectivity. And finally, a thin, lower-power, high-density package with optimized I/O and power delivery. Supporting this huge range of power and performance is an incredible silicon design challenge. Designing Alder Lake was an amazing technical challenge for me, and I would like to share with you how we achieved it. Alder Lake architecture is built from a selection of world-class IPs for die-level configurability. We enabled multiple combination of Performance-cores and Efficient-cores, a large number of I/Os and accelerators, various levels of Xe graphics and 4 different memory types. Both P-cores and E-cores are built as interchangeable slices that include a portion of the last-level cache, allowing us to build multiple die topologies, spanning Alder Lake's huge design range. The accelerators and I/Os are connected through an [ hierarchical ] structure, configured to support the required bus width queue sizes, number of ports and memory access feature set. Alder Lake leveraged the Xe LP graphics from Tiger Lake ported to Intel 7. It supports 1080p gameplay and 12-bit end-to-end video pipeline. Finally, the memory subsystem is designed in tiles to cope efficiently with the large, acquired bandwidth range, memory encryption, integrity and multiple DDR technologies. Let's take a deeper look at each of the key technologies. Everything starts with the new performance hybrid architecture. We use up to 8 high, single-threaded Performance-cores and up to 8 Efficient-cores, both supporting high dynamic frequency range and per core power states. The E-cores are clustered with a shared L2 cache and deliver scalable multiple performance and efficient offload of background tasks. The last-level cache has a shared structure between the cores and graphics that provides higher effective cache size on a likely threaded load. For controlling the operation of this massive compute, we have developed an autonomous power management scheme. This controls the various cores to optimize performance per watt according to software and platform preferences. As we saw in the demo, all of this is orchestrated by the Thread Director for proper workload scheduling. We developed a sophisticated hardware runtime mechanism that identified the class of each workload. The class, together with the energy and Performance-core scoring mechanism, guides the OS to schedule threads on the right core for performance or efficiency per demand. Let me show you the memory capabilities. Alder Lake delivers a separate set DDR technologies with Intel's unique [ PHYs ], supporting DDR4 and DDR5 as well as LPDDR4 and LPDDR5 in a single chip, leading the industry to this major memory transition. Alder Lake supports high-frequency DDR speeds and can alter the speed based on runtime bandwidth requirements while tracking the workload behavior. This allowed high-speed, high-power or low-speed, low-power operations, based on real-time heuristics. If you think this is cool, we also upgraded our PCIe capabilities. Alder Lake is leading the transition to PCIe Gen5 with up to twice the bandwidth of Gen4. It supports up to 16 lanes and reaches 64 gigabyte per second, ready for the next generation of SSDs and discrete graphics. So let's see how all of this works together. The challenge of building such a highly scalable architecture is that we need to meet the incredible bandwidth demands of the compute and I/O agents without compromising of power. To solve this challenge, we have designed 3 independent fabrics, each with real-time, demand-based heuristics. While the workload is running, the power management units collects telemetry from the fabric sources, track the traffic and select the most efficient work point. The compute fabric can support up to 1,000 gigabytes per second, which is 100 gigabytes per second per core ultra-cluster. It connects the cores and graphics to the last-level cache to the memory. It has a high dynamic frequency range, and it's capable of dynamically selecting the data path for latency versus bandwidth optimization based on actual fabric loads. It also dynamically adjusts the last-level cache policy, inclusive or noninclusive based on utilization. The I/O fabric supports up to 64 gigawatt per second and connects to different types of I/Os as well as internal devices. It can change speed seamlessly without interfering with device's normal operation, selecting the fabric speed to match the required amount of data transfer. And last, the memory fabric can deliver up to 204 gigabytes of data. It dynamically scales its bus width and speed to support multiple operating points for high bandwidth, low latency or low power. This real-time scaling enables Alder Lake to take -- dynamically shift the power budget to where it matters the most. Finally, I'm working with the team on Alder Lake in the lab now, and I can't wait to have one at home. Thank you. And back to you, Raja.

Thanks, Arik. We look forward to seeing Alder Lake in customers' hands later this year. Let's change gears from hybrid computing to visual computing. I'm sure you all want to hear a little bit more about our discrete Xe GPU architectures. If you step back, and look at what we have been doing recently, you'll see that we have made tremendous progress on integrated GPU hardware and software in less than 3 years. We have effectively doubled performance year-over-year 2 years in a row now, first with Gen9 to Gen11 and then with Gen11 to Xe LP. This was an incredible start. And this effort removed friction for millions of users. We raised the performance bar for ultrathin mobile devices. But as we have already announced, we have bigger plants. Integrated graphics is constrained, but discrete, on the other hand, is unconstrained, well, relatively. This is a great time to be entering the high-performance PC graphics market. Why are we doing this? Why now? These are extremely exciting times, game engines and software teams are producing near real life in-game visuals in real time. And leading-edge hardware is enabling everything to come together to deliver incredible experiences that allow gamers to feel more immersed than ever before. Publishers, developers, gamers and creators are constantly pushing the boundaries of what is possible, always asking more from their hardware, and they are also looking for more innovation and choice. The PC ecosystem is built around innovation and choice. Many different OEMs, many different shapes, sizes and form factors and many different operating systems and a diversity of software. The vast choice of what to buy or the flexibility to build your own PC, to customize, upgrade and to modify. These are some of the reasons the PC market has been so popular and exciting since the beginning. These are the reasons the PC ecosystem is great. 1.5 billion people are PC gamers. Our focus today is to deliver a better experience for gamers and creators, to give them innovation and choice in hardware coupled with open and accessible software and tools, to create a great experience across form factor segments and users, to remove friction and deliver high-performance graphics experiences to everyone. We recently unveiled Arc, which is a brand for our visual computing products. The word "arc" is used to describe the narrative flow and the various plot inflections of a story. Every gamer, game and creator has a story. And every story has an arc. The Arc brand represents the next chapter of our story and our commitment to removing friction from gamers. Building great GPU hardware is necessary but nowhere sufficient. Great software plays a critical role for the user experience. To discuss the progress we are making on software and user experiences, please welcome the leader of our GPU software team, Lisa Pearce.

Thanks, Raja. With our first high-performance gaming GPU, it goes without saying the performance and quality are job one. First, at the heart of our focus is the design of the core driver itself that covers integrated and discrete graphics products in one unified code base. We've completed a rearchitecture of these core driver components, specifically our memory manager and compiler. As a result, this year, we've improved the throughput of CPU bound titles by up to 18%, and improved the game load times by up to 25%. This low time reduction was accomplished through enhancements to our stage-compilation technology, such as eliminating redundant shader compilation and improving task scheduling for our compiler threads. We also completed a major refactor to fully optimize our local memory utilization on our discrete graphics products. At the same time, we implemented over 30 large optimizations, affecting over 100 gaming workloads that rolled out in our existing installed base this year with our unified graphics driver. Now we are always about new APIs and engines since new games are always pushing up the visual quality bar. For the last 3 years, we've been co-engineering new features for DX 12 Ultimate with Microsoft. We're excited that at launch, we will support hardware-based ray tracing, mesh shading and sampler feedback. Together, these technologies deliver next-gen visuals in games like HITMAN 3, Chivalry 2 and many others. We've also been working closely with Epic. And I'm excited to tell you that Unreal Engine 5 runs on our discrete graphics GPUs today. We can't wait to see what game developers will do next in their next-generation engines. At launch, we'll also enable updates to our user controls to help gamers take advantage of these technologies, including support for AI-assisted virtual cameras, game highlights and, of course, capture for streaming that will make use of our high-performance and quality hardware encoders. And we also will integrate all of our overclocking and performance interfaces directly to the app. And finally, in the end, it is all about experiences. One thing that gets us really excited is enabling a range of experiences across product segments, from integrated graphics to high-performance discrete. And today, I'm excited to share a new feature that will do just that, but first, some background. Given the fixed amount of performance potential in the GPU, gamers are forced to make a choice between high-quality and acceptable performance. There are cases where you have content that already runs close to 60 fps at 4K and the frame rate could be further increased by upscaling. Or you can have a more recent content like ray tracing that needs a performance boost, even to achieve playable frame rates. Over the years, games have developed various technologies to reconstruct a high-res image from fewer pixels. These technologies use novel algorithms to reconstruct details from neighboring pixels and spacer time, but they're often accompanied by issues like blurring or ghosting. And these technologies can often fall short with high-quality rendering, like ray trace reflections and shadows, detailed geometry or high-res textures. Additionally, their computational overhead in doing these operations. Ultimately, we want to target this region of high performance and high quality. Our solution to this problem is Xe SS. Xe SS is an easy to integrate API, and it fits within today's game engine flow. It uses deep learning to synthesize images that are very close to the quality of native high-res rendering. It works by reconstructing subpixel details from neighboring pixels as well as motion-compensated previous frames. This reconstruction is performed by a neural network, trained to deliver high performance and great quality. Now let's see Xe SS in action. This is a demo prepared by Rens using Unreal Engine. We can see the demo rendering real-time in 4K. But in reality, the engine renders to a smaller 1080p render target, which is upscaled to 4K by Xe SS. Compared to rendering in native 4K, there's no visible quality loss. Upskilling from 1080p to 4K with Xe SS gives us same quality image as rendered in native 4K. In this scene to the right, you can see the actual content rendered by the engine. The left side shows how this 1080p image is upskilled by Xe SS to achieve the final high-quality result. Rendering to a smaller 1080p rendered target allows to significantly reduce the rendering time and achieve higher frame rates. The cost of upscaling operation remains relatively small compared to the overall render time. Thanks to the use of AI-assisted scaling, we can also achieve up to 2x performance boost. And now games that would only be playable in low-quality settings can run smoothly at 4K. It may be a challenge to see these details in the live stream, so we've added a high-resolution video in the demo area that can be viewed on demand. Our goal with Xe SS was to deliver neural network-based super sampling for a wide range of GPU hardware across the industry. The demo you just saw was running on our recently announced Arc Alchemist SoC, leveraging our new XMX hardware acceleration that we'll discuss further in a few minutes. In addition, we also came up with another innovation to enable Xe SS on a broad set of hardware, including our competition, with a smart quality performance trade-off. We accomplished this by using DP4a instruction, which is available on a wide range of shipping hardware, including integrated graphics. This brings the benefits of Xe SS neural super sampling approach to millions of gamers. I'm thrilled that everyone can experience Xe SS. We're excited to have several early game developers engaged on Xe SS. The SDK for the initial XMX version will be available for ISVs this month, and the DP4a version will be available later this year. At Intel, we believe in open-source standards. Xe SS APIs will mature as we gain broad support for games and hardware, and we will open up the tools and SDKs for everyone. To learn more about XMX and our Xe HPG GPU microarchitecture, let me bring in our GPU Chief Architect, David Blythe.

Thanks, Lisa. Hi, everyone. It's time for our new GPU microarchitecture to be introduced to the world. This microarchitecture, which we call Xe HPG for high-performance gaming, is the convergence of our Xe LP, HP and HPC microarchitectures. Xe HPG is engineered to deliver great scalability and compute efficiency with advanced graphics features. Today, I'll give you a brief introduction to the new compute graphics and scalability capabilities of Xe HPG. To deliver scalability beyond Xe LP in Xe MAX and build enthusiast-class hardware, we've had to rework the fundamental architecture of our GPU. Starting with the heart of the engine, we defined a new compute building block, which serves as a foundation for the Xe architecture. As part of this architecture change, we're also taking the opportunity to update some of the naming. So you won't hear us talking about execution units or EUs much anymore. The execution units are getting too large to reason about and the generational changes make it difficult to do comparisons. So allow me to introduce the Xe core. Xe core include efficient arithmetic units, caches and load store logic. The arithmetic units include engines for traditional floating point and integer vector operations, along with engines to accelerate convolution and matrix operations, commonly found in AI workloads. The architecture gives us a core ISA with the flexibility to adapt the Xe cores for specific workloads and market segments. I don't have time to tell you everything about the Xe cores we've built for our Xe HPG microarchitecture today, but I can share some details. For Xe HPG, Xe cores include 16 vector engines and 16 matrix engines, which we refer to as XMX or Xe Matrix eXtensions. And you've already seen XMX in action with the Xe SS demo presented by Lisa. With more and more workloads infused with AI, XMX is a key engine for delivering more efficient compute. The Xe HPG microarchitecture is designed to be gaming first and to build much larger GPUs compared to the maximum of 6 Xe cores in Xe LP. We scaled the hardware required for real-time rendering in a larger building block we call our render slice. The render slice contains 4 Xe cores and the rendering fix function for real-time 3D graphics. The rendering fix function includes geometry, rasterization, samplers and pixel back-ends, designed for DirectX 12 Ultimate with support for variable rate shading through to mesh shading and sampler feedback. Each slice also includes 4 new ray tracing units, architected to accelerate ray traversal, bounding box intersections and triangle intersections. They provide full support for DXR or DirectX Raytracing as well as Vulkan Ray Tracing.

Thanks, David. With Xe cores and their advanced feature set, we now have next-generation real-time graphics. But we also wanted to scale this to enthusiast-class performance. Can you walk us through how we achieve that?

Of course, Raja, to scale our performance to enthusiast-class GPUs, we work on 2 fronts. First, we replicate these slices and then we connect them to a shared L2 cache through a high-bandwidth memory fabric. We have the flexibility to scale different configurations up to 8 slices. To hit our performance goals, not only did we create an architecture for building larger GPUs and add additional features, but we also challenged ourselves to increase the power efficiency and the operating frequency of the design. Working across architecture and engineering, we performed detailed analysis for power-reduction opportunities, which resulted in new methodologies and optimizations at every level of the design from the Xe core on up. The changes were spread across microarchitecture, logic design and physical design and often need complementary changes. It was truly a team effort, and I'm delighted to say that compared to the XE LP IP in our Iris Xe MAX product, we increased the relative operating frequency and the performance per watt each by roughly 1.5x. I should also point out that the team effort included close cooperation with process technology, and that, too, contributed to the great results. I'll hand things back to Raja, and he can elaborate on that a little bit more.

Thanks, David. Last year, I told you that Xe HPG GPUs would be built with an external foundry partner. Today, I'm happy to unveil that our partner is TSMC and Alchemist GPUs are built on the N6 process. This is the wafer of Alchemist. This is a great example of our IDM 2.0 partnerships. We have the flexibility to make the right process choice for each architecture. The progress I witnessed in our labs week by week with Alchemist GPUs and its software is very encouraging. Alchemist GPUs are now sampling to ISVs and partners. I can't wait to get the first generation of our products in your hands by Q1 of 2022. While our core silicon and software teams are working very hard to get this to you, our design and architecture teams are busy creating the next few generations of our gaming GPUs. Here, I have the code names, Battlemage with Xe2, Celestial with Xe3 and Druid after. Can't wait to share more at a future event. Hopefully, live. [Break]

Welcome back. In the first half of today's event, we shared details about Intel's new x86 compute cores. We also saw Intel's Alder Lake, which reinvents multicore architecture. In graphics, we showcased our new Xe SS technology and upcoming Alchemist GPU. Now let's shift gears to the data center, where we have even more exciting announcements. You'll hear about Mount Evans, our new infrastructure processing unit; and then Ponte Vecchio, our GPU for exascale. Let's start with Sapphire Rapids. The technology building blocks for this architecture have been years in the making. This includes a performance x86 core built for the data center, new accelerator cores, new memory architecture, new fabric architecture, new I/O architecture and a host of new software and security features. This is a big deal for Intel and a big deal for the entire data center ecosystem. To tell you more, let's bring on Sailesh, our Chief Architect for Data Center.

Thanks, Raja. Hello, everybody. It's great to be here today. I'm excited to introduce Sapphire Rapids because I believe Sapphire Rapids will establish a new standard in data center architecture. Sapphire Rapids is our next-generation Xeon scalable processor. It delivers great out-of-the-box performance with enhanced capabilities for the breadth of workloads and deployment models in the data center. Sapphire Rapids delivers a step function in performance across a broad set of scaler and parallel workloads. More importantly, it is fundamentally architected for breakthrough performance in elastic computing models like containerized micro-services and for a rapidly expanding use of AI in all forms of data-centric compute. Sapphire Rapids also advances the state-of-the-art in-memory and I/O technologies. Our overall architecture philosophy for Xeon is to deliver the best infrastructure in the data center. Xeon spans a wide range from monolithic server node deployments to data center scale elastic solutions. It delivers consistent performance across compute, storage and network usages. Xeon architecture is optimized to deliver great node-level performance as well as data center-level performance. Sapphire Rapids delivers big improvements at both levels. The new performance core in Sapphire Rapids brings significant scalar performance improvements. In addition, the multiple integrated accelerator engines and increased core counts provide a massive increase in data parallel performance. Furthermore, these performance cores are paired with the right levels of cache and industry-leading system capabilities of DDR5 and PCIe Gen 5 to provide optimal balance across compute, memory and I/O. Finally, all of these are integrated through a modular SoC architecture that provides consistent and efficient performance scaling across the socket, the node and the data center. At data center scale, it is critical to deliver great performance and utilization under multi-tenant usages, low-jitter performance to meet the tight SLA or service-level agreements as well as elasticity across the entire infrastructure. In contrast, the industry standard benchmarks focus on node-level compute throughput and do not reflect the reality of data center scale usages. We have drawn deep insights from multiple generations of Xeon products deployed at cloud scale to inform Sapphire Rapids architecture. As a result, we delivered big advances in each of these areas with Sapphire Rapids. For example, it offers several virtualization and telemetry capabilities to improve multi-tenant usages. We expand the QoS capabilities and architecture enhancements to reduce jitter for performance consistency under high utilization. In addition, we are introducing several micro-architecture and architecture capabilities to improve performance across a broad set of workloads to deliver better data center elasticity. Data center deployment models exhibit significant overheads. Sapphire Rapids fundamentally changes the paradigm of handling these overheads through acceleration engines. These accelerators not only speed up the overhead processing multifold but also significantly offload the cores, enabling them to deliver more application workload performance. As I said, this will be the new standard of data center architecture. Ladies and gentlemen, this is Sapphire Rapids. I would like to call on Chief Engineer, Nevine Nassif, to introduce the breakthrough SoC architecture that is Sapphire Rapids.

Thank you, Sailesh. At the heart of Sapphire Rapids is a new modular tiled architecture that allows us to scale the balanced Xeon architecture beyond the limits of a physical reticle. Sapphire Rapids is the first Xeon product built using EMIB, our latest 55-micron bump pitch silicon bridge technology. This innovative new technology enables independent tiles to be integrated in the package to realize a single logical processor. The resulting performance, power and density are comparable to an equivalent monolithic die. We're now able to increase core counts, cache, memory and I/O, free from the physical constraints that would otherwise have been imposed on the architecture and would have led to difficult compromises. This base SoC architecture is critical for providing balanced scaling and consistent performance across all workloads. This is key for data center scale elasticity and achieving optimal data center utilization. With this architecture, we're now able to provide software with a single balanced, unified memory access with every thread having full access to all resources on all tiles, including cache, memory and I/O. The result is consistent low latency and high cross-sectional bandwidth across the entire SoC. This is one of the critical ways we achieve low jitter in Sapphire Rapids. While Sapphire Rapids delivers out-of-the-box scalability for existing software and ecosystems, users can enable clustering at sub-NUMA and sub-UMA levels for additional performance and latency improvements. Sapphire Rapids sets a new standard for data center architecture with the seamless integration of cores and acceleration engines, providing a heterogeneous compute infrastructure. It delivers the highest levels of compute performance through a combination of a high-performance core, increased core counts, increased AI performance and the industry's broadest range of data center relevant accelerators. And Sapphire Rapids delivers leadership I/O capabilities through CXL 1.1, PCIe Gen 5 and UPI 2.0 technologies. All of these are provisioned with Intel's highest bandwidth and low-latency memory solutions through industry-leading DDR5, Optane and HBM memory technologies. Now back to Sailesh.

Thanks, Nevine. Now let's start with the details of the 3 major pillars that Nevine outlined, starting with the data center performance core. As mentioned earlier, optimizing exclusively for standard benchmarks would have been the easy path, but that does not reflect the full picture of real data center usages. We use the insights from generations of Xeon large-scale deployments to inform our micro-architecture choices for the performance core. Just to provide a flavor of this, data center workloads exhibit large code footprints and are fundamentally bottlenecked by the front-end performance of the core. We fundamentally redesigned the front end to address these bottlenecks in the performance core. Consistent performance under multi-tenant usages is critical. The core delivers several improvements like fast VM migration, enhanced cache and new TLB QoS capabilities for multi-tenant usages. We introduce autonomous and fine-grain power management to improve core performance without jitter. In addition, we added several new architecture capabilities in the core, including instructions and capabilities relevant for the data center. I want to provide a few examples of new ISA capabilities here. As Adi mentioned, we integrated AMX capabilities to accelerate tensor operations for AI workloads. We are also introducing Accelerator interfacing Architecture instruction set, AiA, which supports efficient dispatch, synchronization and signaling to the accelerators and devices from user mode as opposed to high overhead kernel mode. To address the growing demands for signal processing, we introduced half precision floating point through AVX. Another example is the CLDEMOTE instruction. It helps with optimal movement of data across cache hierarchy to improve shared data usage models. Another major area of focus for Sapphire Rapids compute capability was to improve performance significantly for common functions and overheads with at-scale data center deployments. I would like to invite Arijit, the lead architect on Sapphire Rapids, to tell us more.