Micron Technology, Inc. (MU) Earnings Call Transcript & Summary

Good afternoon. My name is Dilem, and I'll be your conference facilitator today. At this time, I would like to welcome everyone to a presentation and Q&A session with Scott DeBoer, Micron's EVP of Technology and Products. [Operator Instructions] It is now my pleasure to turn the floor over to your host, Farhan Ahmad, Vice President of Investor Relations. You may begin.

Hello. I am Farhan Ahmad, Vice President of Investor Relations at Micron. Thanks for joining us for today's presentation and Q&A session. On the call with me today is Scott DeBoer, EVP of Technology and Products at Micron; and Dave Zinsner, our CFO. We request that you keep questions focused on topics related to today's presentation. As a reminder, the matters we will be discussing today include forward-looking statements. These forward-looking statements are subject to risks and uncertainties that may cause actual results to differ materially from the statements made today. We refer you to the documents we filed with the SEC, specifically our most recent Form 10-K for our discussion of risks that may affect our future results. Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements. We are under no duty to update any of the forward-looking statements after today's date to conform these statements to actual results. I'll now hand it off to Scott.

Thanks, Farhan. Good afternoon. I'm Scott DeBoer, Executive Vice President of Technology and Products at Micron Technology. Over the last few years, Micron is focused on closing the gap with competition in both DRAM and NAND technology through faster node transitions. In parallel, we put significant focus on increasing the mix of high-value differentiated solutions. We have aggressively focused on execution and driven quality leadership. As we look ahead to the next phase of our journey, we envision the new Micron as an industry technology and product leader. Now that we've caught up on technology, our target is to introduce leading technology nodes as typical industry cadence, while maintaining our improved competitive position. In the last few years, we've targeted our supply growth to be roughly aligned with industry demand growth. We believe this strategy helps reduce overall industry cyclicality and supports healthier market conditions. We're committed to maintaining this strategy. On the product portfolio side, over the last few years, Micron has transformed our product portfolio by increasing our mix of high-value solutions. 80% of our NAND bits are now comprised of high-value solutions. Looking ahead, there are many more opportunities for differentiated products as the world moves towards heterogeneous computing. Today, I'll provide an overview of Micron's technology and product strategy as well as update you on the future direction of our key technologies with a focus on NAND and DRAM. Starting up with our strategy. The new Micron is strong and getting stronger, with greater R&D efficiency, a broad technology portfolio and the industry's best talent. About a year ago, we integrated our technology and product organizations under my leadership to drive greater R&D efficiency and customer value. This tighter vertical integration has made us more agile on covering opportunities to incorporate customer product requirements directly into our R&D technology and design road maps at the die level. The result is faster time to market, differentiated performance, best-in-class quality and cost competitiveness for our customers. This integration of technology and products, and the result is a great example of how the new Micron is continually adapting to drive innovation and improve execution. Micron has the industry's broadest portfolio of technologies, delivering economies of scope via R&D efficiencies and revenue synergies such as the ability to bring our customers' differentiated solutions across the entire memory and storage hierarchy. We are the only company in the world with DRAM, NAND and 3D XPoint products and the only manufacturer of 3D XPoint. We are pushing the boundary on performance with the fastest GDDR6X, and I'm proud to announce that we have begun revenue shipments of our first HBM2E products. We are also expanding our reach into the high-capacity cold storage market with our industry-leading QLC products. In the space between DRAM and NAND, our 3D XPoint technology provides a cost and performance value proposition that will grow as new computing paradigms evolve. Micron is uniquely positioned to attract the industry's best talent globally with R&D teams in the U.S., Italy, Germany, India and China, and technology development co-located with manufacturing in Taiwan, Japan and Singapore. We are confident that our global talent is a significant competitive advantage fueling our innovation. Over 50% of the new hires in R&D have Masters or PhD degrees. The strength of our team is also evident in our growing patent portfolio of over 44,000 granted patents. Micron has been recognized as a Top 25 company in terms of U.S. patents and has been recognized as a Best Employer for Diversity and a Great Place to Work. In the last year, approximately 25% of our R&D new hires have been women. In just over a year, the number of women inventors and patent holders at Micron grew by 80% year-over-year. We're extremely proud of these women supported by WIN. WIN is our program for women innovators at Micron. We are committed to furthering diversity, equality and inclusion at all levels across the company. Now turning to our core technology, and starting out with DRAM. We're really excited about our progress on the 1-alpha DRAM node. This node will offer tremendous improvement on bit density, performance and costs and significantly improve our competitive position in the industry. We expect this node will be in volume production in the first half of calendar '21. As 1-alpha ramps, it will provide Micron with a very good cost structure, while also delivering substantial performance improvements. It will enable the industry's lowest power mobile DRAM with a 15% improvement over our prior generation and will include a road map for the highest speed DRAM available across the comprehensive portfolio. Our 1-alpha node has a very impressive 40% increase in density versus 1z nanometer. This includes a 10% increase in density, specifically from design efficiency alone. Following this node, we do expect to return to a more normal bit density growth. We are truly excited by the progress we've made on our 1-alpha node, and we have an exciting road map ahead that builds on this momentum. Micron's DRAM road map will enable continued scaling with cost and performance improvements at industry pace over the next decade. This road map contemplates the deployment of high-case seam loss at the appropriate time to cost-effectively improve performance while lowering power consumption. We are making solid progress on our 1-beta node currently in development as well. And we have extensive pathfinding work focused on the nodes beyond that. We continue to evaluate EUV and are prepared to implement EUV when the time is right for Micron. Our 1-delta node may use EUV or multi-patterning, depending on a variety of factors in our pathfinding analysis. As we have previously stated, our multi-patterning immersion lithography provides a cost advantage relative to today's EUV, and our assessment will continue to do so for the next several years. Micron's proprietary multi-patterning technology combines our expertise in process technology and lithography with the most advanced emergent systems to provide a cost-effective road map. In addition, the quality and performance that we are able to obtain in our end DRAM products is highly dependent on the extreme care we take in minimizing all varieties of pattern variation that may occur during wafer processing. Our current lithography technology is a key enabler of our exceptional level of end-product quality that our customers depend on. This sets a high bar for us to ensure that we incorporate EUV at a time when it is capable of delivering to our high-quality standards. As we continue to evaluate EUV, there is no question that the EUV ecosystem and EUV tools will continue to improve. But for the next couple of nodes, they will not meet our industry-leading quality standards. We expect EUV will ultimately be capable of providing benefits for DRAM, and we are confident that our implementation of EUV for future DRAM is well aligned with that capability timing. Next, I'll move on to NAND. As a result of our strong execution over the last 2 years, we have successfully transitioned to replacement gate technology, enabling the world's highest layer count NAND at 176 layers. There were 3 fundamental ingredients we combined to make this happen: our replacement gate architecture, CMOS under the array and advanced charge trap process technology. Our 176-layer NAND has 40% higher layer count and a 30% smaller die size as compared to our leading competitor's latest offering. It features an industry-leading maximum data transfer rate at 1,600 mega transfers per second, which leads to faster system boot-up and improved user experience across multiple end markets. We also see better power performance capability with greater-than-2x improved power efficiency and ride performance versus Micron's 96-layer 3D NAND. This capability is essential for addressing future high-end mobile applications. Our first-generation 128-layer replacement gate node was designed to be a limited volume node to demonstrate the technology and obtain early manufacturing experience. As expected, node-to-node qualification time was substantially greater than for prior transitions. Through outstanding execution across the Micron team on our 176-layer node, we dramatically improved the qualification time and reestablished a competitive position. Now that we've put ourselves in a strong competitive position, we expect to pursue future node transitions at a typical industry cadence to maintain that position. Our road map continues to provide 3D NAND scaling and cost reductions for several generations. Beyond 176-layer, our 2xx replacement gate NAND will continue to deliver best-in-class technology and industry-leading performance specifications. Beyond 2xx replacement gate, we're in early development for the next node and pathfinding for subsequent generations. Additionally, we're focused on extending QLC leadership to accelerate hard disk drive replacement. Micron's transition to replacement gate provides better scalability with superior power and performance for several generations of 3D NAND to come. While floating gate was competitive across the key product attributes and made sense for less than 100 layers, replacement gate is the clear choice for greater than 100 layers. Despite the much higher layer count, our 176-layer replacement gate NAND has about the same z height as our current floating gate NAND in production and can easily scale to greater than 300 layers with dual-stack technology due to the structural simplicity and better aspect ratio per critical etches in the replacement gate technology flow. In addition to the superior cost we see with replacement gate technology, it also delivers better power efficiency and performance, enabling us to better serve our diverse end markets from edge to cloud. We also see the replacement gate technology of being able to support improved QLC compatibility for future node transitions with superior endurance capability. Now turning to products. Today, I'll highlight 3 leadership areas: ultra bandwidth solutions, mobile and solid-state drives. Memory and storage are foundational for artificial intelligence. Micron has strong product portfolios addressing this high-growth market, and our ultra bandwidth solutions are critical to resolve the data bottleneck that can be created while analyzing the massive data sets for AI. As I mentioned earlier, we've begun revenue shipments for our HBM2E products, which are a clear enabler for training and inferencing in the cloud. These products extend system bandwidth to greater than 2 terabytes per second and leverage our more than 20 years of experience in memory stacking and advanced packaging. This is an area where Micron has tremendous strength with thousands of patents. On the edge, our products play a critical role in inferencing. Our proprietary industry-leading GDDR6X product has applications for AI inferencing on the Edge and for gaming. We're extremely excited with what we've been able to accomplish with our GDDR6X, which was developed in close partnership with NVIDIA. The partnership has enabled them to deliver superior end-user experience, utilizing our industry-leading graphics DRAM bandwidth. This has allowed them to deliver differentiated system performance of greater than 1 terabyte per second. Our GDDR6X utilizes differentiated PAM4 multilevel signaling, which doubles the data transfer rate. In addition, this GDDR6X also lowers the power consumption by approximately 20% relative to industry standard GDDR6, helping improve energy efficiency on platforms where it's used. Leveraging our low-power DRAM and NAND technology leadership, Micron has also emerged as a technology and product leader in the mobile space with a complete portfolio of mobile products that are qualified with all major chipsets. Additionally, the breadth of our product portfolio offers our customers greater flexibility to design phones that better match their target market segments and redefine the end-user experience. Micron's LP5 is a great example of a product that redefines the end-user experience and our close collaboration with customers. Collaborating closely with Xiaomi, Micron was first to bring LP5 DRAM technology to market. This technology meets the growing consumer demand for 5G and AI functionality in smartphones. Building on the success we've had with LP4, and we lead in LP5 technology and power efficiency and speed, our 1z nanometer LP5 product has approximately 20% lower power consumption for bandwidth-intensive use cases, including 8K video recording compared to competitors' LP5. As mentioned before, we expect a fully 15 -- a further 15% improvement with our 1-alpha DRAM node. Our LP5 is also the fastest low-power DRAM in the market, delivering industry-leading gigabits per second, translating into better performance for AI applications, superior photo and video and more. Micron has growing momentum across our expansive SSD portfolio. We have made significant progress over the past year and now have NVMe SSDs for data center, client and automotive. We're leveraging greater levels of vertical integration to deliver differentiated solutions to our customers. Our broadening portfolio of SSDs using internally-developed controllers is a great example. Micron is an industry leader in QLC SSDs, providing leading density and performance at a compelling value to accelerate hard disk drive replacement. Micron's broad portfolio also delivers breakthrough performance on the other end of the spectrum with the world's fastest SSD. The X100, based on 3D XPoint and our proprietary system solution innovations, delivers close to 4x better random read and mixed workload bandwidth versus competitor SSDs with the same media. Our mission is to transform how the world uses the information to enrich life for all. This starts with our focus on innovation, technology acceleration and execution. This focus over the past several years has resulted in the significant advancement in our overall competitive position. It extends to products where Micron has the industry's broadest portfolio and is driving to deliver product leadership. It also enables our customers to unleash the power of data and win in the data-centric era. With that, I would like to thank you for your participation in today's webcast and open up the line for questions.

[Operator Instructions] I show our first question comes from the line of C.J. Muse from Evercore.

I guess, Scott, my question is on EUV. And you talked about, really, a focus on cost. And so just curious, what kind of improvement in throughput do you think you'll need versus ASML's D tool to get to the point where it's cost competitive with multi-patterning? And then how do you think about the time to yield and uniformity within that kind of economic bucket of when adoption of EUV would make sense for you guys?

Sure. Thanks for the question. So first off, without getting down to specific numbers, we've looked at the road map, including both performance and long-term performance in terms of long-term downs on tools as well as the overall just capability road map of EUV in the industry, and there's clearly going to be different adoption times for different competitors depending on the situation. For our particular applications on DRAM, we do still think it's going to be another 2 or 3 years before it makes the most sense for us to implement EUV based on assumptions that the performance will continue to make good progress over -- and improvements over the next several years. So I think the throughput road maps are kind of out there for different -- or at least assumptions around them for what the supplier is going to provide. And we think that the road map will hit sometime in that time period the right throughput for us to go forward. The second piece is really around -- in our decision, is really around making sure that the overall quality of our product can be maintained as we continue to shrink. And our confidence in our multi-patterning approach that we've talked about before is high, and our ability to execute high-quality products as well as to develop them quickly is also high. So I think we're confident in this approach. We think we'll be prepared to implement EUV at the right time for Micron and continue to keep our technology in a strong position, some of which I talked about today in terms of where our DRAM road map is at now, which is a strong competitive position, and we believe that will continue through the next several years, and we'll implement EUV at a time when it lets us continue that pace.

I show our next question comes from the line of Harlan Sur from JPMorgan.

We know what the team's cost down targets in DRAM and NAND are going to be this fiscal year, down mid-single-digits percentage in DRAM, down low- to mid-teens percentage in NAND. But the road map that you've just outlined for your future technologies, what can we expect in terms of DRAM and NAND cost down targets on an annualized basis?

So we're not changing our projection on what our cost downs are going to be. Our strategy continues to be to optimize our technology nodes with the capability to get the most cost down that we can out of them, depending on how we move forward with the amount of bit growth we have each year. And our strategy continues to be aimed at matching our supply growth with where we see the demand growth being. Inside of that, we optimize our cost structure and these technology nodes, both on the NAND and the DRAM side, really let us have an advantage or an opportunity to optimize that cost structure in a meaningful way by providing a significant benefit. Both the 1-alpha and the 176-tier nodes are better nodes than we've introduced on the prior generations. And that happens through time as every node is not created equal and either in the inside or the DRAM side. We tend to have some nodes that are -- some that are a little better and some that are a little bit worse, and these are both very strong nodes. Overall, we'll continue with the pace that I've talked about before.

I show our next question comes from the line of Timothy Arcuri from UBS.

I actually had 2 questions wrapped into one. I guess the first question on Slide 13. So it looks like for 1-alpha, you're sort of getting back to the same sort of bit per wafer growth that you had for 1x. So I guess the first question is for Dave, and then the second question for Scott. So Dave, does this mean that the cost down should get back if you look at 1z versus 1-alpha? Should the cost downs for 1-alpha get back to the mid-teens that they were for 1x versus the mid-singles today for 1z? And then I guess, for Scott, clearly, it's not related to EUV. So can you maybe double-click a little bit on sort of how you're getting that increase in bit per wafer? Is it some aspect of 3D DRAM, something like that?

Sure. David?

So yes -- so Tim, we don't talk about the specific cost decline by node. I would say, I think you're making a good assumption that at least directionally that one-off has a really good cost structure to it, that it contributes to actually decent cost declines for fiscal '21. We talk about this mid-single digit, but that includes some mix headwinds. So you strip that out, it's actually a bit higher, the cost declines. And of course, 1-alpha doesn't really start getting going until the first half of the calendar year. So that will certainly mean that on average, that cost is much better than that and is helping drive decent cost reduction into fiscal '21 that should carry on in a more meaningful way in fiscal '22. That's about as much kind of quantitative information that I can give you on the cost side.

And on the architecture side, I would just say this is purely a shrink on planar DRAM. And the combination of how we've chosen to develop this node in terms of the minimum feature size and as well as we have a substantial improvement on this particular node purely from design efficiency. And one of the challenges that we have had in the past node or 2 in terms of driving the best possible bit per wafer has been a need to improve our design efficiency. Our design team has really done an outstanding job here with what I referenced on 10% of the efficiency being purely just out of how we designed this chip in a more efficient way relative to the previous 1z node. And the rest of it comes from just the technology shrink in standard planar DRAM.

Our next question comes from the line of Joe Moore from Morgan Stanley.

I wanted to ask about your lead in GDDR6X that you talked about. How long do you think you keep a strong position there? And I guess when you talk about using PAM4 in a DRAM chip, that's not a capability that I would have thought Micron had. Until that shift came out, how long do you think it takes your competitors to get to where you are on that technology?

Sure. Well, first off, I think one of the important things about a development like this, where we're working closely with customers, is that we're able to really enable some special products as we have and some products that are incorporating and taking advantage of the technology that we've developed over a number of years. So while I can't comment on how specifically long it's going to take any of our given competitors to develop something similar, I know that it gives us an opportunity to create differentiation for our customers, which is important. And for sure, a DRAM development from grounds up on a new technology takes some amount -- a significant amount of time no matter what. So assuming people started trying to figure it out once we brought it out, then it will take a year plus, but it can be longer. It's a -- I think, a really novel technology advancement, and we hope to have more of those in the future, partnering closely with our customers.

I show our next question comes from the line of Aaron Rakers from Wells Fargo.

Congrats on the strong execution. I guess my question is away from DRAM and NAND. I just wanted to ask about 3D XPoint as you continue to kind of carry 200 basis points plus of headwind to gross margin. Any update on how we should think about the progression of 3D XPoint, the SSD road map and when we should kind of consider that hitting a volume and kind of lessening that gross margin headwind?

Yes. I might leave that one for Dave on -- relative to the financial firms. We're focused on the technology we continue to be in terms of creating differentiated products. We'll have more on that as we go through this year on exactly what those products are and what the specific, probably more clear estimates of the volumes are. But at this point today, I can tell you, we're making strong progress in the development of those products, and we have confidence in the road map. And other than that, I'll leave that to Dave to add any color he'd like to.

Sure. So on the underloading charges -- sorry, my phone started to connect to the speaker. On the underloading charges, we were, I don't know, I think, at about $155 million in the third quarter. We managed to get that down despite the extra week, down to about $135 million in the fourth quarter. It should trend through the year and I think by the end of the year, get fairly close to $100 million of underload charge. So we are making some improvements while we wait for the products to ramp by just better managing the spend of that specific fab. But as you, I think, point out and as Scott talked about, really, where we see these underloading charges really go away is when the volume of those products start to ramp in the fabs and that gets the fab to be fully utilized and thus those kind of utilization charges get de minimis. It's going to take a while for that to happen, probably a couple of years. Whenever you're dealing with new technologies like this, even as fast as we can innovate, still the market takes a while to adopt these in volume and figure out use cases that really exploit the technology. We think that will take a few years before that really happens. So we'll likely see a little bit of revenue in the next couple of years, but I think it will be relatively small. And then I think at some point, we'll see a knee in the -- knee of the curve here, and the products take off and the underutilization charge will cease to be a headwind for us.

I show your next question comes from the line of John Pitzer from Credit Suisse.

Scott, I'm just kind of curious When you think about DRAM and the introduction of EUV, when you guys move to EUV, would you expect that to be kind of a normal shrink node for you? Or is it going to be something akin to replacement gate where you have to go through some learning pains before you kind of get normal cost down? And to the extent that EUV sounds mostly like a cost decision to you, not a capability decision, I'm just kind of curious as to why you think peers will be moving to EUV more quickly than you? What are they seeing on the cost side that you guys aren't?