Rambus Inc. (RMBS) Earnings Call Transcript & Summary

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Good morning, everybody. My name is Gary Mobley. I'm one of the semiconductor research analyst here at Wells Fargo Securities. Joining me is Aaron Rakers, who also covers semiconductors here at Wells. And with us today, we have our 2 guests, we have Steven Woo from Rambus, and we have Desmond Lynch, who you all may know as the CFO of Rambus. And the topic here today is a discussion about CXL, about the market adoption of the technology, what it means for the industry, what it means for Rambus. But before we get into that, I wanted to turn it over to Steven so that he can introduce himself and establish a context for a discussion.

Thanks very much, Gary. Hi, everyone. My name is Steve Woo. I'm a fellow and a distinguished inventor here at Rambus. I've been with the company for more than 25 years. And I've donned a number of roles within the company. I've worked in technology development and architecture and product planning and strategy as well. I worked my way back around to the research side of our organization. And today, I lead a team of senior architects looking at some of the important technologies that are shaping the future of things like the data center. So I'm very happy to be here to get a chance to talk about CXL and its impact in the future.

Appreciate that, Steven -- Steve, I should say. I know you have some slides that you can perhaps share with us. And I guess as an introduction to the slides, I was hoping that maybe you could give us an overview of the technology. I know there's a lot of buzz out there relating to CXL. Perhaps if you can start off by telling us what all the excitement is about.

Sure. Yes. I think that's a great place to start. So CXL is a really interesting technology. And there have been these challenges that have been brewing in the data center for the last 10, 15 years. And on this slide here, you see what 3 of really the biggest challenges are, and they're only going to get worse going forward. So the first on the left is that in companies like Intel and AMD, they've been great at delivering more cores per CPU. But the challenge that happens is every one of these cores wants its own memory bandwidth and its own memory capacity. They're all running different programs and they all have different requirements. So the challenge that comes up is you need to keep scaling that memory bandwidth and capacity so each new core that gets brought in has some resources that it can do its own work in. Now what you'll see on that slide is -- in that little graph is, in the green line, it's the number of cores per CPU. It's going up into the right. And if you look at the orange line, which is the memory bandwidth per core that's available, you see that as kind of sloping downward to the right, unfortunately, which means every new core is getting less memory bandwidth than in previous years. And just the way programs work, you always want the same or more resources. And so this is a challenge. The question is how do you continue to give the resources that these cores want. In the middle there, you see what's this classic picture of the memory hierarchy. You have different kinds of memory and storage that are available to your processor cores. There's on-chip caches, which are very fast and then you have direct attached DRAM, which is a little bit slower, but you get a lot of it. And it's great because it can hold lots and lots of data. But then once you get past that, there's this huge gap in terms of latency and bandwidth. And so after your locally-attached memory, you have storage. And so you have to be very careful as a programmer. You don't want to be executing out of your discs because it's so incredibly slow. And it's very low bandwidth as well. You can get a lot of it. But from a performance standpoint, it's really just not what you want to be doing. So the question is, as these -- our data sets get larger and as our programs get bigger, how do you either avoid that gap or really the current view is, how do you fill it? I need something else that can go in there. And then the third thing on the right is there is an issue of memory stranding. Now memory is a very important resource in your system. And it's very useful, and it's fast compared to anything else that's outside of the processor. But the challenge is that the way servers are put together today, they're put together in kind of these fixed ratios where you buy a server and it's got a couple of processors and some fixed amount of memory. And so it really forces you to think, well, I have to size things in a way that it's the worst case workload I'll ever deal with, which means sometimes in the average case, you're not really using all that memory. It would be really nice if there was a way to have more of a composable infrastructure. As my jobs come in, it'd be nice to be able to just marshal whatever resources I need for that job. And in some cases, I might be borrowing them from someplace else, and I could just give them back when I'm done. And in other cases, I might just have enough that's in the box. And so something that's a little bit more tailorable and something that's a little bit more dynamic can really help improve the cost of operation. And so CXL is really the result of understanding what some of these limitations' challenges are and kind of finding ways to address them. So let's take a look at how CXL does some of these things. So I mentioned that big gap in the hierarchy, and you can see here, there's kind of these 3 new levels that get inserted into that gap. So after your direct-attached DRAM that goes directly on the CPU, you can now have direct-attached CXL DRAM. So you can take the same kind of DRAM chips, and you can connect them through another kind of interconnect -- the CXL interconnect. It's a little bit longer latency than the direct-attached native DRAM, but it gives you this great expansion capability in both bandwidth and capacity. A little bit beyond that is this notion of pooling memory where we can have appliances that are just full of memory. And you can kind of treat them like a library where if a processor runs out of its own local memory and it needs more, it can go to this appliance and kind of borrow, it can provision or check out some memory and use it for the duration of a job and then give it back so some other job can use it in the future, and that helps improve both the utilization and the operating costs. And then kind of a little bit below that is this notion of switch or fabric-attached memory where we can have these appliances and they can be accessible through a fabric, kind of like a network just for memory. And so what that does is it gives you a much broader expansion capability and a much wider sharing capability. And so these are the ways that CXL can help us introduce new tiers into the memory hierarchy and fill that massive, really, chasm that exists today between DRAM and storage. And then let's take a look at some of the benefits now. And here's a classic server that you see in the image here. You have a few different kinds of processors, you have a CPU, sometimes you have a Smart NIC, and you can have accelerators like AI engines and things like that. And really, the CPU has got its own direct-attached DDR memory. And in the case of AI, the AI engine will have its own high-performance memory as well. And you can kind of see there's not a lot of opportunity really to expand across a wide range of capacities and bandwidths here. Things are kind of fixed. But when you start thinking about what CXL can do for you, what you see is there's these new attach points now for memory. And so you see these CXL memory modules attached to both the CPU and the AI engine. What it allows you to do is if you need it, you can expand both the amount of memory capacity and the memory bandwidth that's available to both of those engines. The bandwidth is really directly related to the number of links over which data travels. It's kind of like if you had a freeway, like a 4-lane freeway and you went to a 5-lane freeway, you can now handle more traffic. It's more -- it handles more bandwidth. And it has a nice capability in addition to giving you that capacity, to giving you the bandwidth that these engines really want. What it also does is, if you have a choice to add some memory, you can -- because you can add it across these extra links, then what it does is it scales the amount of bandwidth along with the capacity. And that's important. As we add more cores, each one again wants its own memory bandwidth and capacity. So being able to scale both of those as the core counts goes up, makes it very, very useful. CXL also offers this other really interesting capability. So you'll see on the CXL memory module, there's something kind of blue here, and it's a CXL memory controller. And what that controller chip does is it gives you, what's called, media independence. So when the CPU talks to this module, it doesn't really know what kind of memory is here. It just passes a request on to this blue chip in the center of the module. And that chip can kind of talk natively to whatever kind of memory is on the module. And so that media independence means I can put lots of different kinds of things there. I could put like a storage class memory. I can put many different kinds of DDR back there. And so that's -- as the industry thinks about new kinds of memory in the future, and there's a possible attach point now and a good method for being able to do that. And then the other thing that's really kind of interesting about it is, if you look at the kind of the resources on a chip that are required to talk to a DDR memory, there's quite a lot of pins and then there's some silicon real estate for like a controller that will [ never ] talk to the DDR. And so, yes, the interesting thing about this is, with CXL, you don't require as many pins now to talk to something that's externally connected. So it becomes more pin-efficient, and it is a more general interface. So if you decide, in your system, that memory is the thing you need, great, you can -- through this narrow interface, you can add memory modules. But if you decide that there's something else you need to talk to, maybe it's another accelerator or maybe it's another kind of device, maybe it's a storage device or something like that, you can use these CXL interconnects to talk to that as well. It turns out that memory is often talked about because it's such a precious resource, and it's such a limiter in systems. But CXL is a more general kind of interconnect that allows you to do really different kinds of things here. And then once we get kind of beyond the direct-attached capabilities that CXL gives you, there is this really neat capability called pooling that I mentioned before, where the vision for the future is that you can have a bunch of compute nodes like dual socket servers, and those are shown in kind of this gold up at the top here. You see a bunch of these compute nodes. And then what we have are a bunch of memory nodes on the bottom. And so what you can do with these interconnects is the compute nodes can be -- they can have connections to multiple of these memory nodes. And as they need resources, they just borrow them from these pools, they check out the resources and then check them back in. It's nice to be able to do something like this because within a data center, we've seen that the number and really variants of the kinds of workloads has grown dramatically. If you go to Microsoft Azure or Amazon AWS, you can just see the many, many different kinds of computing instances that you can rent. And so the data center folks are having to keep up with this tremendous diversity of workloads and something like this allows them to do that and also have a good kind of operating cost as well. So once this is in place, then what you can do is, you can actually start thinking about not only having direct connections between these compute nodes and memory nodes, but you can have switches in between them, just like we do in Ethernet today. And so you can start to have now fabrics and things that allow memory to be connected to compute resources and you can start to scale in really dramatic ways now. So these resources can be shared very widely and very broadly across the data center. And that will continue to give you, as a user, even better use cases where you can have lots and lots of memory at your disposal. And then from a data center standpoint, it gives you the option to support even wider ranges of workloads. So just what we're seeing is kind of this ability to continue to address the needs for more memory and the ability to have nice scalable solutions.

Thank you for that overview. I forgot to mention something when we started. If you have a question, you can e-mail my colleague, Aaron Rakers, at [email protected]. But I wanted to ask you, Steve, how does the industry plan to support CXL going forward?

Yes, it's a really good question. So what we're seeing is this very broad industry support. So there's a consortium, which is always a good first step. And what we're seeing is we're seeing really just tremendous support, top to bottom, in the supply chain and the value chain. So companies from cloud service providers and traditional server manufacturers, they're all supporting CXL. They're all part of the consortium. And then of course, you need really good support on the processor side. And so companies like Intel, AMD, Arm, they're all part of the consortium as well. So -- and they're even publicly talking about it. They're saying, well, my processor, in the case of Intel, they're saying Sapphire Rapids, which is the kind of the next big architecture evolution on their server product line is supporting CXL. And we're getting similar messages from other companies. And so that kind of support starts to trickle down through the value chain, and you see companies that are component manufacturers and suppliers are supporting it. Memory manufacturers are supporting it and companies like Rambus through silicon IP and products are supporting it as well. So we see this great top to bottom kind of support. And honestly, this is what it should look like when you're looking at a new technology that needs to come out. It takes quite a lot of companies working together. In terms of kind of how the industry is looking at a rollout of the technology, there's a longer-term vision to get to pooling and to get to sharing and switching. And it takes multiple steps to get there. And so the early versions of the standard, CXL 1.1, really, that's kind of an initial deployment of the CXL standard. And what you see is the introduction of the different use cases for CXL. It's a very -- in my opinion, a very smart rollout strategy. They're leveraging existing physical technology like PCI Express Gen 5, so something you know and you know how to work with and something that you're layering on top, which is new, which is CXL and some new use cases. And then following that is really the deployment of CXL 2.0. And this is where you'll see kind of, again, growth and some new capabilities. One of them is memory pooling, like I mentioned. And also, we're seeing more capability that's being built in for security as well. A lot of concern that when you're having shared infrastructure among many people that you need to have support for security in that infrastructure as well. And then the kind of larger scale out that I showed with switches and things like that, that comes with CXL 3.0, and it gives you faster interconnect. So PCIe Gen 6 is really the target there. And also, this thing called coherent memory is another kind of important capability that CXL 3.0 will enable. And really, what that means is kind of a fancy way of just saying -- these days, everybody wants to take a big problem and they want to break it up into pieces and run it in parallel across lots of engines. The AI guys do this all the time, where you have these big language models and you train it across many -- for example, NVIDIA training engines. And people want to do that with the CPUs as well. And you have to have a way to share that memory. Now once you have a big problem that you break into pieces, then you have to have a way that they can communicate and they can see -- one processor can see another's update. And so that's what coherent memory is all about. So these are just some of the ways that CXL is being enabled, but it's got a very, I think, well-thought-out enablement plan and a very well-thought-out progression.

So to recap, expanders, pooling and switches, are those really kind of the 3 main product families that will essentially embody the CXL technology? And related to that, how is Rambus positioning in the CXL market?

Yes, that's right. I think it is a progression of -- and like you mentioned, the expansion and pooling and then larger scale switching. Yes, it's a growth of kind of the -- yes, the size and scale of what can be managed with CXL. That's right. Yes, in terms of what Rambus wants to do, and so let me kind of talk about the various kinds of products and things that are kind of slated to be on the market. And so like you mentioned, the kind of the first step is going to be that bandwidth and capacity expansion. And that's really in the -- it's really going to start taking off in that kind of 2024 time frame. And pooling is going to follow shortly after. And so you can kind of think of the bandwidth and expansion capability as the first step and it helps to really enable and establish some of the software infrastructure and things that are going to be needed for pooling. And then following that is when we'll have kind of the whole rack level composability and large scale with switches as well. So that's kind of the deployment time lines and where we're going to see vectors of differentiation. People are going to have a number of different offerings within each of those product categories. And they're going to be differentiated by things like what is the bandwidth you're going to be able to provide. Just like we see in memory modules, DIMMs today, there's going to be speed grades. And so some people will specialize in the higher speed grades and some will specialize in kind of the maybe lower speed grades but higher capacity, those kinds of things. Latency is going to be really important here. And so that controller chip that I pointed to, that blue controller chip on the CXL modules, the design of that is going to -- there are a couple of different ways you can think about doing it. And some of those solutions are going to really bias the latency over anything else. Scalability is another way people will differentiate, how many compute nodes can talk to a memory node at a time. There are different trade-offs you can do there as well. Security, like I mentioned, there's -- there are provisions in the standard for encrypting the links, but there's other things that you can actually do as well. You can have a root of trust that really helps to attest to the authenticity of both the memory node itself and allowing access to certain data as well, things like encryption, just to make sure the data that's there is accessible by only the people that are allowed to access it. And there are some other things too like power efficiency and some other things like reliability as well. So there's a need to have these things to be very reliable since they'll have lots of data in them. So those are some of the kind of the main ways people will differentiate. And so as we think about kind of how Rambus is really interested in kind of working in the area -- we're -- we've already got products today that are helping to enable the CXL infrastructure. So one example of that is we have in our portfolio of silicon IP cores, it's really an industry-leading portfolio, got a lot of great connectivity solutions like PCI Express, and we also have controllers that are important and security cores as well. So some of these fundamental building blocks, we've got them already today. Looking further out, we do have product plans. And so our plan is to attack some of the early use cases like memory bandwidth and capacity expansion and then eventually pooling. And we're getting a lot of good interaction with people in the cloud space and the server space as well as the memory manufacturers. And our plans are kind of aligned pretty well to that time line I just showed.

Okay. I know my colleague Aaron Rakers is chomping at the bit to ask some questions. So I'm going to turn it over to him for a little bit.

Yes. Thanks, Gary. Thanks, Steve, for doing this. And as Gary mentioned earlier, if anybody wants to ask a question, feel free to e-mail me. It should be shown here on the slide. So we had written a note, actually published a detailed dive into CXL on Tuesday. And I guess maybe the first question I'll ask you is that, as we think about the opportunity set, do you think that we're going to see AMD Genoa launch next week with, I think, 1.1 support, you mentioned Sapphire Rapids. The 3.0 specification, just that to me seems like the inflection point. I guess, first of all, would you agree with that notion? And if so, can you just like -- when do you expect to see or how do we, as investors, kind of gauge the progression of that standard and when maybe that becomes more tangible in the market as far as end products?

Yes. I think the end goal is to try and get to something like -- to get to the capabilities and the architecture that CXL 3.0 enables. And it's one of those things where each one of the releases, the 1.1, 2.0 and 3.0, as you see processors supporting those, those are all important steps in getting to that end goal. And so I guess the way that I kind of see it is I think each one of those steps is very important for the industry. That end goal, of course, is important to get to. But it's something that needs to be built up to, and that's kind of why that you see this plan for a more phased rollout of the specs and things. I think that each one of them will see kind of an important change in the ecosystem and an important -- I kind of think of them as each inflection points, really, as you get to -- and some of them may be bigger than others, obviously. And obviously, the end goal is to get to something kind of large and encompassing like CXL 3.0. But I do think each of the other steps are going to be important as well.

Yes. And I think on the architecture side, just so I maybe level set for those in the audience that aren't as familiar, like this idea of the pin count, the real estate attributes of the DDR5 controllers or DDR4 controllers of the DDR5, I should point out, I think, actually, Genoa next week moves from 8 to actual 12 channels of support on that processor. Can you just help us understand like CXL actually takes all of that controller functionality, so what's actually on the stock? What's the -- help me understand again that migration of the controller of the [ stock is ] and what exactly that means? And then I'm going to throw the other part of that question in there. You mentioned coherency, right, and the importance of coherent memory with CXL 3.0. Can you just help us appreciate how does that -- what's coherent mean relative to how things are deployed today?

Yes, yes, absolutely. So let me take that first question about -- talking about kind of the interconnects and things like that. So one, the thing that's really interesting about it is, like you mentioned, Genoa is going to go from 8 channels of DDR to 12. And so what that does speak to is both the need for more memory capacity and the need for more memory bandwidth. So those are things that are really important. And it turns out that the DDR interface itself is pretty wide. And so there's a lot of pins associated with each of those interfaces. And so if you look at the CPUs that are coming out with when you go from 8 to 12 memory channels, it's dominated by pins that are meant for kind of the memory interface. Now what that means is every one of those processors, it pays for the pins and the real estate for the memory controller that's used to talk to the memory channels. And so they're wide and you are getting to a point where, wow, it's getting harder and harder to add pins. And so the thinking is, with something like CXL, especially for memory, it's always good to have some locally-attached memory. But if you can take those pins and maybe use them in a slightly different way, and so a CXL interface only takes 1/3 of the pins as a memory interface. What you can then do is, you can say, wow, I can effectively put 3x as many CXL channels in that same pin count. Now what you have to do in order to do that is you end up having a module with this kind of smarter chip that has a memory controller in it. And on the CPU side, you do have to have a digital logic core that's capable of [ talking ] to the CXL protocol to this chip that's on the memory module. So what gets replaced is kind of the wide pin count interface of a memory interface, along with the memory controller, that memory controller moves into this blue chip and you replace it with a smaller number of pins and in a smaller digital core that talks to this blue chip. And so really what it does is it gives you kind of a more pin-efficient interface that takes less real estate to implement that interface. And it's a little bit more general too. So you don't have to put memory there if you don't want or you can dynamically reconfigure your server if you want to use memory 1 month and then you decide you want an accelerator there on another month, that kind of thing.

And the coherence question?

Yes. So for coherence, coherence is an interesting kind of thing. So I'll give you an example. So one example might be, imagine you had 10 billion numbers and you had to add them all up. And so one way you could do that is you could have one CPU just kind of run through all 10 billion numbers and kind of add them all together. But another way to do it is you could break the problem up into 10 pieces, and you could have 10 processors, you can have them each add up 1 billion numbers. And when they each have their own kind of partial sum, they could agree to add them all together. And you can see that could be done a lot faster because you're employing 10 engines. Now the challenge is when you get to the very end and everybody has their own partial sum, you have to agree on kind of where to put the global sum of all these numbers. And so you usually will say, there's this one memory location where the sum is going to be. And what every processor is going to do is, it's going to say, I'm going to take whatever value is in that location, I'm going to add my partial sum to it. And by the time we get all done, we get the sum total of these 10 billion numbers. And so what this coherence does is it ensures that when one processor does its update to the data that other people can see it. So the worst thing that could happen is we each go to write in our value, and we miss some update that someone else has put in. And so a coherence is a -- it's a very interesting way that the hardware inherently ensures that you don't miss an update. And that's very important as people move to these multiprocessor sharing kind of applications. And that's really the direction people have been going for a while. So you see it in AI, and you do see it today in processors as well. But that's really what it's about.

Yes, that's very helpful. So I'm going to ask you the question, I've gotten a handful of e-mails on already. And I think the loaded question that a lot of us investors are kind of thinking about, I think there was an article a while back talking about this idea of stranded memory, right? I think Microsoft is out there saying, look, 25% of our Azure memory is "stranded" or underutilized. Does CXL, in a simplistic form or fashion, do you see CXLs expanding memory in the data center? Or do you see it potentially allowing data center customers will not use -- allowing those data center customers to deploy less memory?

Yes, it's a good question. And my firm belief is that it will end up expanding both the capabilities and the amount of memory that's needed in the data center. And it's really -- I think historically, if we look back at some of these really interesting technologies that have been introduced in the data center that improve efficiency, what we find is that they end up increasing the market as well. So one example of that is just multi-core processors. I mean there was this concern that when you went from single core to dual core processors that suddenly the number of servers sold would get cut in half. And really what happened, historically, you can see, what it did is it made more efficient computing infrastructure that people wanted more of, and it kind of drove more hardware sales. Same thing with virtualization. Once the hardware got more efficient, then people began to realize, hey, there's this other really neat use cases I can implement. And that just allowed me to write better software, and it made the demand higher. My belief here is that when you talk to software people, there is this concern that I'm not allowed to write the kind of software I really want to write because I'm limited by the amount of memory that's available to me. And I think once you start to open that up, like we've seen time and time again, when you give software people more capable hardware, you get better applications, you get new use cases and use models and really interesting things start to happen that just spur a higher demand for those use cases. So my belief is that just like we've seen many times over the last 20 years, more capable, more efficient and more rich hardware being provided is going to lead to just higher demand and better software.

Yes. And I agree. I think actually, Micron as a reference, right, at their Analyst Day earlier this year, said that CXL would be a $20 billion addressable market over the next -- I forget the time horizon, but definitely progressing rapidly as we move forward. I'm going to throw one other kind of architectural kind of thought out there and wonder if this resonates with you and feel free to refute it. When you start to go down the path of CXL 3.0 and you start to think about memory appliances and disaggregation and composability, is it not fair to also think about this as similar to the transition when we went from direct-attached storage in the back of a server to a network topology, fiber channel SANs or NAVs? Does that make sense to you as well as you kind of think about that 3.0 path going forward?

It does. I mean what we've seen in general is that, like you point out, connectivity has its own benefit. So once you can have connectivity and shareability of resource, and storage is a great example of that, you see that people begin to use it in new ways. And really the driver, I think, in both of those cases is that the amount of data in the world is continuing to grow rapidly and you need some way to store that data and parse through it all to get some meaning from it. And so one of the big drivers that we're seeing is digital data is doubling every -- really every like 2 to 3 years, the amount of digital data in the world doubles. And we got to search it all, we have to process it, we have to extract meaning from it, being able to share that among multiple engines in a way like -- through switched memory that CXL 3.0 will allow. That's just going to allow us to, again, have better insights and really better use cases around the data.

And I think in that context, should we be thinking about system like architecture, so instead of like DDR, it looks like PCIe connected slots inside of a server, but actually taking CXL outside the server and actually having, again, those dedicated -- where do you see the appliance market evolving towards?

Yes, it's a good question. I think a lot of it really depends on the use cases that are put into place, but there's a definite need for something like the appliances, just based on things like you see like stranding and the fact that people want these large footprint applications that just go well beyond the amount of memory that is inside a server. And then that's just an application that might run on 1 or 2 cores and the number of cores that are in the CPU is growing dramatically as well. So these appliances are really -- I think, a really nice solution to address both the growing need for larger footprint applications and just the fact that the CPUs have more cores in them.

Yes. And so I -- and Gary told me to kind of keep rolling here, so I'm going to keep rolling a bit. So I appreciate you [ filling ] these kind of questions for me. Rambus plays in that market in what form? I'm not as familiar as obviously Gary, but anybody in the audience, Rambus' role in that kind of evolution of that product portfolio is what exactly?

Yes, absolutely. I've got a couple of slides here that kind of talk about it. One is we do have a long history in memory. Our company was founded to develop new memory solutions. And so just some examples, we've been kind of at the front for many years, and we had the first kind of DDR5 buffer chip sets. So we've been helping enable the industry on new memory technologies. We also do a lot of kind of silicon IP. And so we specialize in really high performance, so things like for AI engines, things like HBM and GDDR, and we do a lot of controller and security cores as well. We do have a strong focus on innovation, and that's where I work right now is in Rambus Labs where we do a lot of forward-looking stuff. We did a very interesting project about 7 or 8 years ago now, where we did look at pooled memory, and you can see kind of a picture of the Smart Data Acceleration board here, where we looked at some of the foundational technologies and changes that would be needed to support pooled memory. And so that's something else that we kind of lean on all of these capabilities. And really just the kind of the DNA of our company is about looking at memory and kind of what some of the problems are. So all of that kind of gets rolled into how we think about things. And where we're positioned really well, as you can kind of see here, this gray box in the middle, it just represents the kind of things that have to go into a CXL controller chip. And so what you have to have is you have to have some physical interconnect to the outside world. So these processors are going to talk over CXL links. The physical implementation of it is the PCI Express, and we've been doing PCI Express controllers and PHYs for seems like forever. And so it's a very important part of our portfolio, but it has been something we've been working on for a couple of decades. So we lean on that experience. In terms of the security cores, what's really interesting is that we have that capability in-house as well. And we have some industry-leading security cores that cover a range of different security levels and needs. And so as we see the market evolving, security is becoming more and more important and kind of more of a first-class design constraint that you have to really think about how to architect that in to the system as well. We do, of course, do memory controllers and PHYs and we've worked for a very long time with the industry on qualifying memory. So we have our DIMM buffer chipsets that we work with both the DRAM manufacturers and the system houses to validate, and we work with Intel and AMD as well. And so that capability is -- it's very important to be able to say your controller chip is validated and works with the memory manufacturers' parts. And then really, just that whole notion of how to sew everything together and how to make sure that you can ensure that the chip and the whole system is going to work together because it's complex. I mean you're putting multiple pieces together. So these are just the areas that we're kind of, I think, uniquely positioned to serve the market.

Yes. And I got a few other quick questions, and I'm going to bounce around here a little bit. But I'm going to go back to that stranded memory discussion. As CXL comes to market, you start seeing these disaggregation of the controllers and new products supporting CXL. I guess, first question on that, do you see CXL actually diminishing or replacing DDR, DIMMs on a server standpoint? And second to that, CXL, it's not like CXL comes to market, you can unlock this capacity that's existing in this "stranded capacity" in your existing data center, CXL is truly a new incremental deployment of memory footprint.

Yes. So I think what -- at least what I see and when we talk to people, I mean where CXL is really helpful in the initial deployments is there are people that are writing software that are just limited by what their resources are that are inside the box. And so the initial deployments of extra bandwidth and capacity through expansion, that will address that part of the market. And so that will be a good enabler for the first step really in trying to improve what's available to applications. In terms of kind of what comes next in the footprint and all, I mean, we definitely -- when we talk to people, they literally can't get enough memory. And so the next step is how do you provide kind of a resource, a large pool of memory that you may not need all the time, but it's something that can be more efficiently deployed more frequently in the data center, and that's kind of where we see the pooling happening as well. And there's a definite -- there's been a need for that for probably 10 years. We've been hearing this particular problem as well. So yes, I mean, I think in the end, if it plays out like it's played out so many times before, I think in the end, the memory footprint within the data center just continues to get larger and larger in part because these capabilities are unlocked with CXL.

Yes, I agree. So the final question, and I'll pass it to Gary unless there's anything that I should be asking and I'm not asking you. Definitely, I'd love to know that. But there's been a lot of standards, right? There's a lot of alphabet [indiscernible] acronyms around memory interconnects, I remember writing a note on Gen Z, OpenCAPI, I think there's CCIX, but CXL is solidified. So should we -- I guess the simple question is, should we be paying attention to those other standards or is CXL just definitely the defined path as we move forward?

Yes. I mean the short answer to it is CXL looks like it's the one. And really, what we've seen is that there's broad industry support, there's public road maps that people talk about that support top to bottom. So the component suppliers, the processor people, the data center folks, everyone is out there talking about their support for it. And we're seeing a lot of, kind of, behind the scenes, there's a lot of movement in the value chain to support this as well. So I think the other efforts, they were all very good. They speak to the problem that memory, in particular, and just connectivity in general, needs to improve. And what we've seen also with Gen Z is that it's now merged into the CXL consortium. So many of the learnings that were important in the early years for these other standards, they're now getting -- we now get the benefit of them in the one interconnect that everybody is really kind of unifying around, which is CXL.

Yes. I'll pass it back to Gary unless, Steve, you have anything that I should have asked you that I didn't.

I do have one closing question. And so your silicon IP business, if I'm not mistaken, is now at about $125 million annual run rate. And I think some of the acquisitions that formed the basis for your licensable CXL and PCIe intellectual properties and the key drivers to that. So my question to you is, who do you see as the main competition on the silicon IP side? And who do you see as the main competition on the chipset side of the CXL market?

Yes. I think it's hard to -- it's hard for me to kind of talk about other companies because you're sort of not in the huddle with them to understand sort of what their plans are and things like that. I think really the thing that's most important in all of this is it's very clear it's going to be a big market. And so the things that we provide in our portfolio today, like silicon IP, there's a lot of applicability of that for CXL-based solutions, whether they be memory-based or accelerator-based, they're going to need CXL controllers, they're going to need PCI Express interfaces, and so that does -- because there's a new type of interconnect that grows the market for some of our solutions that we have today. In terms of where we go in the future, it's very clear that there's a tremendous need and there will be other companies coming in. I think it's hard for me to say kind of what the competitive landscape is going to really look like. But what I do think is that we're well-positioned to play well in the space, given all the capabilities we have in-house and given our experience and especially in the areas of memory enabling and memory validation. So I think we're in a very good position to play an important part in certainly CXL, the ecosystem, and an important part in the memory expansion and pooling capabilities for CXL in the future.

Des, would you want to add something?

Yes, Gary, let me just add on to what Steve said there. I think on the silicon IP side, we'll continue to see our traditional competitors, Synopsys, Cadence there on the IP side. On the chipset side, traditionally, on the memory interface buffer chip side we've had our traditional competitors there. But we're seeing new companies coming in to this space such as Marvell. Microchip has invested as well, as well as some newer start-up type of companies such as Astera Labs. So it's clear to us with the size of this market, we're going to see increased competition based upon that. But you definitely see much more diverse competition on the chipset side, Gary.

Okay. We're running up against time and -- but before we close, I wanted to ask you, Steve. Is there anything we missed? Is there anything that you wanted to highlight that we haven't covered yet?

Not that I can think of. I think we covered a lot of good ground today. I think it is a very exciting technology. It's one of those things that they don't come along that often. And so part of why there's so much excitement is because I think people can see both the way that CXL addresses the many needs that are going on in servers in the data center. And then just the fact that there's a chance now to change the direction of architectures. And so that's always really exciting when you get a chance to see the opportunity for large-scale changes. So we're very excited, and it's for the reasons we talked about. And yes, we're really looking forward to the future and what CXL will bring.

Okay. Steve and Des, on behalf of Aaron, I wanted to thank you for the time that you spend here with us and enjoy your weekend.

Okay, thanks very much.

Thanks, guys. Thank you so much.