Rambus Inc. (RMBS) Earnings Call Transcript & Summary

Hi. My name is Lou Ternullo, and I'm part of the product marketing team for the Rambus IP Group. Today, I'm going to talk to you about accelerating data interconnects with PCI Express 6 interface IP. I'll give you a brief overview of what I'm going to talk about. I'm going to first start to discuss the PCIe standard. The importance of the standard in PCI Express use and adoption. Then I'm going to discuss a little bit about the various application spaces where PCIe is used today. Talk a little bit about the challenges of PCI specifications for 6.0, how they differ from the prior generations and what considerations needed to be or need to be taken into account in the IP and at the system level. And then I'm going to finish up the presentation by giving you a brief introduction to what Rambus offers for PCI Express intellectual property. PCI Express and CXL in a nutshell. PCIe, PCI Express defined as peripheral component interconnect express. It's an interface standard for connecting high-speed components. It is the de facto standard today in connecting application processors or CPUs, 2 peripheral components. PCI Express is the standard today. There is more and more adoption for CXL. I'll touch a little bit on CXL in my presentation, but I'm going to focus on PCI Express. PCI specifications can be found at the PCIe seg. Website, link is below, and CXL specifications are maintained and developed by the CXL consortium, again, information on how to get to the compute Express Link is below as well. The importance of a standard is not only in the ability to design the interface protocol to a certain specification timing and so forth. But it also has to do with the ecosystem. The ecosystem is not only enabling but testing and validating to ensure interoperability in the future. One of the main reasons, rather, I should say, that PCI Express is so prolifically adopted in use, is because of the standard in conjunction with this ecosystem to enable plug-and-play type testing at the PCIC consortiums and so forth to ensure when a company that's developing a server system is buying parts, plugging them in, they're going to work. The other thing about PCI Express is that it's been so well adopted that new standards have been, I guess, I'll say, morphed from it. And by morphed I mean, they use the same exact physical layer and the protocol stack is modified slightly. Some of these standards you may have heard of are like NVMe non-volatile memory express. And the newest one that's come to light is UCIe, universal chiplet interconnect express. Now let me talk to you a little bit about where PCI Express is used today and what some of the benefits are for adopting CXL potentially in the future. Starting with the upper left on high performance computing, referring to cloud, data center and edge computing. Any type of application that you will, that uses a compute processor is referred to and is using the host portion of the PCI Express. So that is the source. And then the peripheral components, as I mentioned, plug into that to enable each of the various types of applications that I have listed here. So first, let's start with enterprise storage. So as you can see by the picture, the enterprise storage uses a front-load EDSF-form factor for SSDs, for example, what's used today in server CPUs. And the SSDs typically use standards like E3.S, which is a too high form factor for a 2U server or E1.S for a one high form factor. And that's adopted by this SNIA standard, S-nia referred to as S-nia ensure interoperability with solid-state rods. Moving over to the right of that, talk about enterprise networks, networking applications, often referred to as network interconnect cards, NICs, has evolved to what is often called today as a smart NIC. And so I want to use the Smart NIC as an example to explain. I mentioned in the previous slides, the peripheral interconnect. What PCI Express Interconnect has now evolved to is compute offload. And essentially, what I mean by that is that you're now adding in a card, not only it is just acting to connect to a peripheral, i.e., an ethernet port, but some type of compute engine that does additional compute to offload what the server CPU used to have to do. So in the case of enterprise networking, we have what's referred to as Smart NICs. Typically, they include a DPU or data processing unit. And the purpose of the data processing unit is to essentially manage the network, manage network traffic, telemetry and all those aspects that the service CPU historically had to do but now it offloads it. And so the Smart NIC market is growing very quickly and is expected to grow in the order of 20% to 25% compound annual growth rate through the middle to latter part of the 2020 decade. Moving down to the lower left corner, talk about artificial intelligence, machine learning and also inference. Artificial intelligence is the biggest buzzword for the last several years and will continue to be in the future. While researching for this presentation, I came across a number of different statistics for AI growth, if you will, and focusing only on hardware aspects. What I learned is that between 2020 and 2030, the AI hardware market, which is a large portion of which is included these accelerated cards or these interface cards plugging in vis-a-vis PCI Express is expected to grow north of 25% compounded annual growth rate. Going from roughly if my memory serves me correctly, $9 billion in 2020 to roughly $90 billion in 2030, which is a significant growth rate with respect to that. And I'll explain more about what the reason for this growth rate is, what's driving it and what the importance is of the PCIe specification and the evolution of the specification to keep up with that. Talk a little bit about test and measurement. So PCI Express, we talked about it as an interface for like a card plug-in. It's also used as a low pin count chip to chip connectivity type of interface. It's used in test and measurement for that, but it's also used -- if I can use this as an opportunity to plug the mobile space. Again, as I mentioned before, connecting anything from some processing unit, whether it's a CPU or an application processor to a peripheral device. In the case of the mobile space, it connects the APU to a modem or some type of radio device. Again, very high speed, low pin count for die size reasons, and it helps enable that as well. Back to test and measurement, the interface in addition to connectivity in the systems also to test these systems, you need to be able to test them. And so the test and measurement solutions need to keep up with these latest standards. So when new SSDs come to market, when new AI cards or smart mix come to market, they can be tested and verified and validated before shipping them to your customers. Last but not least, automotive. So in the automotive space, although ADAS is starting to be more and more prolific, ADAS is essentially artificial intelligence in the car, in the automobile. It's autonomous driving and the essence behind autonomous driving is to understand your surroundings and predict what's going to happen and to guide what to do next. And again, there is a processing unit in the car, in the automobile. And connected to it via a PCI Express interface is some type of artificial intelligence, accelerated card of sorts. Again, this is nothing new. You can go back and look at articles. I think it was a couple of years ago, NVIDIA and Mercedes announced a joint release where the NVIDIA GPU is being used in Mercedes vehicles to support autonomous driving. The other thing I also want to mention about autonomous driving or automobiles in the direction they're going in is from the perspective of communication, car-to-car communication and car to tower, and you probably heard of the term 5G and that wireless standard for your mobile phones, but it's also being adopted by automobiles to communicate car-to-car and car-to-tower to further enable data gathering for the AI engines in these vehicles. A little bit about CXL. So CXL, as I mentioned, it's a new standard, and I'll talk more about the specifics or the different types of CXL devices in the next slide. But I want to use this slide to talk a little bit about where the potential is for using CXL. Obviously, on the host side, in the CPU, enterprise storage, there's applications as well as enterprise networking and smart NIC as well as artificial intelligence or AI machine learning. The CXL interface offers an additional path to the traditional PCIe path, which has a lower latency and is based on coherent memory interface or data access. So the 3 types of CXL, not surprisingly, are referred to as type 1, type 2 and type 3. It is, again, the connection of a peripheral component, whether it's an offload compute component to a host or a processor as in a server CPU. The easiest way I'd like to explain the difference in these types have to do with the communication between the host or the paths of communication between the host processor and the devices. There's a CXL IO path, which is essentially your traditional PCI Express path, which is used to set up the device itself and kick it off and running. And then there's CXL.cache, which allows for a coherent interface between a host processor and any cash device sits on that device. And the CXL.mem, which again, enables a coherent connectivity between the host processor and any memory connected to the device itself. In the Type 2, you could see high bandwidth memory being part of that. So real quickly, briefly, we talked about in the previous slide, the different application spaces. So we talked about Smart NICs type 1 device. So Smart NICs don't typically have additional DRAM associated with it or memory, but there is a cache and that provides the ability for the processor to more seamlessly communicate with the cache. The type 2 device, again, GPUs, accelerators and so forth, and it allows, again, the CPU to communicate with the cache and/or the attached memory. The other thing I want to mention because this is a lower latency to .mem interface is a lower latency interface, it also provides provisions for that accelerated card to borrow or use on partitioned memory from main memory attached to the host processor. You've probably heard of natural language processing. It is an AI process that requires a tremendous amount of memory. And typically, more memory than can be serviced by attaching high-bandwidth memory to the accelerated car. And so using a CXL interface and an AI accelerated card for natural language processing application can give it additional access to memory that's connected to the host processor. And last but not least, we have what's referred to as the Type 3, which is essentially for memory bandwidth expansion or capacity expansion. And by expansion, I mean, being that this CXL device attaches to the PCI Express port, it does not take up any of the direct memory attach DRAM to the host processor. So all that path to direct DRAM exists. This is an additional or an expansion path. And it gives the host other opportunities to decouple the type of memory that is behind the CXL ASIC, either it could be DRAM or a storage class memory or whatever type of memory that could be most valuable for that particular system. Now let me talk a little bit about the history of PCI Express. PCI Express started almost 20 years ago -- actually about 20 years ago in 2003 with version 1, 2.5 gig transfers per lane. And almost consistently, every generation essentially doubles the bandwidth. Fast forward into where we are now. Let's look at PCIe 4, which was released in 2017 at 16 gigabit per second data rate. 2 years later, PCIe 5 was announced, running at 32 gigabit and now we're talking about PCIe 6, which was formally announced by the PCI in January of last year of 2022. And if you're reading in the press, the SIG is also looking forward to PCI Express 7, which is expected to run at a data rate of 128 gigas per second per lane. And that's expected to come out in 2025. And I want to point you to the release year column for a moment. And you see moving from 2019 to '22 to '25, essentially, we're in 3-year increments. I read an article yesterday that was dated on February 22. It was written by Toms Hardware, and it was essentially a summary of Dr. Lisa Su's presentation at the International Solid-State Circuits Conference -- and what Dr. Su was saying in her presentation is that they were tracking CPU server performance and GPU performance over time. essentially, every 2.4 years, the performance of the service CPU doubles. Every roughly 2.2 years, the performance of the GPU doubles. Now I mean, if you round up to 3, that essentially aligns with what we're seeing here for PCI Express. And again, as the server performance increases, it needs to be able to access offload compute and/or peripheral components at a higher data rate. And so it kind of tracks to what we're seeing in the increase in server CPU performance and expecting it to continue on that trend, it's not increased and aligning to where we see the PCI Express standard developing to. And again, I'll use this as an opportunity to plug the standard. The only way we can transition that quickly between the present generation of PCI Express standard to the next generation is through the standard through the ecosystem, through the enablement of the plug test and sources to ensure interoperability. So it's all connected. What were some of the goals that the SIG we're driving to when creating or generating the specification of PCI Express. So number one, as I mentioned, doubling the bandwidth, right? I mean we saw it from the previous chart that every generation doubles the bandwidth. Number 2 is backwards compatibility. You want to make sure that if you have a system that supports the latest standard, i.e., Gen 6, that if you have something that's supporting Gen 5, for example, you could still plug it in, it could still talk. And it's all the way down to 1.1. Similar reach, channel reach versus PCIe 5. Now I'll talk more about this in the upcoming slides, but this is really important from a format perspective. If the reach was dramatically changed going to generation, it's going to completely change all the tooling and everything that already exists and it's going to make the adoption that much harder. And also higher bandwidth efficiency. Again, I'll talk more about what I mean by higher bandwidth efficiency and how it was achieved. So what did this change or drive in the architecture of PCI Express 6? Well, moving to 64 gig transfer per second, and essentially moving from an NRZ, non-return-to-zero, signaling to a PAM4 or pulse amplitude modulation signal. If you're familiar with ethernet, ethernet transitioned to a PAM4 type signaling at 56 giga transfers per second, which follows suit with what we're seeing with PCIe 6 at 64 giga transfers per second. The addition of a low latency forward error correction in fact. I'll talk more about this, and I have one slide dedicated to this. But this forward air correction is in the actual controller itself. It is not part of the SerDes. The SerDes has a number of equalization devices or aspects, which I'll touch on. But this fact, this forward error correction, the need for it to implement in the controller because of some of these changes that need to happen. And it added a fixed size click in coding and the flip being based on CRC. And again, I'll talk a little bit more about what that is and the reason for that. Moving to this next slide here. So previous generations on the far left column, PCIe 6 in the center column and some comments on the right. So let's start off with the top row, the signaling. So as I mentioned, previous generations, Gen 5, in particular, used what was referred to as NRZ signaling. You could see it's essentially 2 data signals, either a 0 or a 1. And you could see that this is actually a very good eye. You have a pretty open eye and a UI with that's pretty solid around the order of 32-gigatransfers, which is what is expected for gen 5. Moving to the PAM4 signaling we see under PCIe 6, you see 3 eye diagrams translating to 4 data types, the 001, 11 and 10. And so essentially, what that means, and so I'll step back a second here. The microfrequency for Gen 5 at NRZ is the same microfrequency for Gen 6. And what that essentially means is over the same period of time, Gen 6 is transmitting as you would expect, twice as much data because of the PAM4 signaling. The second row will talk about the forward air correction. So there's no effect in PCIe5 or earlier generations, but we did add effect or the SIG had an effect into the PCIe 6 as a requirement. And the primary mechanism is to correct errors in the controller or to correct some of the errors. It's not going to catch all of them. But the purpose of the fact in the controller is to slightly improve the bid error rate. And in the next slide, I'll talk a little bit more about what the benefit of that is and what the implication of that is. We also have the data exchange interface on PCIe5 and earlier generations. The data exchange can be variable sizes across the TLP. And with PCIe 6, it's a fixed flip size, if you will, and it's 256 bytes. And this was in part required to support both the FEC and the PAM4. The FEC has to operate on a group of data and requiring the data exchange to be fixed at 256 bytes, enables the fact to work at its optimal. And the combination of using a 256 byte flip as well as the doubling of the data rate, if you will, enabled the efficiency to increase to 3x. And so 2x of that efficiency increase has to do with the data rate, 1.5 has to do with the implementation of this new flip interface to the TLP. From a power mode perspective, so all previous generations of PCI Express have various power modes, and I'll talk about what those are in an upcoming slide. PCI Express 6 added a new power state referred to as L0P. The biggest difference, and again, I'll discuss it more in an upcoming slide, is that L0P can be implemented without interrupting the flow of traffic. Historically, all other power modes, you have to actually interrupt the flow of traffic in order to implement those power modes. And then the pipe interface, Pipe5.x in Gen 5, Gen 5 was the first generation of PCI Express that had an optional pipe interface, either you refer to as LPC or low pin count or SerDes mode. And the SerDes mode essentially pulls the PCS, if you will, that was historically in the front end, the digital portion of the front end of the PHYS pulled it into the controller. And PCIe 6, using pipe 6 standard, the PCS is in the controller. And SerDes mode is communicating between the controller and the physical layer. And one of the benefits of that is now you don't have a protocol stack, if you will, in between the controller and the PHYS, you have a SerDes interface. And that allows for muxing to different types of controllers, i.e., Ethernet with PCI Express, assuming the PHYS itself supports the different types of SerDes-based standard. So it allows multi-protocols SerDes use. More easily allows the use of multiprotocol of SerDes. Now I want to talk a little bit about some of the system-level challenges. And you see a little block diagram, if you will, on the bottom right-hand corner. The vertical interconnect, it's an adding card showing the rough dimensions, if you will, or trace length of signals for PCI Express in an adding card roughly 3 to 4 inches. And then you have traditionally a motherboard with a root complex, which is typically the CPU. And that's roughly 12 to 14 inches. And this is the reach, if you will, that I was referring to as part of the requirements, the reach that was supported by PCIe 5 that needs to be supported also in Gen 6. Let's look at the table now. So moving from Gen 5 to Gen 6, using Gen 5 is kind of a primary reference, because of the PAM4 signaling, roughly 9 dB of signal was lost. And from UI timing window perspective, roughly 33% was lost. Now to translate this into more layman's terms is if you have a 32 gigabit data rate eye in PCIe 5, if you lose roughly 33% of that, now your circuitry no longer has to operate and detect signals at a 32 gig data rate, it has detected at roughly a 40 gig data rate to give you some level of indication. Now let's talk a little bit about the pad-to-pad budget loss. For Gen 5, the total budget was roughly $360. And again, we have the breakout there from roof complex or service CPU to adding card and system, roughly 9 dB 9.5 dB and 17.5 dB respectively. And what is allowed to support PCIE6 was a 32 dB total system budget pad-to-pad loss. 8 dB at the root complex and 8.5 at the adding card in roughly 15.5% at the system level. And this is all at the 16 gigahertz clock rate. In addition to the budgets, again, doubling the data rate itself has implications to it. And so with respect to the BCB with respect to the root complex package, moving to PCIe 6, you need to consider 3 to 6 dB better design characteristics for the package itself the root complex package. For what's referred to as non-root complex package return loss, i.e., the adding card, roughly 0 to 6 dB. And again, from a crosstalk perspective, you need to, again, design for approximately 6 dB better. And so all said and done, yes, the form factor, the reach is essentially the same, moving from Gen 5 to Gen 6, but the designs have to be much tighter in PCIe 6 to work. Okay. Briefly, again, I talked a little bit about the fact, and I'll address it a little bit more on this slide here. The purpose of the FLEC, as I mentioned, is to compensate for the higher error rate and dB lost at 64 gig transfers. The bit error rate for Gen 5 as a benchmark was 1e to the minus 12. Now for Gen 6, it's 1e to the minus 6. So it is a substantial reduction. And so adding the FLEC helps to achieve that, adding the FLEC as well as improving the CRC helps to provide for an improved total system uptime, if you will. And what the addition of the FLEC and the CRC enable is what's called a reduction in packet replay for bit errors. By supporting this and through the actual specification itself, a replay is actually less than 100 nanoseconds, which is not insignificant, but it's not totally detrimental to transferring from a Gen 5 to Gen 6. And you can see from the next bullet here, the CRC is stronger. The cyclic redundancy check is 8 bites for error detection, and that's across the entire flip packet. And previously in Gen 5, CRC was broken up into 2 points. The TLP was 4 bites and the data liquor packet was 2 bites. And the other requirement, again, anything you add into the data path adds latency. And yes, could the FLEC have been stronger? Yes, it could have. But if it was stronger, it wouldn't have been able to be implemented at 2 nanoseconds of additional latency. And so that was the other requirement. Keep the latency within reason with reeffect to where Gen 5 is and improve the error rate and usability for the users. A little bit about power modes now. So the PCIe 6 standard power modes, and these are also the same power modes in Gen 5. L0 is normal operation. L0S standby transmitting data in one direction. And so essentially, what you're doing is the device will be transmitting the host will be receiving. And so on the device side, the receivers turned off on the host side, the transmitter has turned off. The L1, the transceiver logic has actually turned off, reducing power, L2, all transmission disabled, but the power is still active and L3, the power is actually remote. Now you can imagine each of these states going from L0 down to L3, improve the power or reduce the power. As denoted by the little bars on the right in that table, but the exit time is also impacted as well. So obviously, normal operations, there's no impact. But if you go all the way down to power down, it's going to take much more time to come out of low power mode. Now L0P, this allows the power consumption to be proportional to the bandwidth. So what the L0P allows the system to do is now -- if you have 16 lanes, for example, and they're all running at 64 giga transfers, that's the maximum data rate traffic that can be supported. Not all system operations require full utilization of all 16 lanes of 64 giga transfers. So what the L0P allows the system to do is to reduce the number of lanes that are transmitting data. And essentially, what you're doing is by reducing the lanes, you reduce the power. I drew a bar chart on the right there where you go from 16 to 8, you effectively cut the power in half from 8 to 4, again in half and from 4 to 2, again in half. And the other aspect, as I mentioned earlier, is that this L0P can be engaged, if you will, without having to shut the interface down. It can be done without interrupting the traffic flow. And that's a huge benefit for latency of systems coming in and out of power loads. And this is new for Gen 6. Now let's talk a little bit about design considerations for PCIe Gen 6. So the IP needs to support all the specification changes. We talked about 64 gig transfers, the link rate negotiation at PAM4 signaling. So this includes the controller operating at the appropriate cost frequency with the appropriate data path to support the data transfer. It includes the physical layer supporting PAM4 signaling at 64 gig transfers and all the equalization required for that. Flip mode and non-flood -- we talked about backward compatibility and support for prior standards. Well, Gen 5 does not require flip mode, Gen 6 does. So the controller has to support both fit and non flip modes, depending on the mode of operation. The lightweight fact inclusion in Gen 6 and the new L0P power mode optimization. And if you can visualize taking your system from 16 lanes down to 2, it's the same inflow of traffic. It's the same outflow. It's just across fewer lanes. And so that internal to the controller moving into the PHYS, that traffic has to be managed. And so that has to be implemented again all the way through the controller into the physical layer. Some of the IP design needs to help scale. So the option of, again, using standard interfaces like Amba or proprietary interfaces that are typically synchronous in nature. And so if they're running at the same clock rate, the same input clock as the controller itself, you can use synchronous interfaces sometimes, they're running at different clock rates. And so asynchronous nature of those interfaces need to be supported. Customizing the core data path with and the pipe interface, it's support different peripheral clocks and data width, leveraging the PAM4 architecture for other connectivity protocols, as I mentioned, the ability to leverage multiprotocol serves. So all these, again, need to be accounted for in IP. The need for built-in RAS and security features. So from a RAS or reliability, addressability and serviceability perspective, monitoring and/or identifying when there is an error is critical so the system can implement a replay or a retry to try and get that data back, assuming that it was lost across the link itself. Replaying it could get the data back correctly. It also requires the ability to debug and monitor to collect telemetry information. And so part of this is the systems, these are very high-performance systems and their uptime is very critical. And so monitoring where these types of errors occur, when they occur, how often they occur, helps the service provider to better understand, is there something systemic? Is there something systemic in the server itself, and the traffic and the environment or whatever and be able to address that before they get severe downtimes. Also as we move into these higher interface standards, the data encryption and integrity and data encryption are also becoming much, much more important. The communication of data anywhere across any interface. Nowadays, encryption is something that is very important to be managed. And again, supporting the IDE engine as an optional block is also something that is essential to be considered for PCIe 5 and 6 in particular. A little bit about the Rambus PCIe 6 interface subsystem. So here, I'm just showing a simple block diagram of the controller and the physical layer, some of the high-level capabilities, and we've already talked about a few of them. So supporting the options for native or a standard space like an AMPA interface, the pipe 6.1 SerDes mode interface between what we sort as a PCS or what is seen here in the chart as a PCIe 5 layer, which is in the controller and the PMA, the SerDes. Flip and non flip mode, the optional IDE security engine -- and then also here, we also have the Rambus control over IP supports the capability of generating the controller, our TL4 ASIC or FPGA implementation. And so what the benefit of this is, especially in the context of leveraging a protocol in a prototype system, a prototype system using FPGA before you want to go to ASIC, the cost of going to ASICs nowadays to generating mass sets for advanced technology nodes like 5 and 3 nanometer are very expensive. And so doing some prototyping FPGA is one way to leverage that. The other way of leveraging FPGA is for software development. So again, before you actually get your silicon, the ability to leverage FPGA for software development. And the benefit of the Rambus controller IP is that it generates the exact same RTL. From a registered perspective, from a programming perspective, it's exactly the same. The only primary difference between an ASIC and an FPGA implementation RTL is there are more pipe stages that are included to support the lower clock rate of synthesis in the FPGA fabric. And again, as I mentioned, this is all supported through the configuration. On the PHYS side, it is DSP-based SFE and DFE equalizer has built in self-test for supporting various loopback modes and capabilities for testing the SerDes either in a manufacturing environment or in a system boot-up as well as what we refer to as ATPG ready. So although the logic in the PHYS is hardened, it is equipped and ready for ATPG patterns also supporting boundary scan and AC JTAG. The real-time received data eye monitoring and showing. Again, when bringing up the system and tuning the interface, this capability is invaluable, but it also allows you for debug and system should you need that. And per channel PRBS, pseudorandom binary sequence in addition to the ability for users to define their own patterns in those types of PRBS situations that you're testing your system. Okay. Coming down to the end here. I want to talk a little bit about the -- what we believe to be the Rambus advantage, the advantages of the SerDes and PCIe P that's supplied by Rambus. 50-plus ASIC, SoC design wins, over 100 million-plus systems in production, products that are actually shipping units, product units that are actually shipping. And that's a significant amount, which adds to the creating of risk reduction. Fully integrated and co-validated fine controller subsystem offering. So offering a subsystem, the controller and the physical layer together. Our test chips are developed by also integrating the controller in the PHYS when we develop a new physical layer, a new protocol stack, if you will, and test it in our validation boards that you see some of the images over there on the right. Various applications, the Rambus IP, both controller and 5 have been used in Smart NIC storage, networking line cards, 4G, 5G base stations and so by multiple customers in multiple application spaces and multiple products. And what this means for the audience is, it means that not only has it worked and is it working in all these different applications. But each of these applications uses the interface differently. And it's a way that we are learning in conjunction with our customers. And all that learning is forward retroactive, if you will. We take that learning and that gets all rolled into future products. So with 20-plus years of history cut edge development, that's a long time, a lot of learning to be rolled into present day and future products. So now rounding out the presentation. Some of the key takeaways to summarizing. PCI Express improves over PCIe 5 in various areas. We talked about the doubling of the bandwidth. We talked about the higher throughput efficiency, roughly 3x versus PCIe 5 with the implementation of the flip in coding. We talked about the new low-power mode, uninterrupted transition into this new low power mode. And we talked about architected to support the same channel reach. Again, there's no free lunch. Obviously, you have to work for it. But it is implementable that SIG did a fantastic job in ensuring the industry can adopt PCIe 6 successfully using the same essential form factors, if you will, and reach as Gen 5. Again, as a quick summary, the Rambus PCIe 6 IP benefits, over 20 years of experience in the controller architecture and development all the way back from Gen 1 in 2003 to where we are today. A tremendous amount of experience has been rolled into the products over time, the controller products and a very long history in SerDes signal integrity and power integrity and as well as pioneering PAM4 experience. Again, as indicative of the previous slide, all the different applications, the different types of sets starting with NRZ moving now into PAM4 that Rambus has developed and deployed to the market. So with that, I'd like to thank you for your time today, and I encourage you if you like to have more information on PCI Express, Gen 6 or other products that Rambus offers. Please feel free to visit us at www.rambus.com.