eMemory Technology Inc. (3529) Q4 FY2025 Earnings Call Transcript & Summary

Good afternoon, everyone. Welcome to eMemory's Fourth Quarter 2025 Webcast Investor Conference. Joining us today is our Chairman, Dr. Charles Hsu; President, Mr. Michael Ho; Head of IR, Ms. Li-Jeng Chen; and Director of the Finance Department, Mr. Joseph Hsia. The format of today's event will be as follows. First, eMemory's Chairman, Dr. Charles Hsu will give an opening remark. Afterwards, our Financial Officer, Mr. Joseph Hsia will present a review of our financial results. Following that, President Mr. Michael Ho will share our business outlook. Next, Dr. Charles Hsu will give a talk titled eMemory's technology enables AI memory systems to be high-yield reliable and secure. Then we will conclude today's conference with a Q&A session, where our management team will answer your questions. [Operator Instructions]. As a reminder, this conference is being recorded, and a webcast replay will be available after the conference is finished. For more information, please visit the company's website under the Investor Relations section. As usual, before we begin, we would like to remind everyone that today's presentation may contain forward-looking statements subject to risk factors associated with the semiconductor and IP business. Please refer to the cautionary statement on Page 3 of today's presentation. Now I would like to give the floor over to eMemory's Chairman, Dr. Charles Hsu.

Okay. Good afternoon, everyone. Looking back at the fourth quarter of last year, we achieved an impressive milestone with 18 licensing wins in the 3-nanometer defense application. In the first quarter of this year, we expect to secure an additional 3-nanometer license related to AI data center processors. As these licenses progress, our PUF, Physical Unclonable Function, royalties have moved into mass production. Most notably with our PUFrt, which is Root of Trust now integrated into the NVIDIA Vera Rubin architecture, and we expect royalty contributions to grow significantly in the second half of the year. And the era of AI inference is transforming our industry. We are seeing a surge in SRAM Repair demand driven by computing in memory, alongside an urgent need for security in Edge AI and physical AI. Looking further ahead, Google and IBM anticipate that quantum computing will be commercialized within 5 years. As governments worldwide pivot toward post-quantum cryptography, PQC, we are entering the most significant hardware security upgrade in 25 years. We are uniquely prepared for this shift. Our foundation is built on: proven track record over 130 PUF-related tape-outs to date; and also global reach of our technology, more than 700 process platforms worldwide are mass-producing wafers utilizing our technology; and also the -- our production is already a massive volume, an annual production record exceeding 9.8 million wafers, 8-inch equivalent. So this solid foundation is our most irreplaceable advantage as we integrate PUF into the global chip supply chain and establish a definitive Hardware Root of Trust. We remain profoundly confident in the company's future. Next, I would like to invite our financial officer, Joseph Hsia, to present our fourth quarter performance. Afterwards, our President, Michael Ho, will share our future outlook. Thank you.

Good afternoon, everyone. Now allow me to briefly go through our 2025 fourth quarter financial results. Our fourth quarter revenue was TWD 1.05 billion, up 10.1% sequentially and up 3.7% year-over-year. Our operating expenses for the fourth quarter was TWD 413 million, increased 2.1% sequentially but down 7.2% year-over-year. Through ongoing org and process optimization as well as AI transformation, we were able to improve our operational efficiency and that led to our overall expenses remaining broadly flat despite continued business expansion. In result, our operating income was TWD 636 million, with an increase of 15.9% compared to the previous quarter an increase of 12.3% year-over-year. Operating margin increased by 3 percentage points sequentially and increased by 4.6 percentage points year-over-year to 60.6%, reaching a record high, reflecting disciplined cost control and improved cost efficiency. Our net income amounting to TWD 563 million, up 15.6% quarter-over-quarter and 9.4% year-over-year. EPS for Q4 of 2025 was TWD 7.54. And next, let's move on to revenue breakdown by licensing and royalty. Licensing in the fourth quarter accounted for 33.1% of our total revenue, down 0.1% sequentially but up 9.9% year-over-year. Royalties in the first quarter contributed 66.9% of the total revenue, increasing 15.9% sequentially and increasing 0.9% year-over-year. For the full year of 2025, licensing increased 10.4% year-over-year and royalties increased 5.1% Y-o-Y. And with that, I will comment further on our revenue contributions by specific IPs. First of all, NeoBit, it accounted for 22.5% of the total revenue in the fourth quarter. Its licensing decreased 25.5% sequentially but increased 16.5% year-over-year, while royalty revenue increased 3.6% sequentially but decreased 7.9% year-over-year. Second, it is our NeoFuse technology. NeoFuse accounted for 58.5% of our total revenue in the first (sic) [ fourth ] quarter. Its licensing revenue decreased 22.1% sequentially but -- and 23% year-over-year. While royalty revenue increased 20.3% sequentially and 2.1% year-over-year. For PUF-based security IPs, it contributed 10.2% of our total revenue in the fourth quarter, mainly driven by licensing. Licensing revenue increased 91.7% sequentially and 45.5% year-over-year, while royalty revenue accounted for less than 1% of the total royalties. And lastly, for MTP technology, it accounted for 8.8% of our total revenue in the fourth quarter. Licensing revenue increased 4.7% sequentially and 29.8% year-over-year, while royalty revenue increased 13.6% sequentially and 49.9% year-over-year. And for the entire year of 2025, NeoBit licensing revenue increased by 16.1% year-over-year and royalty increased by 2.5%. And for NeoFuse, the licensing revenue increased by 0.7% and royalty increased by 5.2% year-over-year. And for PUF-based security IPs, the licensing revenue increased by 37.4% year-over-year. And lastly, for MTP technology, the licensing revenue increased by 3.6% and royalty increased by 21.7% year-over-year. And digging a little bit further into royalties breakdown by 8-inch and 12-inch wafers. For 8-inch wafers accounted for 36.2% of our royalties, up 3.3% sequentially but down 10.5% year-over-year. For 12-inch wafers, it contributed 63.8% of our royalties, up 24.5% sequentially and up 8.8% year-over-year. A total of 201 product tape-outs were completed in the fourth quarter, and we will provide more information regarding that in our management report. And next, I would like to pass the floor to our President, Michael Ho to share more about our future outlook. Thank you.

Thank you, Joseph. Good afternoon, everyone. In the following section, I will address our future outlook. For licensing revenue, we expect continued growth, strong growth driven by increase in both the number of licenses and the average license price across our foundry and fabless customers. For royalties, growth is accelerating, driven by the ramp-up of mass production across various applications, higher ASP from the advanced nodes, additional PUF-related royalties and higher royalty rates from the MTP-related IPs. New application ramp-up include: mobile, RF ICs for U.S.-based smartphone modem platforms; automotive, ADAS, networking-related applications, ISP and LiDAR; cloud AI, BMC, SSD controllers, networking-related applications, CXL controllers and DIMMs; edge and endpoint, embedded controller for notebook and PCs as well as security application for various smart devices including printer cartridges using the embedded PUF for anti-counterfeiting. IP and security platforms. One, OTP, advanced GAA OTP IP development with leading foundries, extending towards sub 3-nanometer nodes. RRAM, embedded RRAM platform with key foundries and IDM for FinFET, BCD and automotive applications. NeoFlash, deployment across foundries for BCD and mixed-signal process in 12-inch fabs. Security IP. PUF-PQC achieved NIST FIPS 205 and SP 800-208 certification, reaching a milestone in comprehensive Post-Quantum Cryptography protection. For security ecosystem expansion, chiplet security, end-to-end authentication and supply chain-trust for advanced packaging. CPU platform collaboration, PUF-based security Root of Trust integrated with major CPU platforms. Automotive and health care, PUF-based HSM servers supporting secure OTA and privacy protection. This concludes my comments. Next, I will pass the time to Charles. Thank you.

So let's watch a video first. [Presentation]

Okay. So as you can -- have seen in the video, this is just one clear example of how our IP can power AI in reliable and efficient manners and particularly to overcome current pain point encountered by using current technologies such as eFuse or AI implementations. Thus, to follow, I would like to present to you a more comprehensive view of eMemory's technologies and how we can enhance reliability and security across various memory architectures. In today's AI-driven world, memory system face 3 critical challenges; achieving high yield advanced node process nodes, ensuring reliability under extreme workloads, the maintaining robust securities. And eMemory addresses all 3 through our innovative logic NVM and PUF-based security solutions. Let me walk you through how our technology enables the AI memory ecosystem from on-package memory all the way to a system-level storage. As the heart of eMemory is our logic NVM technology, that is nonvolatile memory built using standard logic fabrication processes. First, onetime programmable memory, we call it OTP. This includes our NeoBit mainly on 8-inch wafers for mature nodes and NeoFuse on 12-inch wafers, mainly for both mature and also advanced nodes. And OTP is a programmable once and they cannot be altered, perfect for storing permanent data. And the second is the multiple-time programmable memory, which is MTP. Our NeoEE, NeoMTP and the NeoFTP solutions allow reprogramming multiple times, offering flexibility for firmware updates and also configuration changes. And third is flash memory, with our NeoRRAM and NeoFlash product, providing the highest rewrite endurance for code storage and executions. Together, they can be used in a wide range of critical applications. For instance, we use OTP to repair defective memory cells in DRAM and SRAM, restore faulty pixels in image sensors and trim analog circuits to meet specifications. These directly translate to higher manufacturing yield and lower cost. And for MTP and Flash, which enable on-chip code storage and also execution, eliminating dependency on external memory. They also support product version control and post-manufacturing customizations. And for security applications, OTP provides the foundation for storing unalterable hardware key, the root of trust for any secure systems. Once programmed, these keys cannot be modified even by sophisticated attacks. And compared to traditional non-volatile memory, logic nonvolatile memory possesses several advantages. In terms of manufacturing complexity, traditional NVM requires 10 or more additional masks beyond the standard logic process. That is more than tens of actual manufacturing steps. And our logic NVM, no additional mask needed, which make it a dramatically simpler process. And those extra process steps in traditional NVM also means longer manufacturing cycle and significantly higher costs. And our logic NVM use the same equipment, comparable process flow, resulting in substantially lower costs. And for complex processing results in the lower yield, the traditional NVM suffers from this. And the logic NVM built on mature, standard logic process typically maintains a high yield even at advanced nodes. And a shorter development cycle is also a major advantage of logic NVM. Traditional NVM requires the development of a new transistor model, extensive R&D and a lengthy testing before its deployment. But the logic NVM uses existing logic process and the model, which can be integrated and deployed rapidly without reinventing the wheel. And for the scalability is also critical for future implementation. The traditional NVM has limited expansion capacity due to a requirement of new equipment investments. However, logic NVM is highly expandable, no new equipment needed due to its logic process compatibilities. We have noticed a major chip manufacturer increasingly adopting logic NVM. And it is not just because it's better, it is also economically essential at advanced process nodes. Okay. Now let me introduce our second core technology, which is PUF-based hardware security. PUF stands for physically unclonable functions. And in fact, our anti-fuse PUF, NeoPUF was developed from our OTP and serves as the foundation of our security IP solutions. Thinking of PUF as silicon fingerprint just as no 2 human fingerprints are identical, no 2 chip produce the same PUF signature, even chips from the same wafer. This hardware key is essentially invisible to attackers, making it extremely difficult for them to extract or clone. And during the past 6 years, we have developed several security IP based on this foundation. For root of trust, our secure OTP store immutable data, TRNG generates true random numbers and combined with new NeoPUF, our PUFrt IP provides chip-unique ID and the keys, establishing well-anchored trust foundations. And by integrating with the crypto-processors, we offer PUFcc for cryptographic coprocessing and PUFhsm for hardware security module, enabling secure key management and cryptographic operations. And in terms of cryptography, we support a comprehensive suite of cryptographic algorithms, traditional standards like RSA, ECC, AES, and SHA as well as PQC for post-quantum cryptography, and many others, providing complete cryptographic coverage for any security requirement. Our solutions have achieved multiple critical certifications. For post-quantum cryptography, we have NIST CAVP certification covering FIPS 203, 204 and 205 plus SP 800-208. And for random number generation, we have also achieved NIST CAVP and ESV verifications. And for platform security, our solutions are PSA Level 2 ready and Level 3 root of trust certified. Additionally, we hold SESIP Level 3 certification for IoT security evaluation. This comprehensive certification portfolio ensure our solution meet the most stringent security requirement across all major industries. Altogether, this security approach that have been validated can provide in-depth defense network to secure modern systems. And with our security IP in mind, now let me show you how our technology enables the entire AI memory architecture hierarchies. SRAMs are the fastest caches embedded directly in GPU, TPU and the NPU of AI accelerators. At advanced nodes like 3-nanometer and below SRAM cells are extremely sensitive to manufacturing variations. With the ability to repair defective SRAM, HBM and DRAM cells, our OTPs dramatically improve SRAM yield and the lower the cost of the chips. And for high bandwidth memory, HBM, are on-package 3D stacked DRAM, providing massive bandwidth for AI training and inference. HBM stack can be 8 or 12 or even 16 layers high. And since a single defect can compromise the entire stack, embedded memory repair ensures stack integrities. Our OTP can endure thermal and also electrical stress, and thus guarantees long-term data memory retention and also operational stability under extreme AI workloads. And then for server DRAMs include GDDR6/7 and the emerging SOC advanced memory module and DDR5 standards also benefit from our embedded memory repair solution by OTP, whereas our MTP enable flexible memory management for DIMM configurations in DDR5 and the SOC advanced memory module standards. With these IP, we enable cost-effective AI chip mass production. When there are millions of AI server modules, a few percentage points of yield improvement translates to hundreds of millions in cost saving across the industries. And for CXL memory, which represents the future of data center memory architecture where memory pooling and disaggregation happen at the infrastructure level. Since CXL memory pool are assessed by the hundreds of servers, our PUFrt security solution is critical here without proper security, data leakage becomes a critical risk. PUFrt enables multi-tenant data isolation, ensuring that when multiple customers share the same physical memory infrastructure, their data remains cryptographically separated. And for the storage memory, our PUF-based security solution protects data storage within NVMe and the SSD controllers to safeguard AI models, which can be worth millions in development costs and for proprietary data. Lastly, let me reemphasize the key message here: Our IP and the technologies provided by our company, e-memory and PUFsecurity are AI memory system-enabling technologies. In summary, with our technology, AI memory system achieved 3 critical goals simultaneously. First is high yield which is necessary for economic AI chip production at advanced nodes. The second is high reliability, which is required for the AI inference workloads in mission-critical applications. And the third is high security demanded by the enterprise and the cloud AI deployment with multi-tenant environments. So this is what makes the AI system truly scalable and deployable in production environments. And this is what I would like to share with you today. Thank you for listening. And the next, I will enter the Q&A session.

Thank you, Charles. This concludes our prepared statement. We will now begin the Q&A session. [Operator Instructions]

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[Interpreted] Our first question, is the company continues to highlight growth in foundry and design lines. With foundries expanding capacity and our TAM increasing, why hasn't our royalty revenue growth outperform the foundries. Joseph, please?

Actually the expansion of TAM does not translate immediately and proportionally into our royalty revenue as there is an inherent time lag between the 2, whether it is technology licensing to the foundry side or design licensing to the chip customers, the cycle from contract signing to design-in to customer mass production and eventually to our royalty revenue recognition typically takes time and especially for advanced nodes and more complex applications. Over the past 2 years, while industry growth was concentrated in advanced nodes, many of our licenses were still in the design and integration phase and had not yet reached high-volume production. Currently, our penetration rate among major foundries 12-inch capacity is around 1.4%. And to date, we have built a solid pipeline with more than 100 tape-outs at 16-nano and below. And these designs will gradually move into mass production, and we do see meaningful room for further royalty revenue growth.

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[Interpreted] Given the rising memory cost that MediaTek and Qualcomm side as a headwind or consumer demand, how does eMemory view this potential impact on overall business performance. Michael, please?

This year, the revenue contribution from the major U.S. smartphone customers have primarily benefited from the increased content per device, including the following factors: one, increased content from the modem-related chips driven by broader adoption across modem modules; two, migration to more advanced process with PMIC moving from 0.13 micron to 55 micron and OLED driver IC transition from 28-nanometer to 16-nanometer, resulting in higher ASP per wafer; three, higher DDI content driven by affordable smartphones, where the number of display driver ICs has increased from 1 to 2 per device. Furthermore, we also benefit from a natural hedge in the aftermarket. Even when new smartphone sales slow down, the demand for replacement panel remains robust because every panel replacement require a new DDI. This elastic demand allow us to offset any weakness in the new device market and maintain a resilient revenue base. Thank you.

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[Interpreted] Using NVIDIA's generation platforms such as Vera Rubin as an example of industries move towards confidential computing and how were security architectures. Could you share more insights into its design in progress and commercialization time line in this area. Joseph, please?

Yes. Within NVIDIA's Vera Rubin architecture, the integration of Caliptra as hardware root of trust for [indiscernible] confidential computing has become a core design. And this actually reflects a pivotal once in 2 decade structural upgrade in hardware security. And as agentic AI demands significantly higher security, production is no longer an optional add-on, but a foundational element integrated directly into the silicon architecture. And with the production provided by Caliptra, model developers like OpenAI and Anthropic can securely deploy their multibillion-dollar models onto third-party cloud platforms because they can trust that even on external service, their model weights remain encrypted and accessible only to their authorized codes. And we have already secured multiple design wins within this framework. As we deepen our collaboration with global CSPs, our security IP will support the evolving requirements for hardware trust and confidential computing in the upcoming Caliptra 2.0. And combined with the essential demand for SRAM repair in inference chips, we do expect that our penetration within the AI server market will continue to expand.

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[Interpreted] Given that 3-nanometer products currently in mass production have not yet contributed to royalty revenue, how should we think about the adoption trajectory at 3-nanometer going forward? What are the key drivers that support future penetration? Michael, please?

It's common for the initial wave of 3-nanometer SoCs in mass production to utilize design legacy from previous generation as customers prioritize a fast time to market. However, we are seeing a clear shift for the next wave of 3-nanometer applications. As designs become increasingly compressed and security requirements more stringent, customers are moving toward proven validated and highly integrated IPs. They need system-level security solutions that can be seamlessly integrate into their advanced architectures. This is precisely where our competitive advantage lies, offering a silicon-proven security foundation that reduce design risk and accelerate deployment for our customers.

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[Interpreted] Could you share an update on customer adoption progress for post-quantum cryptography? And Joseph, please?

Yes. Our PUF-based PQC hardware security solution has successfully met NIST FIPS 205 and SP 800-208 standards. It covers critical applications such as key exchange and digital signatures. And our technology now fully complies with NIST currently defined core PQC specifications and is ready for commercial adoption. And in terms of application progress, our PQC solutions have already been adopted by several survey-related chip customers. And these designs utilize our IP to meet NIST compliant post-quantum security requirements and serving as a critical component of the overall hardware root of trust within the high security systems.

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[Interpreted] We've discussed how post-quantum cryptography will drive demand for our security solutions. Do you foresee a trend toward localization in this field where, for example, the U.S. mandates the use of domestic IP providers while China does the same. Joseph, please?

Yes. Regarding the localization of security solutions. It is quite important to note that commercial electronics are part of the global market. For data to be interoperable across borders, security applications might adhere to the same unified standards. And currently, the global benchmark for security algorithm is primarily set by NIST in the U.S. And our PUF-based security solutions provide high integrity hardware security that aligns with these international standards. This is why we have a robust customer base in both the U.S. and China because their end products are designed and ultimately sold in the global market. Thank you.

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[Interpreted] Could you please provide a detailed explanation of your agreement with DARPA. If DARPA adopts eMemory solution, will DARPA supplier also adopt these solutions? If so, how does eMemory proceed with such business opportunities? Joseph, please?

Yes. When our technology is adopted within DARPA programs, it indicates that the solution has undergone a practical validation in high security systems, covering key requirements such as hardware root of trust, key protection and system integration. And these programs typically establish reference security design frameworks that enable relevant system suppliers or ecosystem partners to evaluate and consider for their subsequent projects. And in practice, when these suppliers claim products for applications such as defense, aerospace and other high-security infrastructure, they often prioritize architectures that have already been validated through existing DARPA programs. And this would help reduce both of their design and qualification risk.

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[Interpreted] Regarding the trending topic of CPO refer to cold-packaged optics, will your IPs be required for these types of optical communication solutions? And Joseph, please?

Yes. We already have customers adopting our solutions for nano chips. And we also have start-up customers that were recently acquired by industry leaders who have also adopted our solutions. And as data transmission speeds accelerate to 800 gig and even 1.6 tera, the precision required for optical electrical conversion becomes extremely high. And in the field of CPO, our OTP acts as both a digital ID and the precision calibration profile. And there are 4 core reasons why OTP is essential for CPO from our point of view. First is precision calibration. Since every silicon photonic chips has a slight manufacturing variance, our OTP stores laser power and wavelength parameters to ensure that each chip achieves their peak transmission performance. And second is security and authentication. CPO modules are high-value components for AI data centers, and we provide unique IDs and secure boot solutions that will prevent hardware counterfeiting and also ensure the integrity of firmware execution. And third is optimized configuration. CPO modules contain multiple complex components and our OTP record hardware revisions and default parameters such as equalization settings, allowing the system to automatically recognize and optimize device up and startup, which will significantly reduce the system integration complexity. And last is the space efficiency and reliability. Space is extremely limited in CPO packaging. And unlike traditional external ecomms, our OTP is integrated directly into the chip. And this not only saves critical work space, but also ensures data remains permanent and tamperproof. Thank you.

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[Interpreted] According to Jensen Huang chip iteration cycles have shortened from 2 years to just 1. Is this trend a net positive or negative for the company? Joseph, please?

All right. Well, this is actually a very positive trend for us as a provider of [ IP ]. our solutions need to be processed, qualified before it can be adopted by fabless customers. And in the past, for chips manufactured on the foundry's most advanced nodes, completing our IP validation in time for the first wave designs was often quite challenging. So as a result, adoption typically occurred when customers migrate from the previous process node. And now as customers' migration cycles are accelerating, the likelihood of their IP replacement also increases and the transition to the next generation can also happen faster. In addition, with chiplet-based architectures, even if the compute die moves into the most leading-edge nodes such as 2 nano or IP can be introduced earlier through a 3-nano triplet and integrate it into the main system via advanced packaging. Thank you.

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[Interpreted] Could you update us on collaboration with ARM. Charles, please?

Our collaboration with Arm has evolved from a pure IP licensing model into broader ecosystem collaboration. On the technical side, we align our hardware root of trust with Arm-based security subsystems and reference designs to support confidential computing in edge AI and cloud data center. At the same time, we continue integrating OTP and the PUF technologies on advanced node platform to meet the system-level security needs.

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[Interpreted] Do you have any ASIC customers currently integrating our IPs? And what are the specific applications, Michael, please?

We have successfully secured multiple ASIC design wins with several key projects already moving into advanced nodes. Our IPs are being integrated into critical designs such as AI accelerator, CPU ISP and high-speed interface like SerDes specifically targeting high-performance application in AI and HPC. Furthermore, we continue to expand the adoption and application of our IPs across advanced process platforms through strategic collaboration with our ASIC design service partner. This collaborative approach allow us to scale our presence and capture the growing demand in the high-end application market.

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[Interpreted] In the context of global supply chain realignment, how does the company view future business opportunities with Chinese foundries and their overall contribution? Joseph, please?

Actually, our technology is licensed to foundries and IDMs worldwide and extending far beyond just China and Taiwan. Both U.S. domestic semiconductor companies and major global foundries with manufacturing sites in the U.S. utilize our IPs. And as the demand for advanced nodes and security integrated platforms continue to surge, we do believe this broad geographical presence position us favorably to capture these growth opportunities.

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[Interpreted] Who are your main competitors in the security IP market? And how does your competitiveness compare to theirs? Joseph, please?

Yes. When looking at this landscape, we see 3 other main players who are Rambus, Cadence, who entered the market through the acquisition of Secure-IC and Synopsys. For Rambus and Cadence, they do excel in the software encryption and protocols, whereas we focus on hardware physical layer. Because of this, our role are often complementary. And in fact, they are our potential customers. And for Synopsys and there is SRAM PUF technology. Our NeoPUF has a clear advantage in terms of physical stability. We are fully aligned with Caliptra hardware standards and most importantly, our new PUF doesn't require complex error correction or help data. By eliminating these extra requirements, we can significantly simplify the system architecture. And combined with our radiation-hardened reliability, our PUF-based security IPs remain the top choice for high-security applications. Thank you.

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[Interpreted] TSMC is reducing its mature node capacity. This means we are losing that market segment entirely. Joseph, please?

Yes. We observed that the foundries are engaging in a strategic reallocation of capacity rather than a simple reduction in the mature node capacity. And many customers are migrating to advanced platforms because of this. For example, we're seeing transition of PMIC from 8-inch to 12-inch wafers or leveraging other fab capacity. And this shift has no material impact to our customers' production or on our business. And in fact, we do believe that this kind of disciplined capacity management actually helps stabilize the supply and demand for mature node capacity, ultimately will foster a more favorable pricing environment for us.

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[Interpreted] Have there been recent price hike for mature nodes? What is our outlook on foundry pricing? Joseph, please?

As major foundries adjust their capacity and tighten supply for mature nodes, we're actually hearing from our customers about the potential increase of mature node wafer price. However, the extent of such price adjustment will depend on specific foundries pricing strategy and also the utilization rates. But compared to the previous period of price erosion, the current trend of price stabilization and potential recovery is actually quite positive for our royalty revenue from our point of view.

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[Interpreted] Will PUF become the market mainstream in the foreseeable future compared to current security solutions? What specific problems does it solve that make it a must-have for chip designers? Charles, please?

Our PUF technology serves as a unique ID and secure key. Beyond its current role in AI accelerators and data center security, this is becoming essential for the expansion of Edge AI and Physical AI. As we move toward an autonomous world, every autonomous device will require a unique identity and its own cryptographic keys to protect both data and assets. We are providing the foundation trust for this future.

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[Interpreted] As AI tools are reshaping the software industry, do you see any comparable impact or structural change emerging in the semiconductor IP industry? Joseph, please?

Yes, we believe that the IP industry is fundamentally different from pure software services. Regarding AI, we see as an enabler instead of a disruptor. While AI can optimize workflow, it cannot replicate our core value, which is the invention of the underlying transistor technology. And our mode is built on patented innovations and also decades of process know-how and the silicon proven track record. And these are the foundational assets rooted in the long-term trust and physical engineering. And these are the things that AI tools alone cannot simply replace. And as we move into advanced nodes, the requirements for things like reliability, for yield, for security will become even more stringent. And this increases the industry's reliance on actual mass production experience and also platform level expertise, which creates a significant barrier to entry. So that being said, rather than diminishing the long-term value of the IP industry, we actually believe AI will further widen the gap between companies with proven silicon success and those without, and it will strengthen our competitive moat.

In the interest of time, we will begin the last questions.

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[Interpreted] Could management share what tangible results have been observed from the recent transformation initiatives? Joseph, please?

Yes. We believe our transformation must be reflected in measurable financial results. And over the past year, we have focused on optimizing our costs and processes to build a more resilient, flexible and efficient business that can better withstand market volatility. On the revenue side, as long as the foundry pricing remains stable and avoids further declines, our existing business mix is well positioned for steady growth. On the operational side, through ongoing process improvements and cost discipline, our operating margin actually improved by 3.4 percentage points last year. And this indicates that our transformation is successfully translating into tangible profitability. And with high margins and low CapEx, our business model is built for operating leverages. As we scale, we do expect efficiency gains to drive stronger earnings while maintaining financial discipline through our transformation. Thank you.

And we will begin the closing comments. And Charles, please.

Thank you very much for coming to our investment conference. And for more information about our PUF-based security IP and technology, we encourage you to visit our PUF security website at www.security.com and check out our articles and other materials. And thank you again for your patience and the support for eMemory. We can -- we will continue to work hard on technology and IP innovation and the PUF-based hardware security solution for our customers and bringing a higher return for our shareholders. Thank you.

Thank you, ladies and gentlemen. Please be advised that the conference recording will be accessible within the next 3 hours. Thank you, everyone, for joining us today. We hope you will join us again next quarter. You may now disconnect. Goodbye, and have a good day. [Portions of this transcript that are marked [Interpreted] were spoken by an interpreter present on the live call.]